Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s submission filed 12/03/2025 has been entered. Claims 1 and 3-17 remain pending in the present Office Action.
Specification
The attempt to incorporate subject matter into this application by reference to EP 3425497 in paragraph [0003] of the specification is ineffective because the root words “incorporate” and “reference” have been omitted (see 37 CFR 1.57(c)(1)).
The incorporation by reference will not be effective until correction is made to comply with 37 CFR 1.57(c), (d), or (e). If the incorporated material is relied upon to meet any outstanding objection, rejection, or other requirement imposed by the Office, the correction must be made within any time period set by the Office for responding to the objection, rejection, or other requirement for the incorporation to be effective. Compliance will not be held in abeyance with respect to responding to the objection, rejection, or other requirement for the incorporation to be effective. In no case may the correction be made later than the close of prosecution as defined in 37 CFR 1.114(b), or abandonment of the application, whichever occurs earlier.
Any correction inserting material by amendment that was previously incorporated by reference must be accompanied by a statement that the material being inserted is the material incorporated by reference and the amendment contains no new matter. 37 CFR 1.57(g).
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “digital to analog converting, DAC, module” in claims 1, 3, and 8; “analog to digital, ADC, module” in claims 1, 8, and 14; and “analog to analog converting, AAC, module” in claim 4.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
For clarity of the record, the Examiner would like to point to claims 1 and 8 which disclose the DAC module and ADC module are executed by a classical computer, and claims 4 and 10, which disclose the AAC module is executed by the classical computer.
Claims 1 and 8 recite “a digital to analog converting, DAC, module, […] configured to convert a quantum program expressed as a quantum circuit into a quantum program expressed as a temporal schedule”. Since the function of converting a quantum program as recited in claims 1 and 8 is not coextensive with a general purpose classical computer, paragraphs [0053]-[0055] of the specification are read upon to disclose an algorithm for converting a quantum circuit to a temporal schedule, in which the DAC module converts a quantum circuit into a temporal schedule by converting each quantum gate into an elementary schedule. Thus, the Examiner’s interpretation of the “DAC module, to be executed by the classical computer, configured to convert a quantum program” as recited in claims 1 and 8 is any classical computer that converts a quantum circuit to a temporal schedule by converting the quantum gates of the quantum circuit to elementary schedules. The Examiner would also like to note steps the DAC module is configured to perform in claims 6 and 16 appear to be disclosed by the algorithm for converting a quantum circuit to a temporal schedule as described in paragraphs [0053]-[0055].
Claims 1 and 8 recite “an analog to digital converting, ADC, module, […], configured to convert a quantum program expressed as a temporal schedule into a quantum program expressed as a quantum circuit”. Since the function of converting a quantum program as recited in claims 1 and 8 is not coextensive with a general purpose classical computer, paragraph [0065] is read upon to disclose an algorithm for converting a temporal schedule to a quantum circuit, in which the ADC converts a temporal schedule to a quantum circuit by converting each elementary schedule in the temporal schedule into a quantum gate. Thus, the Examiner’s interpretation of the “ADC module, to be executed by the classical computer, configured to convert a quantum program” as recited in claims 1 and 8 is any classical computer that converts a temporal schedule to a quantum circuit by converting the elementary schedules of the temporal schedule to corresponding quantum gates.
Claim 3 recites “the DAC module is configured to optimize a temporal schedule”. Claim 4 similarly recites “an analog to analog converting, AAC, module, to be executed by the classical computer, configured to optimize a temporal schedule”. Claim 14 similarly recites “the ADC module is configured to optimize a temporal schedule”. Since the function of optimizing a temporal schedule as recited in claims 3, 4, and 14 is not coextensive with a general purpose classical computer, paragraph [0073] is read upon to disclose an algorithm for optimizing a temporal schedule, in which it is stated the optimization algorithms carried out by the ADC module, DAC module, or AAC module are considered to be known to the skilled person. Thus, the Examiner’s interpretation of the ADC module, DAC module, or AAC module “configured to optimize a temporal schedule” as recited in claims 3, 4 and 14 is any classical computer that optimizes a temporal schedule according to any optimization algorithm known in the art.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 9 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 9 recites the limitation “performing a quantum program optimization algorithm on the quantum circuit to produce an optimized quantum circuit”. The Examiner was unable to find support for the limitation in the Specification. In fact, the Specification only teaches performing optimization algorithms on temporal schedules, and teaches a reason why a person would want to convert a quantum circuit to a temporal schedule and back to a quantum circuit is so that quantum program optimizing algorithms which are available in the analog quantum framework can be used on quantum programs expressed as a quantum circuit (see Spec: [0070]).
Applicant should point to specific portions of the Specification which support “performing a quantum program optimization algorithm on the quantum circuit to produce an optimized quantum circuit” or remove the subject matter from the claims.
Allowable Subject Matter
Claims 1, 3-8 and 10-17 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claims 1 and 8, the closest prior art found is Linvill (U.S. Pub. No. 2020/0027029), which teaches A computing system for executing quantum programs ([0034]-[0035]), said computing system comprising a classical computer ([0120]), an analog quantum computer (quantum annealer 110a/adiabatic quantum computer) configured to execute quantum programs expressed as temporal schedules and a digital quantum computer (quantum gate processor 110b) configured to execute quantum programs expressed as quantum circuits ([0052]-[0053], [0070], and [0081]-[0082]), wherein said computing system further comprises:
a digital quantum processing module comprising an input interface for receiving a quantum program expressed as a quantum circuit to be executed by the digital quantum computer ([0051], [0070], [0092], [0106], [0114], and [0116]; A quantum computing resource, such as a quantum gate model computer, accepts formulations of data such as sequences of quantum logic gates ("quantum circuit"). The system provides a computing task in an appropriate formulation to the selected quantum computing resource in order to obtain results of execution of the task. The quantum computing resources 110a-110d, including quantum gate processor 110b, may be connected to a digital (i.e., "classical") computer executing quantum formulation independent solver 142 via a quantum data communication network. For router 140 to provide an appropriate formulation for a quantum computing task to quantum computing resources 110a-d, the quantum computing resources 110a-d necessarily have some input "interface".);
an analog quantum processing module comprising an input interface for receiving a quantum program expressed as a temporal schedule to be executed by the analog quantum computer ([0051], [0070], [0092], [0106], [0114], and [0116]; A quantum computing resource, such as an adiabatic quantum computer, accepts formulations of data such as Hamiltonians ("temporal schedules"). The system provides a computing task in an appropriate formulation to the selected quantum computing resource in order to obtain results of execution of the task. The quantum computing resources 110a-110d, including quantum annealer 110a, may be connected to a digital (i.e., "classical") computer executing quantum formulation independent solver 142 via a quantum data communication network. For router 140 to provide an appropriate formulation for a quantum computing task to quantum computing resources 110a-d, the quantum computing resources 110a-d necessarily have some input "interface".);
a digital to analog converting, DAC, module (FIG. 2, quantum formulation independent solver 142 comprising quantum formulation converter 202 and formulation optimizer 204), to be executed by the classical computer ([0120]), configured to convert a quantum program expressed as a quantum circuit into a quantum program expressed as a temporal schedule, said DAC module comprising an input interface for receiving a quantum circuit to be converted ([0037], [0069]-[0071] and [0076]; A sequence of quantum gates ("quantum circuit") may be received as input data 102 representing a computational task, and may be converted by the quantum formulation converter 202 to a Hamiltonian ("temporal schedule") when an adiabatic quantum computer is specified as the device type to be used, thereby functioning as the DAC module. The quantum formulation converter 202 may use a mapping of variables of one type of formulation (such as quantum gates in a sequence of quantum gates, i.e., a quantum circuit) to map the received formulation to variables of a different type of formulation (such as Hamiltonians).) and an output interface for outputting a corresponding temporal schedule generated by converting the quantum program [0077]-[0078] and [0108]; The quantum formulation converter 202 provides (outputs) the converted formulation of the input data 102 to formulation optimizer 204, which is outputted to the router for routing to the selected quantum computing resource.);
wherein a same format is used on respective input interfaces of both the digital quantum processing module and the DAC module ([0070]-[0071] and [0074]; The “format” of data representing a computational task to be inputted to a quantum gate model computer ("digital quantum processing module") may be a formulation representing a sequence of quantum gates, i.e., a quantum circuit. The quantum formulation converter 202 (part of the DAC module - quantum formulation independent solver 142) may receive input data 102 already expressed as a formulation for a particular type of quantum computing resource, such as a sequence of quantum gates, which is the “same format” as the input accepted by a quantum gate model computer.), and a same format is used on both the output interface of the DAC module and the input interface of the analog quantum processing module ([0070]-[0071]; The format of input data representing a computational task to an adiabatic quantum computer ("analog quantum processing module") may be a formulation representing a Hamiltonian. The quantum formulation converter 204 (part of DAC module - quantum formulation independent solver 142) may receive input data 102 expressed as a sequence of quantum gates and convert to a new formulation for a selected quantum computing resource. In the case the selected quantum computing resource is an adiabatic quantum computer, the converter 204 would output a formulation representing a Hamiltonian, which is a same format accepted by the input of the adiabatic quantum computer ("analog quantum processing module").);
wherein the computing system further comprises an analog to digital converting, ADC, module (FIG. 2, quantum formulation independent solver 142 comprises quantum formulation converter 202 and formulation optimizer 204. For clarity of the record, the quantum formulation independent solver 142 is disclosed as being able to convert from one formulation of a quantum task to another, and is not specific to one type of conversion, such as digital-to-analog converting or analog-to-digital converting. Therefore, the quantum formulation independent solver 142 is configured to perform the functions of both the claimed DAC module and ADC module.), to be executed by the classical computer ([0120]), configured to convert a quantum program expressed as a temporal schedule into a quantum program expressed as a quantum circuit, said ADC module comprising an input interface for receiving a temporal schedule to be converted ([0037], [0069]-[0071] and [0076]; A Hamiltonian ("temporal schedule") may be received as input data 102 representing a computational task, and may be converted by the quantum formulation converter 202 to a sequence of quantum gates ("quantum circuit") when a quantum gate model computer is specified as the device type to be used. The quantum formulation converter may use a mapping of variables of one type of formulation (such as Hamiltonians) to map the received formulation to variables of a different type of formulation (such as quantum gates in a sequence of quantum gates, i.e., a quantum circuit).)and an output interface for outputting a corresponding quantum circuit generated by converting the quantum program ([0077]-[0078] and [0108]; The quantum formulation converter 202 provides (outputs) the converted formulation to formulation optimizer 204, which is outputted to the router for routing to the selected quantum computing resource.),
wherein a same format is used on the respective input interfaces of both the analog quantum processing module and the ADC module ([0070]-[0071] and [0074]; The “format” of data representing a computational task to be inputted to an adiabatic quantum computer ("analog quantum processing module") may be a formulation representing a Hamiltonian. The quantum formulation converter 204 (part of the ADC module - quantum formulation independent solver 142) may receive input data 102 already expressed as a Hamiltonian, which is the “same format” as the input accepted by an adiabatic quantum computer.), and a same format is used on both the output interface of the ADC module and the input interface of the digital quantum processing module ([0070]-[0071]; The format of input data representing a computational task to a quantum gate model computer ("digital quantum processing module") may be a formulation representing a sequence of quantum gates, or quantum circuit. The quantum formulation converter 204 (part of ADC module - quantum formulation independent solver 142) may receive input data 102 expressed as a Hamiltonian and convert to a new formulation for a selected quantum computing resource. In the case the selected resource is a quantum gate model computer, the converter 204 would output a formulation representing sequences of quantum gates, which is a same format accepted by the input of the quantum gate model computer ("digital quantum processing module").).
Since the DAC module and ADC module of the claims are implemented by the same component of Linvill (the “quantum formulation independent solver 142”) and not by separate components that can be connected through their input/output interfaces, it follows that Linvill fails to teach wherein the DAC module is connected to the ADC module through the output interface of the DAC module and the input interface of the ADC module as recited in claim 1 and wherein the ADC module is connected to the DAC module through the output interface of the ADC module and the input interface of the DAC module as recited in claim 8.
There was no prior art, nor combination of prior art, found which taught both a digital-to-analog converting module and an analog-to-digital converting module reasonably analogous to the DAC and ADC modules recited by the claims as interpreted under 112(f) which are connected through their input/output interfaces in the configuration recited in either claim 1 or claim 8. Further, the was no prior art found which, when applied to Linvill, provided a rationale to separate the DAC and ADC functionality taught by Linvill.
Accordingly claim 1 is allowed for reciting wherein the DAC module is connected to the ADC module through the output interface of the DAC module and the input interface of the ADC module. Similarly, claim 8 is allowed for reciting wherein the ADC module is connected to the DAC module through the output interface of the ADC module and the input interface of the DAC module.
Claims 3-7 and 10-13 depend from claim 1, and thus are allowed for the same reasons presented with respect to claim 1. Claims 14-17 depend from claim 8, and thus are allowed for the same reasoned presented with respect to claim 8.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments, see page 8, filed 12/03/2025, with respect to the rejection of claim 1 under 35 U.S.C. 112(a) have been fully considered and are persuasive. The rejections of claims 8 and 14-17 under 35 U.S.C. 112(a) have been withdrawn.
Applicant argues paragraph [0094] of the publication of the instant application (U.S. Pub. No. 2023/0084607) teaches the combination of a DAC and ADC module as illustrated by Fig. 6 is merely an example of adapting a computing system which comprises both a DAC module and an ADC module, and therefore implicitly discloses other configurations of combinations of a DAC module and an ADC module in a computing system, including that set forth in claim 8.
The specification stating the ADC module and DAC module can be connected and implying other possible configurations of the combination of a DAC module and an ADC module in a single computing system is not enough to teach a specific configuration, such as that recited in claim 8.
However, the portion of paragraph [0094] (“the DAC module 24 connected to the ADC module 25, as illustrated by FIG. 6. This is transparent since the output interface of the DAC module 24 and the input interface of the ADC module use the same (analog) API”) cited by the Applicant teaches connecting the output interface of the DAC module to the input interface of the ADC module “is transparent” based on the interfaces using the same (analog) API. When considered in combination with paragraph [0071] (“both the DQP module 22 and the DAC module 24 use the same (digital) API on their respective input interfaces, such that a same quantum circuit can be fed transparently to either the DQP module 22 or the DAC module 24”) and paragraph [0085] (“the output interface of the ADC module 25 implements the (digital) API supported by the DQP module 22, such that the output of said ADC module 25 can be connected directly to the input of the DQP module 22”), which teach the output interface of the ADC module and the input interface of the DAC module use the same (digital) API, it follows that connecting the ADC module to the DAC module as recited in claim 8 may also be “transparent” as one of the other configurations implied by paragraph [0094].
Accordingly, the rejection of claim 8 under 35 U.S.C. 112(a) is withdrawn.
There was no prior art found which taught “wherein the ADC module is connected to the DAC module through the output interface of the ADC module and the input interface of the DAC module” as recited in claim 8. Accordingly, the rejection of claim 8 is withdrawn and claim 8 is allowed.
Claims 14-17 depend from claim 8, and thus are allowed for the same reasons presented with respect to claim 8. Accordingly, the rejections of claims 14-17 have been withdrawn.
Applicant's arguments, on pages 8-9, filed 12/03/2025 with respect to the rejection of claim 9 under 35 U.S.C. 112(a) have been fully considered but they are not persuasive.
Applicant alleges paragraphs [0094]-[0095] of the publication of the instant application (U.S. Pub. No. 2023/0084607) provides support for the limitation “performing a quantum program optimization algorithm on the quantum circuit to produce an optimized quantum circuit”, specifically citing “This can be useful e.g. if one wants to use quantum programs optimizing algorithms which are available in the analog quantum framework on a quantum program expressed as a quantum circuit. Hence, in such a case, it might be useful to convert the quantum circuit C into a temporal schedule H(t) on which such optimizing algorithms may be applied to produce an optimized temporal schedule H'(t), which may then be converted back into a corresponding quantum circuit C'. FIG. 6 represents schematically an example in which the optimization algorithms are implemented by the ADC module 25. It is emphasized that, in
other examples, the optimization algorithms can also be implemented by the DAC module 24 (in which case the DAC module 24 would produce directly the optimized temporal schedule H'(t))", as teaching an optimization algorithm implemented in either the ADC module and/or the DAC module.
Examiner disagrees. While the specification does teach an optimization algorithm implemented in either the ADC module and/or the DAC module, these modules are taught as performing an optimization algorithm on a temporal schedule, as disclosed in paragraphs [0020]-[0022] and [0097] of the application publication. The only optimization algorithm(s) taught in the specification are disclosed as being performed on a temporal schedule/as being available in the analog quantum framework.
Further, paragraph [0094] as cited by the Applicant teaches optimizing a quantum circuit requires converting the quantum circuit to a temporal schedule on which an optimization algorithm may be performed, and then converting the optimized temporal schedule back into a quantum circuit to produce an optimized quantum circuit. This is not the same as “performing a quantum program optimization algorithm on the quantum circuit” as recited by claim 9, since the optimization algorithm is actually performed on a temporal schedule corresponding to the quantum circuit and not performed on the quantum circuit itself.
Accordingly, claim 9 remains rejected under 35 U.S.C. 112(a) for failing to comply with the written description requirement.
Applicant’s arguments, see pages 9-14, filed 12/03/2025, with respect to the rejection of claim 1 under 35 U.S.C. 103 as being unpatentable over the combination of Linvill in view of Boothby (U.S. Pub. No. 2020/0266234) have been fully considered and are persuasive. The rejections of claims 1, 3-7, and 10-13 have been withdrawn.
Specifically, Applicant’s arguments with respect to the DAC and ADC taught by Boothby and with respect to modifying the teachings of Linvill to incorporate the teachings of Boothby are persuasive.
There was no prior art found which taught “wherein the DAC module is connected to the ADC module through the output interface of the DAC module and the input interface of the ADC module” as recited in claim 1. Accordingly, the rejection of claim 1 is withdrawn and claim 1 is allowed.
Claims 3-7 and 10-13 depend from claim 1, and thus are allowed for the same reasons presented with respect to claim 1. Accordingly, the rejections of claims 3-7 and 10-13 have been withdrawn.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
MARTIEL et al. (U.S. Pub. No. 2020/0242295) teaches a method for optimizing a quantum circuit so that all of its component gates are local (see Abstract and [0001]).
Gambetta et al. (U.S. Pub. No. 2021/0012233) teaches a method to facilitate adaptive compilation of quantum computing jobs in which a quantum device is selected based on run criteria, and the quantum program is modified, e.g., translated from a first high-level programming language to another high-level programming language, based on attributes of the selected quantum device (see Abstract and [0087]).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JENNIFER MARIE GUTMAN whose telephone number is (703)756-1572. The examiner can normally be reached M-F: 8:00 am - 4:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kevin Young can be reached at 571-270-3180. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JENNIFER MARIE GUTMAN/Examiner, Art Unit 2194 /KEVIN L YOUNG/Supervisory Patent Examiner, Art Unit 2194