DETAILED ACTION
This Office Action, based on application 17/941,592 filed 9 September 2022, is filed in response to applicant’s amendment and remarks filed 9 March 2026. Claims 1,2, and 4-22 are currently pending and have been fully considered below.
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9 March 2026 has been entered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s remarks, submitted 9 March 2026 in response to the Office Action filed 8 December 2025, have been fully considered below.
Claim Rejections under 35 U.S.C. § 102/103
The applicant traverses the prior art rejection to the claims via applicant’s ‘Art Rejections’ response alleging cited prior art fails to disclose applicant’s invention. The Office has fully reviewed applicant’s remarks; however, is not persuaded by them and thus maintains the rejections to the claims for reasons previously cited and for further reasons provided in response to applicant’s specific remarks below.
On Pages 3-4, the applicant asserts “The DISABLE signal in RAMAKRISHNAN is generated by the disable logic circuit 214 in response to redundant row signals and a group signal – it is not part of the row address at all, and it does not expand the address space. It is a binary control signal that either permits or prevents access to a specific physical row”. In response, the Office respectfully disagrees with applicant’s characterization and notes the DISABLE signal not only permits/prevents access to a specific physical row, but further enables access to a redundant row when preventing access to the specific physical row. RAMAKRISHNAN at Col 5, Lines 41-46 recites “So the function of word line driver circuit 204 may be to divide a physical row into logical rows and enable one of them based on signal DISABLE. If the row address inputs ROW.sub.13 ADDR corresponds to the faulty row, the disable logic circuit 214 may deselect the signal DISABLE before the signal ROW goes active.” While the applicant has further amended the claims to recite that (1) the ‘extra row address bit’ is appended to row address bits of the physical array and (2) utilizing the ‘extra row address bit’ as a match term to select the virtual row or the physical row, the Office asserts RAMAKRISHNAN teaches the additional limitations for reasons presented in the rejection of record. The Office asserts, based on a reading of RAMAKRISHNAN, that RAMAKRISHNAN inherently discloses that a different physical set of memory cells are accessed when the DISABLE signal is set for a given Address X versus when the DISABLE signal is not set for the given Address X. Regarding (1), the Office notes the specification is completely silent regarding the use of the term ‘append’. While the plain meaning of ‘append’ may be defined as “add as an attachment or supplement”, the Office asserts RAMAKRISHNAN’s DISABLE signal meets the limitation as the signal may be used to supplement the given address to access different sets of memory cells (accessing a ‘regular’ row versus accessing a ‘redundant’ row). Regarding (2), again, the Office asserts RAMAKRISHNAN’s DISABLE signal meets the limitation as the signal may be used to supplement the given address to access different sets of memory cells.
Claim Objections
The following claims are objected to due to informalities:
Claim 1: A comma should be inserted prior to one of the new ‘wherein’ clauses (“the at least one redundant memory element wherein the matching of the redundant row ….”) added via the amendment on 9 March 2026; this grammatical suggestion is consistent with presentation of the similar limitation in Claims 15 and 21.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 2, 15, 17, 19, 21, and 22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by RAMAKRISHNAN (US Patent 6,249,466).
Claim 1: A memory device, comprising:
a physical array (Fig 2, Memory Array 206; Col 3, Lines 34-36 – the memory array comprises ‘m’ number of physical redundant rows. The claimed ‘physical array’ is analogous to the memory array minus the ‘m’ number of physical redundant rows);
a plurality of redundant memory elements (Col 3, Lines 34-36 – the memory array comprises ‘m’ number of physical redundant rows {‘m’ number of physical redundant rows analogous to ‘a plurality of redundant memory elements’); and
a controller (Fig 2, Row Block Logic 201);
wherein the controller is configured to program at least one redundant memory element of the plurality of redundant memory elements of the memory device to a virtual addressable space by matching redundant rows of the at least one redundant memory element with virtual rows of a virtual array associated with the virtual addressable space (Col 5, Lines 33-51 – “So the function of the word line driver circuit 204 may be to divide a physical row into logical rows and enable one of them based on signal DISABLE. If the row address inputs ROW_ADDR corresponds to the faulty row, the disable logic circuit 214 may deselect the signal DISABLE before the signal ROW goes active. The disable logic block 214 may prevent the faulty logical row from getting enabled even momentarily for a read or write operation.”), wherein the matching creates additional usable rows in the virtual addressable space beyond the physical array without increasing memory device die size (Col 5, Lines 33-51 – “So the function of the word line driver circuit 204 may be to divide a physical row into logical rows and enable one of them based on signal DISABLE. If the row address inputs ROW_ADDR corresponds to the faulty row, the disable logic circuit 214 may deselect the signal DISABLE before the signal ROW goes active. The disable logic block 214 may prevent the faulty logical row from getting enabled even momentarily for a read or write operation.” Col 1, Lines 25-38; By not accessing the ‘faulty logical row’ aka the row that was a part of the ‘original’ physical array {or not one of the ‘m’ number of physical redundant rows} and instead accessing a replacement redundant row, additional rows are being accessed beyond the ‘original’ physical array) wherein the virtual addressable space comprises row addresses that are outside an address range of the physical array and wherein virtual rows of the virtual array start at a row address, such that the virtual addressable space is addressable by an extra row address bit appended to the row address bits of the physical array (Col 5, Lines 33-51 – “So the function of the word line driver circuit 204 may be to divide a physical row into logical rows and enable one of them based on signal DISABLE. If the row address inputs ROW_ADDR corresponds to the faulty row, the disable logic circuit 214 may deselect the signal DISABLE before the signal ROW goes active. The disable logic block 214 may prevent the faulty logical row from getting enabled even momentarily for a read or write operation.” Col 1, Lines 25-38; By not accessing the ‘faulty logical row’ aka the row that was a part of the ‘original’ physical array {or not one of the ‘m’ number of physical redundant rows} and instead accessing a replacement redundant row, additional rows are being accessed beyond the ‘original’ physical array; the DISABLE signal supplements the ROW_ADDR such that the ‘regular’ row or ‘redundant’ row is accessed);
wherein the controller is configured to receive a command to activate operation of the memory device to perform a transaction associated with the command associated with an address of the memory device (Col 2, Line 66 through Col 3, Line 3 – “The row logic block 201 may receive the row address inputs (ROW_ADDR) and for a given n bit row address input (ROW_ADDR), the row decoder 202 may select one of the 2^n physical rows of the memory 206 to read from or write to”);
wherein the controller is configured to determine whether an extra row address bit for the address is enabled after receipt of the command (Abstract – “The logic circuit may be configured to generate the disable signal {analogous to ‘extra row address bit’} in response to (i) one or more programmed redundant row signals and (ii) a decoded group signal) wherein the extra row address bit expands an addressable space of the memory device to include both the physical array and the virtual addressable space (Col 5, Lines 33-51 – “So the function of the word line driver circuit 204 may be to divide a physical row into logical rows and enable one of them based on signal DISABLE. If the row address inputs ROW_ADDR corresponds to the faulty row, the disable logic circuit 214 may deselect the signal DISABLE before the signal ROW goes active. The disable logic block 214 may prevent the faulty logical row from getting enabled even momentarily for a read or write operation.” Col 1, Lines 25-38; By not accessing the ‘faulty logical row’ aka the row that was a part of the ‘original’ physical array {or not one of the ‘m’ number of physical redundant rows} and instead accessing a replacement redundant row, additional rows are being accessed beyond the ‘original’ physical array);
wherein the controller is configured to determine, if the extra row address bit for the address is enabled, whether a virtual row associated with the address matches a redundant row of the at least one redundant memory element, wherein the matching of the redundant row to the virtual row comprises the controller utilizing the extra row address bit as a match term to select the virtual row backed by the at least one redundant memory element rather than a physical row of the physical array (Col 5, Lines 33-51 – “So the function of the word line driver circuit 204 may be to divide a physical row into logical rows and enable one of them based on signal DISABLE. If the row address inputs ROW_ADDR corresponds to the faulty row, the disable logic circuit 214 may deselect the signal DISABLE before the signal ROW goes active. The disable logic block 214 may prevent the faulty logical row from getting enabled even momentarily for a read or write operation.”);
wherein the controller is configured to activate the virtual row in the virtual array for the transaction based on a determination that the virtual row associated with the address matches the redundant row (Fig 2, Word Line Driver 232 presents a signal RED_WL to the memory array {selection of a redundancy row} responsive to RED_ROW and GROUP inputs); and
wherein the controller is configured to activate a physical row in the physical array if the extra row address bit for the address is not enabled (Col 5, Lines 52-67 – “The circuit 200 … may use the decoded signal (e.g. DISABLE) to disable the faulty row before the row is enabled. … “; likewise, row would be enabled without enabling the DISABLE signal).
Claim 15: A method, comprising:
programming, by utilizing a controller (Fig 2, Row Block Logic 201) of a memory device, at least one redundant memory element of a plurality of redundant memory elements of the memory device to a virtual addressable space by matching redundant rows of the at least one redundant memory element with virtual rows of a virtual array associated with the virtual addressable space (Col 5, Lines 33-51 – “So the function of the word line driver circuit 204 may be to divide a physical row into logical rows and enable one of them based on signal DISABLE. If the row address inputs ROW_ADDR corresponds to the faulty row, the disable logic circuit 214 may deselect the signal DISABLE before the signal ROW goes active. The disable logic block 214 may prevent the faulty logical row from getting enabled even momentarily for a read or write operation.”), wherein the matching creates additional usable rows in the virtual addressable space beyond the physical array without increasing memory device die size (Col 5, Lines 33-51 – “So the function of the word line driver circuit 204 may be to divide a physical row into logical rows and enable one of them based on signal DISABLE. If the row address inputs ROW_ADDR corresponds to the faulty row, the disable logic circuit 214 may deselect the signal DISABLE before the signal ROW goes active. The disable logic block 214 may prevent the faulty logical row from getting enabled even momentarily for a read or write operation.” Col 1, Lines 25-38; By not accessing the ‘faulty logical row’ aka the row that was a part of the ‘original’ physical array {or not one of the ‘m’ number of physical redundant rows} and instead accessing a replacement redundant row, additional rows are being accessed beyond the ‘original’ physical array) wherein the virtual addressable space comprises row addresses that are outside an address range of the physical array and wherein virtual rows of the virtual array start at a row address, such that the virtual addressable space is addressable by an extra row address bit appended to the row address bits of the physical array (Col 5, Lines 33-51 – “So the function of the word line driver circuit 204 may be to divide a physical row into logical rows and enable one of them based on signal DISABLE. If the row address inputs ROW_ADDR corresponds to the faulty row, the disable logic circuit 214 may deselect the signal DISABLE before the signal ROW goes active. The disable logic block 214 may prevent the faulty logical row from getting enabled even momentarily for a read or write operation.” Col 1, Lines 25-38; By not accessing the ‘faulty logical row’ aka the row that was a part of the ‘original’ physical array {or not one of the ‘m’ number of physical redundant rows} and instead accessing a replacement redundant row, additional rows are being accessed beyond the ‘original’ physical array; the DISABLE signal supplements the ROW_ADDR such that the ‘regular’ row or ‘redundant’ row is accessed);
receiving, by utilizing the controller of the memory device, a command from a host device to activate operation of the memory device to perform a transaction associated with the command associated with an address of the memory device (Col 2, Line 66 through Col 3, Line 3 – “The row logic block 201 may receive the row address inputs (ROW_ADDR) and for a given n bit row address input (ROW_ADDR), the row decoder 202 may select one of the 2^n physical rows of the memory 206 to read from or write to”);
determining, by utilizing the controller of the memory device and in response to receipt of the command, whether an extra row address bit for the address is enabled (Abstract – “The logic circuit may be configured to generate the disable signal {analogous to ‘extra row address bit’} in response to (i) one or more programmed redundant row signals and (ii) a decoded group signal) wherein the extra row address bit expands an addressable space of the memory device to include both the physical array and the virtual addressable space (Col 5, Lines 33-51 – “So the function of the word line driver circuit 204 may be to divide a physical row into logical rows and enable one of them based on signal DISABLE. If the row address inputs ROW_ADDR corresponds to the faulty row, the disable logic circuit 214 may deselect the signal DISABLE before the signal ROW goes active. The disable logic block 214 may prevent the faulty logical row from getting enabled even momentarily for a read or write operation.” Col 1, Lines 25-38; By not accessing the ‘faulty logical row’ aka the row that was a part of the ‘original’ physical array {or not one of the ‘m’ number of physical redundant rows} and instead accessing a replacement redundant row, additional rows are being accessed beyond the ‘original’ physical array);
determining, by utilizing the controller of the memory device and if the extra row address bit for the address is enabled, whether a virtual row associated with the address matches a redundant row of the at least one redundant memory element, wherein the controller utilizes the extra row address bit as a match term to select the at least one addressable physical row backed by the at least one redundant memory element rather than a physical row of the physical array (Col 5, Lines 33-51 – “So the function of the word line driver circuit 204 may be to divide a physical row into logical rows and enable one of them based on signal DISABLE. If the row address inputs ROW_ADDR corresponds to the faulty row, the disable logic circuit 214 may deselect the signal DISABLE before the signal ROW goes active. The disable logic block 214 may prevent the faulty logical row from getting enabled even momentarily for a read or write operation.”); and
activating, by utilizing the controller of the memory device, the virtual row in the virtual array for the transaction based on a determination that the virtual row associated with the address matches the redundant row (Col 2, Line 66 through Col 3, Line 3 – “The row logic block 201 may receive the row address inputs (ROW_ADDR) and for a given n bit row address input (ROW_ADDR), the row decoder 202 may select one of the 2^n physical rows of the memory 206 to read from or write to”).
Claim 21: A system, comprising:
a host device (Fig 2, Row Decoder 2022 and Redundant Row Programming Logic 208 receive input ROW_ADDR 219 from an external source {analogous to a ‘host device’}; Col 4, Lines 45-48 – “The conventional circuit 100 generally provides row address inputs from an output of an intermediate stage of the multistage regular row decoder to save area”); and
a memory device (Fig 2, 200) including a physical array (Fig 2, Memory Array 206; Col 3, Lines 34-36 – the memory array comprises ‘m’ number of physical redundant rows. The claimed ‘physical array’ is analogous to the memory array minus the ‘m’ number of physical redundant rows) and configured to store data and include an addressable space of the memory device including a physical addressable space corresponding to a physical array including physical rows and a virtual addressable space corresponding to a virtual array including virtual rows (Col 5, Lines 33-51 – “So the function of the word line driver circuit 204 may be to divide a physical row into logical rows and enable one of them based on signal DISABLE. If the row address inputs ROW_ADDR corresponds to the faulty row, the disable logic circuit 214 may deselect the signal DISABLE before the signal ROW goes active. The disable logic block 214 may prevent the faulty logical row from getting enabled even momentarily for a read or write operation.”) wherein the virtual addressable space comprises row addresses that are outside an address range of the physical array and wherein virtual rows of the virtual array start at a row address, such that the virtual addressable space is addressable by an extra row address bit appended to the row address bits of the physical array (Col 5, Lines 33-51 – “So the function of the word line driver circuit 204 may be to divide a physical row into logical rows and enable one of them based on signal DISABLE. If the row address inputs ROW_ADDR corresponds to the faulty row, the disable logic circuit 214 may deselect the signal DISABLE before the signal ROW goes active. The disable logic block 214 may prevent the faulty logical row from getting enabled even momentarily for a read or write operation.” Col 1, Lines 25-38; By not accessing the ‘faulty logical row’ aka the row that was a part of the ‘original’ physical array {or not one of the ‘m’ number of physical redundant rows} and instead accessing a replacement redundant row, additional rows are being accessed beyond the ‘original’ physical array; the DISABLE signal supplements the ROW_ADDR such that the ‘regular’ row or ‘redundant’ row is accessed), the memory device comprising;
a controller (Fig 2, Row Block Logic 201);
wherein the controller is configured to program at least one redundant memory element of a plurality of redundant memory elements of the memory device (Col 3, Lines 34-36 – the memory array comprises ‘m’ number of physical redundant rows {‘m’ number of physical redundant rows analogous to ‘a plurality of redundant memory elements’) to the virtual addressable space by matching redundant rows of the at least one redundant memory element with virtual rows of the virtual array associated with the virtual addressable space (Col 5, Lines 33-51 – “So the function of the word line driver circuit 204 may be to divide a physical row into logical rows and enable one of them based on signal DISABLE. If the row address inputs ROW_ADDR corresponds to the faulty row, the disable logic circuit 214 may deselect the signal DISABLE before the signal ROW goes active. The disable logic block 214 may prevent the faulty logical row from getting enabled even momentarily for a read or write operation.”), wherein the matching creates additional usable rows in the virtual addressable space beyond the physical array without increasing memory device die size (Col 5, Lines 33-51 – “So the function of the word line driver circuit 204 may be to divide a physical row into logical rows and enable one of them based on signal DISABLE. If the row address inputs ROW_ADDR corresponds to the faulty row, the disable logic circuit 214 may deselect the signal DISABLE before the signal ROW goes active. The disable logic block 214 may prevent the faulty logical row from getting enabled even momentarily for a read or write operation.” Col 1, Lines 25-38; By not accessing the ‘faulty logical row’ aka the row that was a part of the ‘original’ physical array {or not one of the ‘m’ number of physical redundant rows} and instead accessing a replacement redundant row, additional rows are being accessed beyond the ‘original’ physical array);
wherein the controller is configured to create at least one addressable physical row within the virtual address space based on the programming of the at least one redundant memory element with the virtual rows (Col 5, Lines 33-51 – “So the function of the word line driver circuit 204 may be to divide a physical row into logical rows and enable one of them based on signal DISABLE. If the row address inputs ROW_ADDR corresponds to the faulty row, the disable logic circuit 214 may deselect the signal DISABLE before the signal ROW goes active. The disable logic block 214 may prevent the faulty logical row from getting enabled even momentarily for a read or write operation.”);
wherein the controller is configured to receive a command from the host device to perform a transaction associated with an address of the memory device (Col 2, Line 66 through Col 3, Line 3 – “The row logic block 201 may receive the row address inputs (ROW_ADDR) and for a given n bit row address input (ROW_ADDR), the row decoder 202 may select one of the 2^n physical rows of the memory 206 to read from or write to”); and
wherein the controller is configured to utilize the at least one addressable physical row within the virtual addressable space for the transaction if the address of the memory device associated with the transaction matches a virtual address programmed to the at least one addressable physical row (Fig 2, Word Line Driver 232 presents a signal RED_WL to the memory array {selection of a redundancy row} responsive to RED_ROW and GROUP inputs), wherein the controller utilizes the extra row address bit as a match term to select the at least one addressable physical row backed by the at least one redundant memory element rather than a physical row of the physical array (Col 5, Lines 33-51 – “So the function of the word line driver circuit 204 may be to divide a physical row into logical rows and enable one of them based on signal DISABLE. If the row address inputs ROW_ADDR corresponds to the faulty row, the disable logic circuit 214 may deselect the signal DISABLE before the signal ROW goes active. The disable logic block 214 may prevent the faulty logical row from getting enabled even momentarily for a read or write operation.”).
Claim 2: The memory device of claim 1, wherein the controller is further configured to ignore the command to activate operation of the memory device if the virtual row associated with the address does not match the redundant row of the at least one redundant memory element (Col 5, Lines 52-67 – “The circuit 200 … may use the decoded signal (e.g. DISABLE) to disable the faulty row before the row is enabled. … “; likewise, row would be enabled without enabling the DISABLE signal).
Claim 17: The method of claim 15, wherein the programming of the at least one redundant memory element creates at least one physical row in the virtual addressable space, and wherein each physical row of the at least one physical row contains at least one physical page (Col 5, Lines 33-51 – “So the function of the word line driver circuit 204 may be to divide a physical row into logical rows and enable one of them based on signal DISABLE. If the row address inputs ROW_ADDR corresponds to the faulty row, the disable logic circuit 214 may deselect the signal DISABLE before the signal ROW goes active. The disable logic block 214 may prevent the faulty logical row from getting enabled even momentarily for a read or write operation.”).
Claim 19: The method of claim 15, further comprising activating, by utilizing the controller of the memory device, a physical row within a physical array of the memory device if the extra row address bit for the address is not enabled (Col 5, Lines 52-67 – “The circuit 200 … may use the decoded signal (e.g. DISABLE) to disable the faulty row before the row is enabled. … “; likewise, row would be enabled without enabling the DISABLE signal).
Claim 22: The system of claim 21, wherein the programming of the at least one redundant memory element creates at least one physical row in the virtual addressable space, and wherein each physical row of the at least one physical row contains at least one physical page (Col 5, Lines 33-51 – “So the function of the word line driver circuit 204 may be to divide a physical row into logical rows and enable one of them based on signal DISABLE. If the row address inputs ROW_ADDR corresponds to the faulty row, the disable logic circuit 214 may deselect the signal DISABLE before the signal ROW goes active. The disable logic block 214 may prevent the faulty logical row from getting enabled even momentarily for a read or write operation.”).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 4, 5, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over RAMAKRISHNAN in further view of LEE et al (US Patent 7,734,966).
With respect to Claim 4, RAMAKRISHNAN discloses the memory device of claim 1.
RAMAKRISHNAN may not explicitly disclose wherein the controller is further configured to receive information from the memory device indicating a current availability of redundant memory elements of the plurality of redundant memory elements.
However, LEE discloses wherein the controller is further configured to receive information from the memory device indicating a current availability of redundant memory elements of the plurality of redundant memory elements (Col 7, Lines 3-8 – “The size of the bad location list depends on the amount of available redundant resource”).
RAMAKRISHNAN and LEE are analogous art because they are from the same field of endeavor of storage device management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of RAMAKRISHNAN and LEE before him or her, to modify the controller circuit of RAMAKRISHNAN to include maintaining a bad location list as taught by LEE. A motivation for doing so would have been to enable classification of failed memory locations such that redundant resources may be allocated to them in a priority sequence (Abstract). Therefore, it would have been obvious to combine RAMAKRISHNAN and LEE to obtain the invention as specified in the instant claims.
With respect to Claim 5, the combination of RAMAKRISHNAN and LEE disclose the memory device of claim 4.
RAMAKRISHNAN and LEE may not explicitly disclose wherein the controller is configured to receive the information indicating the current availability of the redundant memory elements from a mode register of the memory device.
However, LEE states in the Abstract that “the present invention further provides a redundant resource allocation system, which uses a bad location list and an associated bad location list to classify failed memory location” which at least suggests the bad location list is maintained and stored in some form of memory storage. As such, with the suggestions asserted by LEE, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to have taken into consideration the combination of RAMAKRISHNAN and LEE’s explicit teachings and suggestions to have been able to modify the combination of RAMAKRISHNAN and LEE’s explicit teachings such that the bad location list is maintained and stored in a mode register with a reasonable expectation of success. A motivation for doing so is to provide a dedicated memory location for accessing the bad location list at a desired performance.
With respect to Claim 16, RAMAKRISHNAN discloses the method of claim 15.
RAMAKRISHNAN may not explicitly disclose reporting, by utilizing the memory device, a quantity of available redundant memory elements of the plurality of redundant memory elements.
However, LEE discloses reporting, by utilizing the memory device, a quantity of available redundant memory elements of the plurality of redundant memory elements (Col 7, Lines 3-8 – “The size of the bad location list depends on the amount of available redundant resource”).
RAMAKRISHNAN and LEE are analogous art because they are from the same field of endeavor of storage device management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of RAMAKRISHNAN and LEE before him or her, to modify the controller circuit of RAMAKRISHNAN to include maintaining a bad location list as taught by LEE. A motivation for doing so would have been to enable classification of failed memory locations such that redundant resources may be allocated to them in a priority sequence (Abstract). Therefore, it would have been obvious to combine RAMAKRISHNAN and LEE to obtain the invention as specified in the instant claims.
Claim(s) 6-12, 14, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over RAMAKRISHNAN in further view of WILSON et al (US PGPub 2015/0287480).
With respect to Claim 6, RAMAKRISHNAN discloses the memory device of claim 1.
RAMAKRISHNAN further discloses wherein if the supplied row address is in the virtual address space the extra row address bit is enabled (Col 5, Lines 33-51 – “So the function of the word line driver circuit 204 may be to divide a physical row into logical rows and enable one of them based on signal DISABLE. If the row address inputs ROW_ADDR corresponds to the faulty row, the disable logic circuit 214 may deselect the signal DISABLE before the signal ROW goes active. The disable logic block 214 may prevent the faulty logical row from getting enabled even momentarily for a read or write operation.”).
RAMAKRISHNAN may not explicitly disclose wherein the controller is configured to perform a post package repair to match a supplied row address to a redundant memory element of the plurality of redundant memory elements.
However, WILSON discloses wherein the controller is configured to perform a post package repair to match a supplied row address to a redundant memory element of the plurality of redundant memory element (¶[0020] – “soft post package repair can repair a memory device by remapping a defective address that had been previously remapped to a defective group of redundant memory cells”).
RAMAKRISHNAN and WILSON are analogous art because they are from the same field of endeavor of storage device management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of RAMAKRISHNAN and WILSON before him or her, to modify the controller circuit of RAMAKRISHNAN to include soft post package repair as taught by WILSON. A motivation for doing so would have been to make the memory device effective even after the memory device has been packaged and rendered defective during the packaging process (¶[0004]). Therefore, it would have been obvious to combine RAMAKRISHNAN and WILSON to obtain the invention as specified in the instant claims.
With respect to Claim 7, the combination of RAMAKRISHNAN and WILSON disclose the memory device of claim 6.
WILSON further discloses wherein the controller is configured to create an addressable physical row within the virtual address space based on performing the post package repair (¶[0038] – “the address to be accessed can be compared to the defective address to determine whether there is a soft post package repair match at block 212. When the address to be accessed matches a defective address stored in the storage element, a soft post package match is present. The defective address can be remapped to a group of functional memory cells of the memory array”).
With respect to Claim 8, RAMAKRISHNAN discloses the memory device of claim 1.
RAMAKRISHNAN further discloses wherein if the supplied row address is in the virtual address space the extra row address bit is enabled (Col 5, Lines 33-51 – “So the function of the word line driver circuit 204 may be to divide a physical row into logical rows and enable one of them based on signal DISABLE. If the row address inputs ROW_ADDR corresponds to the faulty row, the disable logic circuit 214 may deselect the signal DISABLE before the signal ROW goes active. The disable logic block 214 may prevent the faulty logical row from getting enabled even momentarily for a read or write operation.”).
RAMAKRISHNAN may not explicitly disclose wherein the controller is configured to perform a soft post package repair to match a supplied row address to a redundant memory element of the plurality of redundant memory elements.
However, WILSON discloses wherein the controller is configured to perform a soft post package repair to match a supplied row address to a redundant memory element of the plurality of redundant memory elements (¶[0038] – “the address to be accessed can be compared to the defective address to determine whether there is a soft post package repair match at block 212. When the address to be accessed matches a defective address stored in the storage element, a soft post package match is present. The defective address can be remapped to a group of functional memory cells of the memory array”).
RAMAKRISHNAN and WILSON are analogous art because they are from the same field of endeavor of storage device management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of RAMAKRISHNAN and WILSON before him or her, to modify the controller circuit of RAMAKRISHNAN to include soft post package repair as taught by WILSON. A motivation for doing so would have been to make the memory device effective even after the memory device has been packaged and rendered defective during the packaging process (¶[0004]). Therefore, it would have been obvious to combine RAMAKRISHNAN and WILSON to obtain the invention as specified in the instant claims.
With respect to Claim 9, RAMAKRISHNAN discloses the memory device of claim 1.
RAMAKRISHNAN further discloses wherein if the supplied row address is in the physical address space the extra row address bit is not enabled (Col 5, Lines 33-51 – “So the function of the word line driver circuit 204 may be to divide a physical row into logical rows and enable one of them based on signal DISABLE. If the row address inputs ROW_ADDR corresponds to the faulty row, the disable logic circuit 214 may deselect the signal DISABLE before the signal ROW goes active. The disable logic block 214 may prevent the faulty logical row from getting enabled even momentarily for a read or write operation.”).
RAMAKRISHNAN may not explicitly disclose wherein the controller is further configured to perform a post package repair to substitute a physical row in the physical array with a redundant memory element of the plurality of redundant memory elements.
However, WILSON discloses wherein the controller is further configured to perform a post package repair to substitute a physical row in the physical array with a redundant memory element of the plurality of redundant memory elements (¶[0038] – “the address to be accessed can be compared to the defective address to determine whether there is a soft post package repair match at block 212. When the address to be accessed matches a defective address stored in the storage element, a soft post package match is present. The defective address can be remapped to a group of functional memory cells of the memory array”).
RAMAKRISHNAN and WILSON are analogous art because they are from the same field of endeavor of storage device management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of RAMAKRISHNAN and WILSON before him or her, to modify the controller circuit of RAMAKRISHNAN to include soft post package repair as taught by WILSON. A motivation for doing so would have been to make the memory device effective even after the memory device has been packaged and rendered defective during the packaging process (¶[0004]). Therefore, it would have been obvious to combine RAMAKRISHNAN and WILSON to obtain the invention as specified in the instant claims.
With respect to Claim 10, RAMAKRISHNAN discloses the memory device of claim 1.
RAMAKRISHNAN further discloses wherein if the supplied row address is in the physical address space the extra row address bit is not enabled (Col 5, Lines 33-51 – “So the function of the word line driver circuit 204 may be to divide a physical row into logical rows and enable one of them based on signal DISABLE. If the row address inputs ROW_ADDR corresponds to the faulty row, the disable logic circuit 214 may deselect the signal DISABLE before the signal ROW goes active. The disable logic block 214 may prevent the faulty logical row from getting enabled even momentarily for a read or write operation.”).
RAMAKRISHNAN may not explicitly disclose wherein the controller is configured to perform a soft post package repair to substitute a physical row in the physical array with a redundant memory element of the plurality of redundant memory elements.
However, WILSON discloses wherein the controller is configured to perform a soft post package repair to substitute a physical row in the physical array with a redundant memory element of the plurality of redundant memory elements (¶[0038] – “the address to be accessed can be compared to the defective address to determine whether there is a soft post package repair match at block 212. When the address to be accessed matches a defective address stored in the storage element, a soft post package match is present. The defective address can be remapped to a group of functional memory cells of the memory array”).
RAMAKRISHNAN and WILSON are analogous art because they are from the same field of endeavor of storage device management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of RAMAKRISHNAN and WILSON before him or her, to modify the controller circuit of RAMAKRISHNAN to include soft post package repair as taught by WILSON. A motivation for doing so would have been to make the memory device effective even after the memory device has been packaged and rendered defective during the packaging process (¶[0004]). Therefore, it would have been obvious to combine RAMAKRISHNAN and WILSON to obtain the invention as specified in the instant claims.
With respect to Claim 11, RAMAKRISHNAN discloses the memory device of claim 1.
RAMAKRISHNAN may not explicitly disclose wherein the controller is configured to facilitate powering down of the memory device.
However, WILSON discloses wherein the controller is configured to facilitate powering down of the memory device (¶[0018] – “The defective address data can be stored as part of a power up sequence of a memory device, for example. The defective address data can be stored in volatile memory until the memory device is powered down.”).
RAMAKRISHNAN and WILSON are analogous art because they are from the same field of endeavor of storage device management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of RAMAKRISHNAN and WILSON before him or her, to modify the controller circuit of RAMAKRISHNAN to include placing defective address data in non-volatile memory when powering down the memory device and placing defective address data in volatile memory when powering up the memory device as taught by WILSON. A motivation for doing so would have been to place the defective address data in a performance memory when being used and place the defective address data in a memory that will retain the information when power is off in order to prevent data loss. Therefore, it would have been obvious to combine RAMAKRISHNAN and WILSON to obtain the invention as specified in the instant claims.
With respect to Claim 12, the combination of RAMAKRISHNAN and WILSON disclose the memory device of claim 11,.
WILSON further discloses wherein the controller is configured to maintain a post package repair, lose a soft package repair, or a combination thereof, after the memory device is powered down (¶[0018] – “In soft post package repair, defective address data can be stored in volatile memory of the memory device after the memory device is packaged”).
With respect to Claim 14, RAMAKRISHNAN discloses the memory device of claim 1.
RAMAKRISHNAN may not explicitly disclose wherein the controller is configured to perform post package repair by programming redundant elements to create extra usable rows in the virtual space after device fabrication.
However, WILSON discloses wherein the controller is configured to perform post package repair by programming redundant elements to create extra usable rows in the virtual space after device fabrication (¶[0020] – “soft post package repair can repair a memory device by remapping a defective address that had been previously remapped to a defective group of redundant memory cells”; ¶[0038] – “the address to be accessed can be compared to the defective address to determine whether there is a soft post package repair match at block 212. When the address to be accessed matches a defective address stored in the storage element, a soft post package match is present. The defective address can be remapped to a group of functional memory cells of the memory array”).
RAMAKRISHNAN and WILSON are analogous art because they are from the same field of endeavor of storage device management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of RAMAKRISHNAN and WILSON before him or her, to modify the controller circuit of RAMAKRISHNAN to include soft post package repair as taught by WILSON. A motivation for doing so would have been to make the memory device effective even after the memory device has been packaged and rendered defective during the packaging process (¶[0004]). Therefore, it would have been obvious to combine RAMAKRISHNAN and WILSON to obtain the invention as specified in the instant claims.
With respect to Claim 20, RAMAKRISHNAN discloses the method of claim 15.
RAMAKRISHNAN may not explicitly disclose perform, by utilizing the controller of the memory device, a post package repair to match a supplied row address in the virtual addressable space to a redundant memory element of the plurality of redundant memory elements if the supplied row address has the extra row address bit enabled.
However, WILSON discloses perform, by utilizing the controller of the memory device, a post package repair to match a supplied row address in the virtual addressable space to a redundant memory element of the plurality of redundant memory elements if the supplied row address has the extra row address bit enabled (¶[0038] – “the address to be accessed can be compared to the defective address to determine whether there is a soft post package repair match at block 212. When the address to be accessed matches a defective address stored in the storage element, a soft post package match is present. The defective address can be remapped to a group of functional memory cells of the memory array”).
RAMAKRISHNAN and WILSON are analogous art because they are from the same field of endeavor of storage device management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of RAMAKRISHNAN and WILSON before him or her, to modify the controller circuit of RAMAKRISHNAN to include soft post package repair as taught by WILSON. A motivation for doing so would have been to make the memory device effective even after the memory device has been packaged and rendered defective during the packaging process (¶[0004]). Therefore, it would have been obvious to combine RAMAKRISHNAN and WILSON to obtain the invention as specified in the instant claims.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over RAMAKRISHNAN and KLEVELAND et al (US PGPub 2013/0173970).
With respect to Claim 13, RAMAKRISHNAN discloses the memory device of claim 1.
RAMAKRISHNAN may not explicitly disclose wherein the controller is configured to predict when the plurality of redundant memory elements of the memory device will no longer be available to substitute physical rows of the physical array or be available to match with the virtual rows of the virtual array.
However, KLEVELAND discloses wherein the controller is configured to predict when the plurality of redundant memory elements of the memory device will no longer be available to substitute physical rows of the physical array or be available to match with the virtual rows of the virtual array (¶[0127-0128] – “After the diagnosis, inquiry determines whether there are sufficient resources for the expected lifespan of the part. If there are insufficient resources for the lifespan of the part, then operation provides a service report to the user … and optionally provide a quantitative status of redundant memory and/or expected lifetime”).
RAMAKRISHNAN and KLEVELAND are analogous art because they are from the same field of endeavor of storage device management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of RAMAKRISHNAN and KLEVELAND before him or her, to modify the controller circuit of RAMAKRISHNAN to include lifetime prediction as taught by KLEVELAND. A motivation for doing so would have been to provide notification to a user or administrator such that they can take appropriate action including replacement of the device. Therefore, it would have been obvious to combine RAMAKRISHNAN and KLEVELAND to obtain the invention as specified in the instant claims.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over RAMAKRISHNAN in further view of KOSEKI et al (US PGPub 2018/0018113).
With respect to Claim 18, RAMAKRISHNAN discloses the method of claim 15.
RAMAKRISHNAN may not explicitly disclose adjusting, by utilizing the controller of the memory device, a size of the virtual array as a quantity of available redundant memory elements of the plurality of redundant memory elements changes over time.
However, KOSEKI discloses adjusting, by utilizing the controller of the memory device, a size of the virtual array as a quantity of available redundant memory elements of the plurality of redundant memory elements changes over time (¶[0040-0041] – “when failure occurs to part of the storage areas in the SSD, the area becomes unusable, the storage area is set to a blocked stated, and the use thereof is stopped. At this time, it is necessary to reduce either the logical capacity or the reserve capacity corresponding to the size of the storage area being blocked”)
RAMAKRISHNAN and KOSEKI are analogous art because they are from the same field of endeavor of storage device management. Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of RAMAKRISHNAN and KOSEKI before him or her, to modify the controller circuit of RAMAKRISHNAN to include address space management as taught by KOSEKI. A motivation for doing so would have been to manage the memory device to prevent further access to portions of memory that have become unusable preventing loss of data (¶[0004]). Therefore, it would have been obvious to combine RAMAKRISHNAN and KOSEKI to obtain the invention as specified in the instant claims.
Conclusion
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/ERIC T LOONAN/Examiner, Art Unit 2137
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