DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/28/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, 6, 8 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al. [US 2020/0091376 A1], “Lim” in view of Ko et al. [US 2019/0304960 A1], “Ko”, Yin et al. [US 2013/0285248 A1], “Yin” and Chen et al. [US 2016/0087155 A1], “Chen”.
Regarding claim 1, Lim disclose a display module (Fig. 1 – 8), comprising: substrate comprising:
a substrate (Fig. 2, 220),
a device layer (221) provided at a front surface of the substrate (¶[0086] teaches and comprising an electrode pad (227), and
a driving circuit provided at a rear surface of the glass substrate and configured to drive the device layer (¶[0069] teaches a one or plurality of driving boards (not shown) which is disposed under the substrate (220));
at least one light-emitting diode (LED) (111) comprising at least one LED electrode pad (Fig. 3, 17), wherein the at least one LED electrode pad comprises a barrier layer (171); and
a junction structure (Fig. 8, 17B) provided between the at least one LED electrode pad (17) and the electrode pad (227), wherein the junction structure is in a metallically bonded state (¶[0086] teaches metal bonded), and
wherein the junction structure comprises a metallic compound of a solder layer (¶[0112] teaches bonding material is tin (Sn)), a portion of the at least one LED electrode pad (17A), and a portion of the electrode pad (227A).
Lim discloses the substrate is a printed circuit board (PCB) in resin type, a metal core (Metal Core) PCB, a flexible PCB, a ceramic PCB, or FR-4 substrate (¶[0071]). Lim does not disclose the substrate is glass. Lim does not teach explicitly teaches a thin film transistor substrate wherein a TFT layer provided at a front surface of the glass substrate, the electrode is a TFT electrode and the substrate is glass.
However, Ko discloses the details for several suitable alternative substrates used as a display device. Ko discloses a display module (Fig. 1A) comprising: a thin film transistor (TFT) substrate (¶[0032]) comprising: a glass substrate (1: ¶[0030]), a TFT layer (2: ¶[0026]) provided at a front surface of the glass substrate and comprising a TFT electrode pad (5), and a driving circuit (11) provided at a rear surface of the glass substrate and configured to drive the TFT layer (¶[0037]); at least one light-emitting diode (LED) (6) comprising at least one LED electrode pad (61) connected to the TFT electrode pad (5).
Therefore it would have been obvious to one of ordinary skill in the art before to have a suitable alternative TFT substrate configuration as taught in Ko in the device of Lim such that a thin film transistor substrate wherein a TFT layer provided at a front surface of the glass substrate, the electrode is a TFT electrode and the substrate is glass because such a modification would provide a TFT substrate with the electrical circuitry required to provide a functional device with enhance process yield and reliability (¶[0025] of Ko).
Lim teaches the first bonding layer (17B) may be formed in a mixture of a part material of the first electrode (17A) of the first light emitting device (111) and a part material of a first lead electrode (227A) of the substrate (220). Lim as modified does not explicitly disclose the junction structure comprises a portion of the barrier layer.
However, Yin discloses a first substrate (Fig. 2, 10) and a second substrate (20) are provided, wherein a surface of the first substrate is covered by a first layer (18) and a surface of the second substrate (20) is covered by a second layer (24) and a first Sn layer (28). A bonding process (Fig. 3) is performed by aligning the first and second substrates followed by bringing the first Sn layer (30) into contact with the first layer in order to form intermetallic compounds (30). As shown in Fig. 3, portions of the first layer (18) and second layer (24) react with the first Sn layer in a controlled bonding process to form the junction (30), while a second portion the first layer (18) and second layer (24) remain (as shown in Fig. 3). This bonding process results in increase bonding strength but also would further reduce gradient stress caused by the bonding because of the symmetric arrangement of the metallic film stacks (50) (¶[0019] of Yin).
Therefore it would have been obvious to one of ordinary skilled in the art before the effective filing date of the invention to use a bonding process such that only a portion of the barrier layer is bonded as taught in Yin in the device of Lim as modified such that the junction structure comprises a portion of the barrier layer, and a portion of the TFT electrode pad because such a modification would allow for an increase bonding strength of the junction (¶[0019] of Yin).
Lin as modified does the at least one LED electrode pad further comprises a filler layer provided on the barrier layer, wherein the filler layer is provided between a semiconductor layer of the at least one LED and the barrier layer.
However, Lim discloses the barrier layer (Fig. 3, 171) can be a multi-layer (¶[0103]). Further, Lim shows in an alternative embodiment additional layer can be formed between the LED and the barrier layer (Fig. 12-14). Specifically, in Fig. 14, the second layer (72) is disposed between the LED and diffusion barrier layer (75). The second layer may for example, may include aluminum (Al) or an alloy thereof (¶0124]). Lim disclose adjusting the thickness of the LED electrode layer helps with bonding efficiency with the different layers and the lead electrode may be improved (¶[0130]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to add an Al filler layer as taught in Fig. 14 of Lim in the device of Lim as modified such that the at least one LED electrode pad further comprises a filler layer provided on the barrier layer, wherein the filler layer is provided between a semiconductor layer of the at least one LED and the barrier layer, and wherein the filler layer comprises Al because such a modification of adjusting the thickness of the LED electrode layer with an additional layer would help improve the bonding efficiency with the different layers and the lead electrode (¶[0130] of Lim).
Lim as modified does not explicitly discloses a thickness of the filler layer is about 1µm to about 5µm.
However Lim does disclose the layers can be adjusted. Specifically, Lim states when the metal layers 73 and 76 having the ferromagnetism material is a multilayer in the first electrode 17, and each layer is 5 nm or more and the total thickness of the plurality of layers may be greater than or equal to 30 nm. As another example, the first electrode 17, when the metal layer having the ferromagnetism material is a single layer, may be formed to a thickness more than 30 nm (¶[0127]). Further, Lim as modified discloses an Al filler layer. Future, Chen discloses an LED device with electrode structure containing the material of the single metal reflective layer (Fig. 1, 212) includes aluminum or aluminum alloy with a thickness not less than 1 um (¶0024]). Further, 1.5-um-thick aluminum single metal reflective layer (212) (¶[0031]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to optimize the thickness of the filler layer as taught in Chen in the device of Lim as modified such that a thickness of the filler layer is about 1µm to about 5µm because optimizing the thickness of the layer will provide proper electrical connection to the display to ensure proper light-emitting efficiency (¶[[0031] of Chen). It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 3, Lim as modified discloses claim 1, Lim disclose the barrier layer (Fig. 3, 171/Fig. 8, 17A) comprises at least one from among Au, Ni, Ti, Cr, Pd, TiN, Ta, TiW, TaN, AlSiTiN, NiTi, TiBN, ZrBN, TiAlN, and TiB2, (¶[0103] teaches a first layer (171) is a diffusion barrier material, may include titanium (Ti) or chrome (Cr)) and wherein the TFT electrode pad comprises at least one from among Au, Cu, Ag, Ni, Ni/Au, Au/Ni, Ni/Cu, and Cu/Ni (¶[0105] teaches the first layer (51) of the first lead electrode (227) may be copper (Cu)).
Regarding claim 4, Lim as modified discloses claim 3, Lim disclose the solder layer comprises Sn or In (¶[0112] teaches bonding material is tin (Sn)).
Regarding claim 6, Lim as modified discloses claim 3, Lim disclose the solder layer comprises at least two from among Sn, Ag, In, Cu, Ni, Au, Bi, Al, Zn, and Ga (¶[0113] teaches at least one or an alloy having these optionally of tin, indium, bismuth agent (Bi), cadmium (Cd), lead (Pb) ).
Regarding claim 8, Lim as modified discloses claim 3, Lim as modified disclose the filler layer comprises one from among Au, Cu, Ni, and Al. (the filler layer may for example, may include aluminum (Al) or an alloy thereof (¶0124] of Lim).
Regarding claim 14, Lim as modified discloses claim 1, Lim disclose the TFT electrode pad comprises Au or Ni (¶[0105] discloses (The third layer 53 of the first lead electrode 227 is for example, gold (Au)).
Claims 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al. [US 2020/0091376 A1], “Lim” in view of Ko et al. [US 2019/0304960 A1], “Ko”, Yin et al. [US 2013/0285248 A1], “Yin” and Chen et al. [US 2016/0087155 A1], “Chen” as applied in claim 8 and 1 respectively and further in view of Batres et al. [US 2020/0176634 A1], “Batres”.
Regarding claim 9, Lim as modified discloses claim 8, Lim does not explicitly a thickness of the at least one LED electrode pad is less than or equal to 40% of a thickness of the at least one LED.
However, Lim discloses the second layer (172) may have a thickness of 30 nm or less. The first lead electrode 227A and the first bonding layer 17B of the substrate 220 may have a thickness ratio of 1:1 to 1:3.5, and the second lead electrode 229A and the second bonding layer 17B may have a thickness ratio of 1:1 to 1:3.5. (¶[0117]). Lim future disclose the layers thickness can be adjust to improve the bonding efficiency with the different layers and the lead electrode (¶[0130]). Future, Batres discloses the LED have layers with various thickness such as the height of each n-doped compound semiconductor region 32 can be in a range from 50 nm to 10 microns, such as from 200 nm to 2 microns (¶[0049]), the active region (34) can include a layer stack including, from bottom to top, a silicon-doped GaN layer having a thickness of 30 nm to 70 nm, such as about 50 nm to about 60 nm, a GaN layer having a thickness of 2 nm to 10 nm, such as about 5 nm to 7 nm, an InGaN layer having a thickness of 1 nm to 5 nm, such as about 3 nm to 4 nm, and a GaN barrier layer having a thickness of 10 nm to 30 nm, such as about 15 nm to 20 nm (¶[0056]). Batres teaches lesser and greater thicknesses can also be employed for the layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to optimize the thickness of each layer as taught in Batres in the device of Lim as modified such that a thickness of the LED electrode pad is less than or equal to 40% of a thickness of the at least one LED because optimizing the size of the device and the electrode will improve the light emission of the device at a particular wavelength (¶[0036]) while providing proper electrical connection to the display. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 10, Lim as modified discloses claim 9, Lim does not explicitly disclose a thickness of the barrier layer is about 0.05µm to about 2µm, wherein a thickness of the solder layer is about 0.4µm to about 2µm.
However Lim does disclose the layers can be adjusted. Specifically, Lim states when the metal layers 73 and 76 having the ferromagnetism material is a multilayer in the first electrode 17, and each layer is 5 nm or more and the total thickness of the plurality of layers may be greater than or equal to 30 nm. As another example, the first electrode 17, when the metal layer having the ferromagnetism material is a single layer, may be formed to a thickness more than 30 nm (¶[0127]). Future, Batres future disclose a thickness of the barrier layer (82) is about 0.05µm to about 2 µm (¶[0096] teaches a thickness in a range from 60 nm to 200 nm), wherein a thickness of the solder layer (431) is about 0.4 µm to about 2 µm (¶[0100] teaches a thickness in a range from 1.5 micron to 4 microns).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to optimize the thickness of each layer as taught in Batres in the device of Lim as modified such that a thickness of the barrier layer is about 0.05µm to about 2µm,wherein a thickness of the solder layer is about 0.4µm to about 2µm because optimizing the thickness of the layer will provide proper electrical connection to the display to ensure proper alignment between the two substrate (¶[[0036] of Batres). It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 11, Lim as modified discloses claim 1, Lim does not disclose a thickness of the TFT electrode pad is about 0.1 µm to about 1 µm.
However Batres does discloses backplane-side tin portion (443) is less than 1 micron, and preferably less than 0.1 micron (¶[0126]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to optimize the thickness of the TFT electrode layer as taught in Batres in the device of Lim as modified such that a thickness of the TFT electrode pad is about 0.1 µm to about 1 µm because optimizing the size of the electrode will improve the light emission of the device at a particular wavelength (¶[0036]) while providing proper electrical connection to the display. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 12, Lim as modified discloses claim 1, Lim discloses the pitch between pixel regions (Fig. 1, 102) in the display device having the light emitting module (1000) may be less than 1.2 mm, for example, to have in a range of 0.6 mm to 0.9 mm, and may improve the pixel density and resolution. Lim does not explicitly does not disclose an interval between LEDs adjacent to one another is about 20% to about 70% of a size of the at least one LED.
Batres discloses a display device, such as a direct view display device, can be formed from an ordered array of pixels bonded to a backplane. The LEDs are soldered to the backplane with optimized positioning such that any combination of colors within a color gamut may be shown on the display for each pixel (¶[0036] and ¶[0044]). The array of light emitting diodes (10) may be formed as a rectangular array or a hexagonal array, and each light emitting diode (10) may be formed with a maximum lateral dimension (such as the diagonal of a rectangular shape or the diameter of a circumscribing circle of a hexagonal shape) in a range from 1 micron to 60 microns, such as from 2 micron to 30 microns (¶0045]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to optimize the interval between LEDs as taught in Batres in the device of Lim as modified such that an interval between LEDs adjacent to one another is about 20 to about 70% of a size of the at least one LED because optimizing the spacing and the size of each LED will provide a sharper image from the display device (¶[0075]). It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 13, Lim as modified discloses claim 12, Lim discloses the TFT electrode pad is provided on the TFT layer (Lim modified by Ko – see claim 1).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Lim et al. [US 2020/0091376 A1], “Lim” in view of Ko et al. [US 2019/0304960 A1], “Ko” in view of Yin et al. [US 2013/0285248 A1], “Yin” in view of Tu et al. [US 2014/0186979 A1], “Tu” and Chen et al. [US 2016/0087155 A1], “Chen”.
Regarding claim 15, Lim discloses a display module (Fig. 1 – 8), comprising:
a substrate (Fig. 2, 220),
a device layer (221) provided at a front surface of the substrate (¶[0086] teaches and comprising an electrode pad (227)), and comprising an electrode pad (227), and
a driving circuit provided at a rear surface of the substrate and configured to drive the device layer (¶[0069] teaches a one or plurality of driving boards (not shown) which is disposed under the substrate (220));
a plurality of light-emitting diodes (LEDs) (Fig. 2, 111, 113, 125); and
a pair of LED electrode pads (17 and 19) provided for each LED of the plurality of LEDs (as shown in Fig. 3);
wherein each of the pair of LED electrode pads comprises a barrier layer (171 and 191),
wherein each of the pair of LED electrode pads comprises a junction structure (Fig. 8, 17B) in a metallically bonded state (¶[0086] teaches metal bonded),
wherein the junction structure (17B) comprises a metallic compound of a solder layer, (¶[0112] teaches bonding material is tin (Sn)), a portion of the LED electrode pad layer (17a), and a portion of the electrode pad (227A), and
Lim discloses the substrate is a printed circuit board (PCB) in resin type, a metal core (Metal Core) PCB, a flexible PCB, a ceramic PCB, or FR-4 substrate (¶[0071]). Lim does not disclose the substrate is glass. Lim does not teach explicitly teaches a thin film transistor substrate wherein a TFT layer provided at a front surface of the glass substrate, the electrode is a TFT electrode and the substrate is glass.
However, Ko discloses the details for several suitable alternative substrates used as a display device. Ko discloses a display module (Fig. 1A) comprising: a thin film transistor (TFT) substrate (¶[0032]) comprising: a glass substrate (1: ¶[0030]), a TFT layer (2: ¶[0026]) provided at a front surface of the glass substrate and comprising a TFT electrode pad (5), and a driving circuit (11) provided at a rear surface of the glass substrate and configured to drive the TFT layer (¶[0037]); at least one light-emitting diode (LED) (6) comprising at least one LED electrode pad (61) connected to the TFT electrode pad (5).
Therefore it would have been obvious to one of ordinary skill in the art before to have a suitable alternative TFT substrate configuration as taught in Ko in the device of Lim such that a thin film transistor substrate wherein a TFT layer provided at a front surface of the glass substrate, the electrode is a TFT electrode and the substrate is glass because such a modification would provide a TFT substrate with the electrical circuitry required to provide a functional device with enhance process yield and reliability (¶[0025] of Ko).
Lim teaches the first bonding layer (17B) may be formed in a mixture of a part material of the first electrode (17A) of the first light emitting device (111) and a part material of a first lead electrode (227A) of the substrate (220). Lim as modified does not explicitly disclose the junction structure comprises a portion of the barrier layer.
However, Yin discloses a first substrate (Fig. 2, 10) and a second substrate (20) are provided, wherein a surface of the first substrate is covered by a first layer (18) and a surface of the second substrate (20) is covered by a second layer (24) and a first Sn layer (28). A bonding process (Fig. 3) is performed by aligning the first and second substrates followed by bringing the first Sn layer (30) into contact with the first layer in order to form intermetallic compounds (30). As shown in Fig. 3, portions of the first layer (18) and second layer (24) react with the first Sn layer in a controlled bonding process to form the junction (30), while a second portion the first layer (18) and second layer (24) remain (as shown in Fig. 3). This bonding process results in increase bonding strength but also would further reduce gradient stress caused by the bonding because of the symmetric arrangement of the metallic film stacks (50) (¶[0019] of Yin).
Therefore it would have been obvious to one of ordinary skilled in the art before the effective filing date of the invention to use a bonding process such that only a portion of the barrier layer is bonded as taught in Yin in the device of Lim as modified such that the junction structure comprises a portion of the barrier layer, and a portion of the TFT electrode pad because such a modification would allow for an increase bonding strength of the junction (¶[0019] of Yin).
Lim as modified does not discloses wherein an interval between LEDs of the plurality of LEDs adjacent to one another is determined based on a minimum distance between the pair of LED electrode pads.
Tu disclose an light emitting device (LED) array (Fig. 3G, 35) connected to a circuit board (23). Tu discloses the distance between two metal layers (Fig. 4B, 260 and 262), i.e. the first distance S3, is limited to the alignment control of the bonding process between the LED array and the circuit board. The distance between two adjacent LEDs, i.e. the third distance S5 is limited by the lithography-etching process, and is smaller than 50 microns, or preferably smaller than 25 microns for reserving more area for the light-emitting stacks (¶[0056]). Optimizing the electrode spacing and the interval between each LED will provide a display device with enhanced resolution while preventing other short circuit malfunctions (¶[0056]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to optimize the interval between the LEDs as taught in Tu in the device of Lim as modified such that the interval between LEDs of the plurality of LEDs adjacent to one another is determined based on a minimum distance between the pair of LED electrode pads because optimizing the electrode spacing and the interval between each LED will provide a display device with enhanced resolution while preventing other short circuit malfunctions (¶[0056] of Tu).
Lin as modified does the at least one LED electrode pad further comprises a filler layer provided on the barrier layer, wherein the filler layer is provided between a semiconductor layer of the at least one LED and the barrier layer.
However, Lim discloses the barrier layer (Fig. 3, 171) can be a multi-layer (¶[0103]). Further, Lim shows in an alternative embodiment additional layer can be formed between the LED and the barrier layer (Fig. 12-14). Specifically, in Fig. 14, the second layer (72) is disposed between the LED and diffusion barrier layer (75). The second layer may for example, may include aluminum (Al) or an alloy thereof (¶0124]). Lim disclose adjusting the thickness of the LED electrode layer helps with bonding efficiency with the different layers and the lead electrode may be improved (¶[0130]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to add an Al filler layer as taught in Fig. 14 of Lim in the device of Lim as modified such that the at least one LED electrode pad further comprises a filler layer provided on the barrier layer, wherein the filler layer is provided between a semiconductor layer of the at least one LED and the barrier layer, and wherein the filler layer comprises Al because such a modification of adjusting the thickness of the LED electrode layer with an additional layer would help improve the bonding efficiency with the different layers and the lead electrode (¶[0130] of Lim).
Lim as modified does not explicitly discloses a thickness of the filler layer is about 1µm to about 5µm.
However Lim does disclose the layers can be adjusted. Specifically, Lim states when the metal layers (73 and 76) having the ferromagnetism material is a multilayer in the first electrode (17), and each layer is 5 nm or more and the total thickness of the plurality of layers may be greater than or equal to 30 nm. As another example, the first electrode (17), when the metal layer having the ferromagnetism material is a single layer, may be formed to a thickness more than 30 nm (¶[0127]). Further, Lim as modified discloses an Al filler layer. Future, Chen discloses an LED device with electrode structure containing the material of the single metal reflective layer (Fig. 1, 212) includes aluminum or aluminum alloy with a thickness not less than 1 um (¶0024]). Further, 1.5-um-thick aluminum single metal reflective layer (212) (¶[0031]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to optimize the thickness of the filler layer as taught in Chen in the device of Lim as modified such that a thickness of the filler layer is about 1µm to about 5µm because optimizing the thickness of the layer will provide proper electrical connection to the display to ensure proper light-emitting efficiency (¶[[0031] of Chen). It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Response to Arguments
Applicant's arguments with respect to the claims have been considered but are moot in view of the new grounds of rejection required by Applicant's amendment.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Liu [US 2020/0373282 A1] disclose a display device with a junction structure.
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PRIYA M. RAMPERSAUD
Examiner
Art Unit 2897
/PRIYA M RAMPERSAUD/Examiner, Art Unit 2897
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