DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Interpretation
The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met. The broadest reasonable interpretation of a system (or apparatus or product) claim having structure that performs a function, which only needs to occur if a condition precedent is met, requires structure for performing the function should the condition occur. The system claim interpretation differs from a method claim interpretation because the claimed structure must be present in the system regardless of whether the condition is met and the function is actually performed. See MPEP 2111.04(II). "[i]f the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out in order for the claimed method to be performed" (quotation omitted). Ex parte Schulhauser, Appeal 2013-007847 (PTAB April 28, 2016).
Claim Objections
Claim 6 is objected to because of the following informalities: a word such as “by” appears to have been omitted following the word “lower” and prior to the phrase “a larger increment” in Line 2. Appropriate correction is required.
Claim 13 is objected to because of the following informalities: a word such as “by” appears to have been omitted following the word “lower” and prior to the phrase “a larger increment” in Line 2. Appropriate correction is required.
Claim 19 is objected to because of the following informalities: a word such as “by” appears to have been omitted following the word “lower” and prior to the phrase “a larger increment” in Line 2. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “high-performance core” in Claims 1, 8, and 15 is a relative term which renders the claim indefinite. The term “high-performance” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For the purposes of evaluating prior art with respect to patentability, the Examiner has interpreted the term “high-performance core” as meaning that the first processing core has a higher performance than the second processing core.
The term “energy-efficient core” in Claims 1, 8, and 15 is a relative term which renders the claim indefinite. The term “energy-efficient” is not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. For the purposes of evaluating prior art with respect to patentability, the Examiner has interpreted the term “energy-efficient core” as meaning that the second processing core has a greater energy efficiency than the first processing core.
Dependent claims inherit the indefiniteness of their parent claims and are rejected under similar reasoning.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 5-6, 8-10, 12-13, and 15-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent Application Publication Number 2017/0212581 to Park et al. (“Park”).
In reference to Claim 1, Park discloses an apparatus comprising: a memory controller (See Figures 1 and 2 Numbers 114 and 116 and Figure 6a Numbers 206 and 610-616) coupled to a first processing core (See Figures 1 and 2 Number 106 and Figure 6a Number 604) and a second processing core (See Figures 1 and 2 Number 108 and Figure 6a Number 602), wherein the first processing core is a high-performance core (See Figure 6a Number 604 and Paragraph 33) and the second processing core is an energy-efficient core (See Figure 6a Number 602 and Paragraph 33), the memory controller comprising: a frequency optimizer (See Figure 2 Number 206 and Figure 6a Number 206 and 610-616) to receive a memory bandwidth increase request (See Figure 6a ‘Core Stall %’ and Paragraphs 34-35) and to increase an operating frequency (See Figure 6a Number 618 and Paragraphs 34-35) of a memory coupled to the first processing core and the second processing core (See Figures 1 and 2 Number 104), wherein the frequency optimizer to increase the operating frequency of the memory a larger increment if the first processing core requested the memory bandwidth increase request (See Figure 6b and Paragraphs 31-32, 34-35, and 37 [when the first processing core is executing a workload with a larger core stall time compared to the second processing core]), than if the second processing core requested the memory bandwidth increase request (See Figure 6b and Paragraphs 31-32, 34-35, and 37 [when the second processing core is executing a workload with a smaller core stall time compared to the first processing core]).
In reference to Claim 2, Park discloses the limitations as applied to Claim 1 above. Park further discloses that the frequency optimizer further to increase the operating frequency of the memory based on a weighted aggregated energy-performance preference of the first processing core and the second processing core (See Paragraphs 27 and 34-37).
In reference to Claim 3, Park discloses the limitations as applied to Claim 2 above. Park further discloses that the weighted aggregated energy-performance preference is an average of a first weight (See Paragraph 36 [adjustment factor]) times a first energy-performance preference (See Figure 6b ‘Original IB Vote’ and Paragraphs 34 and 36) of the first processing core and a second weight (See Paragraph 36 [adjustment factor]) times a second energy-performance preference (See Figure 6b ‘Original IB Vote’ and Paragraphs 34 and 36) of the second processing core, wherein the first weight provides a bigger preference to the first energy-performance preference of the first processing core (See Paragraphs 30 and 36-37).
In reference to Claim 5, Park discloses the limitations as applied to Claim 1 above. Park further discloses that the frequency optimizer further to adjust the operating frequency of the memory lower if a low memory bandwidth utilization condition occurs (See Paragraphs 30-31, 34, and 37).
In reference to Claim 6, Park discloses the limitations as applied to Claim 1 above. Park further discloses that the frequency optimizer to adjust the operating frequency of the memory lower by a larger increment if the memory bandwidth increase request was from the second processing core (See Figure 6b and Paragraphs 31-32, 34-35, and 37 [when the second processing core is executing a workload with a smaller core stall time than the first processing core]) than if the memory bandwidth increase request was from the first processing core (See Figure 6b and Paragraphs 31-32, 34-35, and 37 [when the first processing core is executing a workload with a larger core stall time than the second processing core]).
Claims 8 and 15 recite limitations which are substantially equivalent to those of Claim 1 and are rejected under similar reasoning.
Claims 9 and 16 recite limitations which are substantially equivalent to those of Claim 2 and are rejected under similar reasoning.
Claims 10 and 17 recite limitations which are substantially equivalent to those of Claim 3 and are rejected under similar reasoning.
Claims 12 and 18 recite limitations which are substantially equivalent to those of Claim 5 and are rejected under similar reasoning. Furthermore, it is noted that Claim 18 is a method claim reciting a contingent limitation. As indicated above, if the condition for performing a contingent step is not satisfied, the performance recited by the step need not be carried out by the prior art in order for the claimed method to be performed.
Claims 13 and 19 recite limitations which are substantially equivalent to those of Claim 6 and are rejected under similar reasoning.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to Claims 1 and 8 above, and further in view of US Patent Application Publication Number 2021/0157700 to Dorsey et al. (“Dorsey”).
In reference to Claim 4, Park discloses the limitations as applied to Claim 1 above. However, Park does not explicitly disclose that the frequency optimizer further to increase the operating frequency of the memory based on one of a first latency requirement of the first processing core, and a second latency requirement of the second processing core. Dorsey discloses a frequency optimizer that increases the operating frequency of a memory based on one of a first latency requirement (See Paragraphs 39-41) of a first processing core (See Figure 2 Number 222 and Paragraph 19), and a second latency requirement (See Paragraphs 39-41) of a second processing core (See Figure 2 Number 221 and Paragraph 19); wherein the first processing core is a high-performance core (See Figure 2 Number 222 and Paragraph 19) and the second processing core is an energy-efficient core (See Figure 2 Number 221 and Paragraph 19).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Park using the memory frequency determination based on core latency requirements of Dorsey, resulting in the invention of Claim 4, in order to yield the predictable result of ensuring the that the cores meet their performance goals and perform complete their work in a predetermined period of time (See Paragraph 39 of Dorsey).
Claim 11 recites limitations which are substantially equivalent to those of Claim 4 and are rejected under similar reasoning.
Claim(s) 7, 14, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to Claims 1, 8, and 15 above, and further in view of US Patent Application Publication Number 2015/0378424 to Anyuru (“Anyuru”).
In reference to Claim 7, Park discloses the limitations as applied to Claim 1 above. However, Park does not explicitly disclose that the frequency optimizer to increase the operating frequency of the memory after a hysteresis threshold time has been met. Anyuru discloses a frequency optimizer to increase the operating frequency of a memory after a hysteresis threshold time has been met (See Paragraphs 4, 14, 25-26, 34-37, and 57).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to construct the device of Park using the hysteresis for memory frequency adjustment of Anyuru, resulting in the invention of Claim 7, in order to yield the predictable result of preventing overly rapid switching between memory frequency operating points (See Paragraph 35 of Anyuru).
Claims 14 and 20 recite limitations which are substantially equivalent to those of Claim 7 and are rejected under similar reasoning.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12 September 2022 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Conclusion
The art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THOMAS J CLEARY whose telephone number is (571)272-3624. The examiner can normally be reached Monday-Friday 8AM-5PM.
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/THOMAS J. CLEARY/Primary Examiner, Art Unit 2175