DETAILED ACTION
This action is responsive to U.S. Patent Application No. 17/943,840 filed on 13 September 2022.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election with traverse of the Species 2 embodiment in the reply filed on 29 December 2025 is acknowledged. The traversal is on the grounds that “there is no excessive burden to examine all species. For example, it is not clear what the distinction is between Species 2-4 as they are all described the same.” Applicant Arguments/Remarks Made in an Amendment (filed 29 December 2025) at 7.
Applicant’s arguments are unpersuasive because none of Applicant’s grounds for traversal substantially address any criteria for restriction between mutually exclusive species. See MPEP § 806.04(f). Even in light of Applicant’s arguments, the differences between embodiments noted in the Requirement for Restriction provide prima facie evidence that a serious search burden exists. See Requirement for Restriction (mailed 29 October 2025) at 2-4.
Accordingly, the requirement is still deemed proper and is therefore made FINAL.
Claims 8 and 16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the claimed feature of claim 14 “a second plurality of interconnect features to electrically couple the drain region to a second terminal, wherein one of the first or second terminals is an input/output (I/O) terminal of the integrated circuit structure” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 12 is objected to because of the following informalities:
Claim 7 contains a typo and should read: “and second one or more interconnect features”;
Claim 9 contains a typo and should read: “one or more interconnect features”
Claim 12 contains a typo and should read: “wherein the first diffusion region and the sub-fin form an anode . . . .”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
“The essential inquiry pertaining to this requirement is whether the claims set out and circumscribe a particular subject matter with a reasonable degree of clarity and particularity. ‘As the statutory language of “particular[ity]” and “distinct[ness]” indicates, claims are required to be cast in clear—as opposed to ambiguous, vague, indefinite—terms. It is the claims that notify the public of what is within the protections of the patent, and what is not.' ” MPEP 2173.02(II) (quoting In re Packard, 751 F.3d 1307, 1313, 110 USPQ2d 1785, 1788 (Fed. Cir. 2014)).
Regarding claim 4: claim 4 states, in relevant part, “the trench including dielectric material laterally between (i) the first diffusion region and (ii) the second and third diffusion regions.” This phrase renders the scope of the claim unclear because it is susceptible to more than one interpretation, including whether Applicant is claiming either (1) wherein the trench includes dielectric material disposed between the first diffusion region and second and third regions, or (2) wherein the trench includes dielectric material disposed laterally between the first diffusion region and laterally between the second and third diffusion regions. For the purposes of examination, the relevant phrase has been interpreted in accordance with interpretation (1).
Regarding claim 7: claim 7 states, in relevant part, “first one or more interconnect features to electrically couple the second diffusion region to an input/output (I/O) pin of the integrated circuit structure; and second one or more interconnect feature to electrically couple the first and third diffusion regions to a ground terminal.” This phrase renders the scope of the claim unclear because it is susceptible to more than one interpretation, including whether Applicant is claiming either (1) a first set of one or more interconnect features and a second set of one or more interconnect features, or (2) a set of one or more interconnect features having a first interconnect feature and a second interconnect feature. For the purposes of examination, the relevant phrase has been interpreted in accordance with interpretation (1).
Regarding claim 19: claim 19 states, in relevant part, “a plurality of interconnect features to electrically couple the source region to the layer, wherein the plurality of interconnect features electrically couples the source region and the layer to either a ground terminal or a power terminal, and/or a plurality of interconnect features to electrically couple the drain region to an input/output (I/O) terminal.” The phrase “and/or” renders the scope of the claim unclear because it is susceptible to more than one interpretation, including whether Applicant is claiming either (1) certain interconnect features non-mutually exclusively, or (2) certain interconnect features mutually exclusively (i.e., interconnect features that couple the source region and the layer to either a ground or power terminal, but not interconnect features that electrically couple the drain region to an input/output (I/O) terminal).
For the purposes of examination, the relevant phrase has been interpreted in accordance with interpretation (1).
Applicant may cancel the claims, amend the claims, or present a sufficient showing that the claims comply with the statutory requirements.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 5, 9-12, and 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Patent Publication No. 2019/0081032 (filed Nov. 8, 2018) (hereinafter “Okubo”).
Regarding independent claim 1, Okubo discloses: An integrated circuit structure (FIGS. 33-38, depicting a semiconductor device, [0099]), comprising:
a sub-fin (FIG. 34, p-type well 72, [0197]) having a first type of dopant (FIG. 34, [0198]: “In more detail, a p-type impurity is ion-implanted into a surface of the silicon substrate 71 to form the p-type well 72 in a surface layer of the silicon substrate 71.”);
a first diffusion region (FIG. 34, e.g., rightmost p-type region 84a, [0216]) comprising the first type of dopant (FIG. 34, [0218]: “Next, a p-type impurity is ion-implanted to a portion of the layered structure exposed from the opening 83 a using the resist mask 83. The ion implantation is performed under a condition to achieve a concentration higher than a p-type impurity concentration in the p-type well 72 and the layered structure. Thus, the p-type region 84a is formed in the layered structure . . . .”) and in contact with the sub-fin (FIG. 34, depicting wherein the p-type region 84a is in contact with the p-type well 72);
a second diffusion region (FIG. 34, e.g., rightmost n-type region 82a, [0213]) and a third diffusion region (FIG. 34, e.g., leftmost n-type region 82a, [0213]), each of the second and third diffusion regions comprising a second type of dopant (FIG. 34, [0215]: “Next, an n-type impurity is ion-implanted to a portion of the layered structure exposed from the opening 81 a using the resist mask 81. The ion implantation is performed under a condition to achieve a concentration higher than an n-type impurity concentration in the n-type well 74 and the layered structure. Thus, the n-type region 82 a is formed in the layered structure in the diode formation region”) and in contact with the sub-fin (FIG. 34, depicting wherein the n-type regions 82a are in contact with the p-type well 72),
wherein the first type of dopant is one of a p-type or an n-type dopant (FIG. 34, disclosing wherein the first type is, e.g., a p-type dopant, [0218]), and
wherein the second type of dopant is the other of the p-type or the n-type dopant (FIG. 34, disclosing wherein the first type is, e.g., an n-type dopant, [0215]),
wherein the second diffusion region is laterally between the first and third diffusion regions (FIG. 34, depicting wherein the rightmost n-type region 82a is laterally between the leftmost n-type region 82a and the rightmost p-type region 84a);
a first body of semiconductor material (FIG. 34, e.g., topmost leftmost Si layer 76, [0223]) extending from the second diffusion region to the third diffusion region (FIG. 34, depicting wherein the leftmost Si layer 76 extends in a direction from the rightmost n-type region 82a to the leftmost n-type region 82a); and
a second body of semiconductor material (FIG. 34, e.g., topmost rightmost Si layer 76, [0223]) extending from the first diffusion region towards the second diffusion region (FIG. 34, depicting wherein the rightmost Si layer 76 extends in a direction from the rightmost p-type region 84a to the rightmost n-type region 82a).
Regarding claim 5, Okubo further discloses wherein the third diffusion region (FIG. 34, e.g., leftmost n-type region 82a) is a source region (FIG. 34, depicting wherein the leftmost n-type region 82a may be a source region), and the second diffusion region (FIG. 34, e.g., rightmost n-type region 82a) is a drain region (FIG. 34, depicting wherein the rightmost n-type region 82a may be a drain region).
Regarding claim 9, Okubo further discloses wherein one or more interconnect feature (FIG. 35, e.g., wirings 93/94, [0233]) to electrically couple the first diffusion region to the third diffusion region (FIG. 35, depicting wherein the wirings 93/94 electrically couple the rightmost p-type region 84a and the leftmost n-type region 82a), wherein the first diffusion region is a tap that contacts the sub-fin (FIG. 34, depicting wherein the rightmost p-type region 84a contacts the p-type well 72), and the third diffusion region is a source region (FIG. 34, depicting wherein the leftmost n-type region 82a may be a source region).
Regarding claim 10, Okubo further discloses wherein each of the first and second bodies is a nanoribbon, a nanowire, or a nanosheet (FIGS. 33/34, depicting wherein the topmost leftmost Si layer 76 and topmost rightmost Si layer 76 are nanoribbons).
Regarding claim 11, Okubo further discloses a vertical stack of bodies comprising semiconductor material (FIGS. 33/34, depicting a vertical stack of Si layers 76) extending from the second diffusion region to the third diffusion region (FIGS. 33/34, depicting wherein the vertical stack of Si layers 76 extends in a direction from the rightmost n-type region 82a to the leftmost n-type region 82a), the vertical stack of bodies including the first body (FIGS. 33/34, depicting wherein the vertical stack of Si layers 76 includes the topmost leftmost Si layer 76); and a gate structure (FIGS. 33/34, gate electrode 89, [0227]) wrapping around individual bodies of the vertical stack of bodies (FIGS. 33/34, depicting wherein the gate electrode 89 wraps around the individual Si layers 76 of the stack of Si layers 76).
Regarding claim 12, Okubo further discloses a diode (FIG. 34, e.g., diode DB) that is based on a PN junction between the sub-fin and the second diffusion region (FIG. 34, depicting wherein the diode DB is based on a PN junction between the p-type well 72 and the rightmost n-type region 82a), wherein the first diffusion region and the second form an anode of the diode (FIG. 34, depicting wherein the rightmost p-type region 84a and the p-type well 72 form an anode of the diode DB), and the second diffusion region forms a cathode of the diode (FIG. 34, depicting wherein the rightmost n-type region 82a forms a cathode of the diode DB).
Regarding independent claim 18, Okubo discloses: An integrated circuit structure (FIGS. 33-38, depicting a semiconductor device, [0099]), comprising:
a sub-fin (FIG. 34, p-type well 72, [0197]) having a first type of dopant (FIG. 34, [0198]: “In more detail, a p-type impurity is ion-implanted into a surface of the silicon substrate 71 to form the p-type well 72 in a surface layer of the silicon substrate 71.”);
a source region (FIG. 34, depicting wherein the leftmost n-type region 82a may be a source region) and a drain region (FIG. 34, depicting wherein the rightmost n-type region 82a may be a drain region) comprising a second type of dopant (FIG. 34, [0215]: “Next, an n-type impurity is ion-implanted to a portion of the layered structure exposed from the opening 81 a using the resist mask 81. The ion implantation is performed under a condition to achieve a concentration higher than an n-type impurity concentration in the n-type well 74 and the layered structure. Thus, the n-type region 82 a is formed in the layered structure in the diode formation region”),
the source and drain regions in contact with and extending vertically upward from the sub-fin (FIG. 34, depicting wherein the leftmost and rightmost n-type regions 82a contact and extend vertically upward from the p-type well 72),
wherein the first type of dopant is one of a p-type or an n-type dopant (FIG. 34, disclosing wherein the first type is, e.g., a p-type dopant, [0218]), and
wherein the second type of dopant is the other of the p-type or the n-type dopant (FIG. 34, disclosing wherein the first type is, e.g., an n-type dopant, [0215]);
a layer comprising semiconductor material and including the first type of dopant (FIG. 34, e.g., rightmost p-type region 84a, [0216]),
the layer in contact with, extending vertically upward from, the sub-fin (FIG. 34, depicting wherein the rightmost p-type region 84a contacts and extends vertically upward from the p-type well 72); and
a dielectric material structure (FIGS. 33/34, e.g., gate insulating film 88, which may be a high dielectric film, [0226]) laterally between and separating the layer from the source and drain regions (FIG. 34, depicting wherein the gate insulating film 88 is laterally between and separates the leftmost and rightmost n-type regions 82a from the rightmost p-type region 84a).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6, 7, 13-15, and 19 are rejected under 35 U.S.C. § 103 as being unpatentable over Okubo.
Regarding claim 6, the FIG. 33-38 embodiment of Okubo does not specifically disclose wherein the first diffusion region is a tap that connects the sub-fin to a ground terminal or a power terminal.
In the same field of endeavor, in the FIG. 13 embodiment of Okubo, Okubo discloses a circuit configuration (FIG. 13, depicting a circuit configuration wherein diode DA (An) and diode DB (Bn) are electrically connected to the I/O terminal and the VSS terminal, including current paths P1 and P2, [0150]) comprising an integrated circuit. Regarding the circuit configuration, in [0150], Okubo states: “This configuration increases the current path as compared with the case where the ESD protection diode is composed of only the gate-type diode or only the STI-type diode as in the prior art, and realizes lowered resistance of the ESD protection diode.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed integrated circuit of Okubo FIGS. 33-38 by adding the circuit configuration of Okubo FIG. 13 in order to provide ESD protection and realize lowered resistance of the ESD protection diode. See Okubo [0150].
Moreover, addition of the circuit configuration of Okubo FIG. 13 would result in a configuration wherein the first diffusion region (FIG. 34, e.g., rightmost p-type region 84a) is a tap that connects the sub-fin to a ground terminal or a power terminal (FIGS. 13/34, depicting wherein the rightmost p-type region 84a would be a tap that connects the p-type well 72 to an I/O terminal or a VSS terminal).
Regarding claim 7, the FIG. 33-38 embodiment of Okubo does not specifically disclose a first one or more interconnect features to electrically couple the second diffusion region to an input/output (I/O) pin of the integrated circuit structure; and second one or more interconnect feature to electrically couple the first and third diffusion regions to a ground terminal.
In the same field of endeavor, in the FIG. 13 embodiment of Okubo, Okubo discloses a circuit configuration (FIG. 13, depicting a circuit configuration wherein diode DA (An) and diode DB (Bn) are electrically connected to the I/O terminal and the VSS terminal, including current paths P1 and P2, [0150]) comprising an integrated circuit. Regarding the circuit configuration, in [0150], Okubo states: “This configuration increases the current path as compared with the case where the ESD protection diode is composed of only the gate-type diode or only the STI-type diode as in the prior art, and realizes lowered resistance of the ESD protection diode.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed integrated circuit of Okubo FIGS. 33-38 by adding the circuit configuration of Okubo FIG. 13 in order to provide ESD protection and realize lowered resistance of the ESD protection diode. See Okubo [0150].
Moreover, addition of the circuit configuration of Okubo FIG. 13 would result in a configuration wherein a first one or more interconnect features (FIGS. 13/34, depicting lines connecting the diodes DA and DB (An and Bn, respectively) to various features) electrically couple the second diffusion region to an input/output (I/O) pin of the integrated circuit structure (FIGS. 13/34, depicting wherein the lines would electrically connect the diodes DA and DB, including rightmost n-type region 82a, to the I/O terminal); and second one or more interconnect feature (FIGS. 13/34, depicting lines connecting the diodes DA and DB (An and Bn, respectively) to various features) electrically couple the first and third diffusion regions to a ground terminal (FIGS. 13/34, depicting wherein the lines would electrically connect the diodes DA and DB, including rightmost p-type region 84a and the leftmost n-type region 82a, to the VSS terminal).
Regarding claim 13, the FIG. 33-38 embodiment of Okubo does not specifically disclose wherein the diode is configured to conduct current between the second diffusion region and a ground terminal, during an Electrostatic Discharge (ESD) event occurring in an input/output pin coupled to the second diffusion region.
In the same field of endeavor, in the FIG. 13 embodiment of Okubo, Okubo discloses a circuit configuration (FIG. 13, depicting a circuit configuration wherein diode DA (An) and diode DB (Bn) are electrically connected to the I/O terminal and the VSS terminal, including current paths P1 and P2, [0150]) comprising an integrated circuit. Regarding the circuit configuration, in [0150], Okubo states: “This configuration increases the current path as compared with the case where the ESD protection diode is composed of only the gate-type diode or only the STI-type diode as in the prior art, and realizes lowered resistance of the ESD protection diode.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed integrated circuit of Okubo FIGS. 33-38 by adding the circuit configuration of Okubo FIG. 13 in order to provide ESD protection and realize lowered resistance of the ESD protection diode. See Okubo [0150].
Moreover, addition of the circuit configuration of Okubo FIG. 13 would result in a configuration wherein the diode is configured to conduct current between the second diffusion region and a ground terminal, during an Electrostatic Discharge (ESD) event occurring in an input/output pin coupled to the second diffusion region (FIGS. 13/34, [0150]: “A circuit configuration of the semiconductor device according to this embodiment is illustrated in FIG. 13. In FIG. 13, a diode An (n=1, 2, . . . ) is indicated representing the plurality of first diodes DA arrayed in the lateral direction. A diode Bn (n=1, 2, . . . ) is indicated representing the plurality of second diodes DB arrayed in the longitudinal direction. In this embodiment, the diodes An, Bn are connected in parallel. Therefore, when a surge current flows from an I/O terminal, the surge current is prevented from passing through a CMOS transistor (a p-type MOS transistor and an n-type MOS transistor) and passes through two kinds of current paths P1, P2. The current path P1 is a path passing through the diode An, a power rail clamp, and a VSS terminal. The current path P2 is a path passing through the diode Bn, the power rail clamp, and the VSS terminal. This configuration increases the current path as compared with the case where the ESD protection diode is composed of only the gate-type diode or only the STI-type diode as in the prior art, and realizes lowered resistance of the ESD protection diode.”).
Regarding independent claim 14, Okubo discloses: An integrated circuit structure (FIGS. 33-38, depicting a semiconductor device, [0099]), comprising:
a sub-fin (FIG. 34, p-type well 72, [0197]) having a first type of dopant (FIG. 34, [0198]: “In more detail, a p-type impurity is ion-implanted into a surface of the silicon substrate 71 to form the p-type well 72 in a surface layer of the silicon substrate 71.”);
a diffusion region (FIG. 34, e.g., rightmost p-type region 84a, [0216]) having the first type of dopant (FIG. 34, [0218]: “Next, a p-type impurity is ion-implanted to a portion of the layered structure exposed from the opening 83 a using the resist mask 83. The ion implantation is performed under a condition to achieve a concentration higher than a p-type impurity concentration in the p-type well 72 and the layered structure. Thus, the p-type region 84a is formed in the layered structure . . . .”) and in contact with the sub-fin (FIG. 34, depicting wherein the p-type region 84a is in contact with the p-type well 72);
a source region (FIG. 34, depicting wherein the leftmost n-type region 82a may be a source region) and a drain region (FIG. 34, depicting wherein the rightmost n-type region 82a may be a drain region) comprising a second type of dopant (FIG. 34, [0215]: “Next, an n-type impurity is ion-implanted to a portion of the layered structure exposed from the opening 81 a using the resist mask 81. The ion implantation is performed under a condition to achieve a concentration higher than an n-type impurity concentration in the n-type well 74 and the layered structure. Thus, the n-type region 82 a is formed in the layered structure in the diode formation region”) and in contact with the sub-fin (FIG. 34, depicting wherein the n-type regions 82a are in contact with the p-type well 72).
The FIG. 33-38 embodiment of Okubo does not specifically disclose a first plurality of interconnect features to electrically couple the diffusion region and the source region to a first terminal, and a second plurality of interconnect features to electrically couple the drain region to a second terminal, wherein one of the first or second terminals is an input/output (I/O) terminal of the integrated circuit structure.
In the same field of endeavor, in the FIG. 13 embodiment of Okubo, Okubo discloses a circuit configuration (FIG. 13, depicting a circuit configuration wherein diode DA (An) and diode DB (Bn) are electrically connected to the I/O terminal and the VSS terminal, including current paths P1 and P2, [0150]) comprising an integrated circuit. Regarding the circuit configuration, in [0150], Okubo states: “This configuration increases the current path as compared with the case where the ESD protection diode is composed of only the gate-type diode or only the STI-type diode as in the prior art, and realizes lowered resistance of the ESD protection diode.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed integrated circuit of Okubo FIGS. 33-38 by adding the circuit configuration of Okubo FIG. 13 in order to provide ESD protection and realize lowered resistance of the ESD protection diode. See Okubo [0150].
Moreover, addition of the circuit configuration of Okubo FIG. 13 would result in a configuration wherein a first plurality of interconnect features electrically couple the diffusion region and the source region to a first terminal (FIGS. 13/34/35, e.g., wirings 93/94 and lines connecting the diodes DA and DB (An and Bn, respectively) to various features), and a second plurality of interconnect features to electrically couple the drain region to a second terminal (FIGS. 13/34/35, e.g., wirings 93/94 and lines connecting the diodes DA and DB (An and Bn, respectively) to various features), wherein one of the first or second terminals is an input/output (I/O) terminal of the integrated circuit structure (FIGS. 13/34/35, depicting wherein the lines would electrically connect the diodes DA and DB, including rightmost n-type region 82a, to the I/O terminal).
Regarding claim 15, Okubo FIGS. 33-38 as modified by Okubo FIG. 13 further discloses wherein: the first type of dopant is a p-type (FIG. 34, disclosing wherein the first type is, e.g., a p-type dopant, [0218]), and the second type of dopant is an n-type dopant (FIG. 34, disclosing wherein the first type is, e.g., an n-type dopant, [0215]); the first terminal is the I/O terminal of the integrated circuit structure (FIG. 13, depicting a circuit configuration wherein diode DA (An) and diode DB (Bn) are electrically connected to the I/O terminal and the VSS terminal, including current paths P1 and P2, [0150]); and the second terminal is a ground terminal (FIG. 13, depicting a circuit configuration wherein diode DA (An) and diode DB (Bn) are electrically connected to the I/O terminal and the VSS terminal, including current paths P1 and P2, [0150]).
Regarding claim 19, the FIG. 33-38 embodiment of Okubo does not specifically disclose a plurality of interconnect features to electrically couple the source region to the layer, wherein the plurality of interconnect features electrically couples the source region and the layer to either a ground terminal or a power terminal, and/or a plurality of interconnect features to electrically couple the drain region to an input/output (I/O) terminal.
In the same field of endeavor, in the FIG. 13 embodiment of Okubo, Okubo discloses a circuit configuration (FIG. 13, depicting a circuit configuration wherein diode DA (An) and diode DB (Bn) are electrically connected to the I/O terminal and the VSS terminal, including current paths P1 and P2, [0150]) comprising an integrated circuit. Regarding the circuit configuration, in [0150], Okubo states: “This configuration increases the current path as compared with the case where the ESD protection diode is composed of only the gate-type diode or only the STI-type diode as in the prior art, and realizes lowered resistance of the ESD protection diode.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed integrated circuit of Okubo FIGS. 33-38 by adding the circuit configuration of Okubo FIG. 13 in order to provide ESD protection and realize lowered resistance of the ESD protection diode. See Okubo [0150].
Moreover, addition of the circuit configuration of Okubo FIG. 13 would result in a configuration wherein a plurality of interconnect features electrically couple the source region to the layer (FIGS. 13/34/35, e.g., wirings 93/94 and lines connecting the diodes DA and DB (An and Bn, respectively) to various features), wherein the plurality of interconnect features electrically couples the source region and the layer to either a ground terminal or a power terminal (FIGS. 13/34/35, depicting wherein the lines would electrically connect the diodes DA and DB, including rightmost n-type region 82a and rightmost p-type region 84a, to the I/O terminal and the VSS terminal), and/or a plurality of interconnect features to electrically couple the drain region to an input/output (I/O) terminal (FIGS. 13/34/35, depicting wherein the lines would electrically connect the diodes DA and DB, including leftmost n-type region 82a, to the I/O terminal).
Allowable Subject Matter
Claims 2-3, 17, and 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 4 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The closest prior art known to the Examiner is listed on the PTO 892 forms of record.
With respect to claim 2, the cited prior art does not anticipate or make obvious “a third body of semiconductor material extending from the first diffusion region and away from the second diffusion region, wherein a first end of the second body is in contact with the first diffusion region and an opposing second end of the second body is not in contact with any diffusion region, and wherein a first end of the third body is in contact with the first diffusion region and an opposing second end of the third body is not in contact with any diffusion region.”
With respect to claim 3, the cited prior art does not anticipate or make obvious “a third body of semiconductor material extending from the second diffusion region and towards the first diffusion region, wherein a first end of the third body is in contact with the second diffusion region and an opposing second end of the third body is not in contact with any diffusion region; and a dielectric material structure laterally between, and in contact with, the first body and the third body.”
With respect to claim 4, Okubo discloses a trench including dielectric material that at least in part extends within the sub-fin, the trench including dielectric material laterally between (i) the first diffusion region and (ii) the second and third diffusion regions (FIG. 34, depicting interlayer insulating film 85 and element isolation structures 77, wherein the element isolation structures 77 are laterally between the rightmost p-type region 84a and at least the leftmost n-type region 82a). The cited prior art does not anticipate or make obvious does wherein “each of the first, second, and third diffusion regions at least in part extends within the sub-fin.”
With respect to claim 17, Okubo discloses a first plurality of bodies extending from the source region to the drain region (FIG. 34, e.g., leftmost Si layers 76); a second plurality of bodies extending from the diffusion region towards the drain region (FIG. 34, e.g., rightmost Si layers 76). The cited prior art does not anticipate or make obvious “a third plurality of bodies extending from the diffusion region away from the drain region, wherein each of the first, second and third plurality of bodies is above the sub-fin and comprises semiconductor material.”
With respect to claim 20, Okubo discloses a plurality of bodies comprising semiconductor material extending laterally from the layer (FIG. 34, e.g., rightmost Si layers 76), wherein each of the plurality of bodies is a nanoribbon, a nanowire, or a nanosheet (FIGS. 33/34, depicting wherein the rightmost Si layers 76 are nanoribbons). The cited prior art does not anticipate or make obvious “wherein each of the plurality of bodies is not in contact with any source or drain region.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. U.S. Patent Publication Nos.: 2022/0367659; 2023/0369313; 2022/0045052; 2023/0110825.
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/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813