Detailed Action
1. This office action is in response to communication filed December 8, 2025. Claims 1-5, 8-12, and 15-24 are currently pending and claims 1, 9, and 16 are the independent claims.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
3. This Non-Final Rejection following RCE is in response to the applicant’s remarks and arguments filed on December 8, 2025.
Claims 1, 9, and 16 are amended. Claims 6-7 and 13-14 have been cancelled. Claims 21-24 are new. Claims 1-5, 8-12, and 15-24 remain pending in the application. Claims 2-5, 8, 10-12, 15, and 17-20 filed most recently on August 27, 2025 are being considered on the merits along with amended claims 1, 9, and 16 and new claims 21-24.
Response to Arguments
4. Applicant's arguments filed December 8, 2025 have been fully considered but they are not persuasive.
On Remarks page 8, the Attorney discusses the “Patentability of the Claims under 35 U.S.C. 103”. The Attorney suggests none of the cited references disclose or make obvious the amended claims.
The Examiner respectfully disagrees with the Attorney that “none of the cited references disclose or make obvious at least these claim features” while writing about the amendments to the independent claims. The amendments to the independent claims came from the original claims 6-7 that were cancelled. The prior art that rejected claims 6-7 is still valid for rejecting the amendments to the independent claims. The amendments overcame the 112 rejection, but do not overcome the 103 rejections. Specific interpretations and explanations of how the prior art maps to the claimed language of the invention appears in Section 8 below.
New claims 21-24 appearing in RCE have been rejected in Section 8 below. With that being said, the Examiner maintains the rejections to the independent claims and the dependent claims relying on them such that claims 1-5, 8-12, and 15-24 are rejected under 35 U.S.C. 103.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claims 1-2, 5, 9, 16-17, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sankaran et al. (U.S. Pub. No. 2016/0117190) – hereinafter “Sankaran”, in view of Zhao et al. (U.S. Pub. No. 2011/0145461) – hereinafter “Zhao” and Koryakin et al. (U.S. Patent No. 10,180,855) – hereinafter “Koryakin”.
Regarding independent claim 1, Sankaran discloses a non-transitory computer-readable medium comprising program code that is executable by a processor to:
detect a first interrupt associated with a first device, wherein the first interrupt is intended for a virtual machine; ([0003] “Virtualization is typically implemented by using software (e.g., a virtual machine monitor (“VMM”)) to present to each OS a virtual machine (“VM”) having virtual resources, including one or more virtual processors, that the OS may completely and directly control, while the VMM maintains a system environment for implementing virtualization policies such as sharing and/or allocating the physical resources among the VMs (the “virtualization environment”).” and [0096] “Some embodiments pertain to Example 1 that includes a method comprising receiving an interrupt targeting a virtual processor…”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the interrupt targeting a virtual processor of a virtual machine is received.
based on detecting the first interrupt:
determine whether the virtual machine is in an idle state; ([0049] “In one embodiment, an interrupt may be received while a virtual machine is Running, Pre-empted and Idle/Blocked states… Further, VMM control is obtained for external interrupts to an Idle/Blocked virtual processor to enable the VMM to schedule the virtual processor.” and [0078] “For hard-real time usages, the VMM often dedicates the virtual processors of such VMs to a specific set of logical CPUs, thus ensuring that the virtual processors is running most all the time on those logical CPUs (enabling direct delivery of interrupts to running virtual processors), and getting VMM control immediately on interrupts to blocked virtual processors, so that VMM may quickly transition such virtual processors from the Idle/Blocked state to Pre-empted state to Running state.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the interrupt is received while the VM is in an idle state and the VMM will help to handle the interrupt, such as transitioning the state of the processor.
…interrupts are to be delayed at least until the virtual machine is awakened by an event other than the first interrupt; and ([0098] “Example 3 includes the subject matter of Example 2, further comprising storing the interrupt in a buffer upon determining that the virtual processor is operating in a pre-empted state and delivering the interrupt to the virtual processor upon the virtual processor transitioning from the pre-empted state to the running state.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the virtual machine is determined to be in the awake/running state based on transitioning from the pre-empted state to the running state, thus the interrupt is delivered/transmitted to the virtual processor of the virtual machine only after the virtual processor transitions to the awakened state.
… delay the first interrupt by storing the first interrupt in an interrupt register and preventing the first interrupt from being transmitted to the virtual machine at least until the virtual machine is awakened by an event other than the first interrupt, such that the first interrupt is not used as a basis for awakening the virtual machine from the idle state; ([0098] “Example 3 includes the subject matter of Example 2, further comprising storing the interrupt in a buffer upon determining that the virtual processor is operating in a pre-empted state and delivering the interrupt to the virtual processor upon the virtual processor transitioning from the pre-empted state to the running state.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the interrupt is delayed by storing the interrupt in a buffer and is not transferred to the VM until it is in the running state without any intervention from the delayed interrupt.
subsequent to storing the first interrupt in the interrupt register to delay delivery of the first interrupt to the virtual machine:
determine that the virtual machine is in an awake state; and ([0098] “Example 3 includes the subject matter of Example 2, further comprising storing the interrupt in a buffer upon determining that the virtual processor is operating in a pre-empted state and delivering the interrupt to the virtual processor upon the virtual processor transitioning from the pre-empted state to the running state.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the virtual machine is determined to be in the awake/running state based on transitioning from the pre-empted state to the running state.
in response to determining that the virtual machine is in the awake state, release the delay by transmitting the first interrupt from the interrupt register to the virtual machine, thereby ending the delay of the first interrupt; ([0098] “Example 3 includes the subject matter of Example 2, further comprising storing the interrupt in a buffer upon determining that the virtual processor is operating in a pre-empted state and delivering the interrupt to the virtual processor upon the virtual processor transitioning from the pre-empted state to the running state.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the virtual machine is determined to be in the awake/running state based on transitioning from the pre-empted state to the running state, thus the interrupt is delivered/transmitted to the virtual processor of the virtual machine.
detect a second interrupt associated with a second device that is different from the first device, wherein the second interrupt is also intended for the virtual machine; ([0020-0021] “In still a further embodiment, all external interrupts to a virtual processor are co-migrated whenever a virtual processor is migrated from one logical central processing unit (CPU) to another logical CPU. The above-described embodiments operate for both lowest-priority interrupts, as well as level-triggered external interrupts. Moreover, a mechanism is provided for handling real-time interrupts (e.g., from media devices and/or communication/modem devices) that are qualified as urgent.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, there are multiple interrupts associated with multiple different device types.
… transmit the interrupt to the virtual machine without delaying the interrupt and without storing the interrupt in the interrupt register. (Abstract “The method includes receiving an interrupt targeting a virtual processor, determining a status of the virtual processor and directly delivering the interrupt to the virtual processor upon determining that the virtual processor is operating in a running state.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the virtual machine is determined to be in the awake/running state, thus the interrupt is delivered/transmitted to the virtual processor of the virtual machine without delay.
Sankaran does not explicitly disclose:
determine that a first device type associated with the first device is on a list of device types for which interrupts are to be delayed …
based on determining that the virtual machine is in the idle state, and that the first device type is on the list of device types for which interrupts are to be delayed … delay the first interrupt …
determine that a second device type associated with the second device is not on the list of device types for which interrupts are to be delayed; and
based on determining that the second device type is not on the list of device types for which interrupts are to be delayed, transmit the second interrupt …
However, Zhao discloses:
determine that a first device type associated with the first device is on a list of device types for which interrupts are to be delayed … ([0012] “Preferably, after controlling the interrupt controller to route the interrupt device to one or multiple cores in the scheduling core group to which the default processing core belongs, the method further comprises: judging whether the number of interrupts allocated by the interrupt device to each core to which the interrupt device is routed exceeds the interrupt threshold; or for each core to which the interrupt device is routed, judging whether a processing amount thereof exceeds an interrupt load thereof; and if the judgment result is yes, processing interrupts of the interrupt device in a polling manner.” and Table 1, type of interrupt source serial port and PCI device both have interrupt modes of interrupt/polling and thus will be delayed in a polling manner until resources to handle the interrupt are available) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the type of the interrupt device is supposed to be routed to the default processing core, but the interrupt threshold is reached so it will process interrupts in a polling manner as suggested in Table 1, thus delaying the interrupts.
based on determining that … the first device type is on the list of device types for which interrupts are to be delayed … [process the interrupt in a polling manner]; (Fig. 4, Steps S402-S406 and [0014] “Preferably, pre-configuring a default processing core and a scheduling core group corresponding to an interrupt device specifically comprises: setting the corresponding relation among type of the interrupt device, the scheduling core group, and the default processing core in a static interrupt strategy table, and storing the static interrupt strategy table in a nonvolatile memory, wherein the static interrupt strategy table is further set with the interrupt threshold and an interrupt mode, the interrupt mode including interrupt and polling.” and [0046-0048] “Step S402, pre-configuring a default processing core and a scheduling core group corresponding to an interrupt device, wherein the default processing core is one core in the scheduling core group; Step S404, configuring the interrupt controller to route the interrupt device to the corresponding default processing core; Step S406, controlling the interrupt controller to route the interrupt device to one or multiple cores in the scheduling core group to which the default processing core belongs”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the interrupt device is determined to be equivalent to the pre-configured entry for the interrupt device in the static interrupt strategy table and is thus handled in a polling manner as is set for the interrupt mode.
determine that a second device type associated with the second device is not on the list of device types for which interrupts are to be delayed; and ([0014] “Preferably, pre-configuring a default processing core and a scheduling core group corresponding to an interrupt device specifically comprises: setting the corresponding relation among type of the interrupt device, the scheduling core group, and the default processing core in a static interrupt strategy table, and storing the static interrupt strategy table in a nonvolatile memory, wherein the static interrupt strategy table is further set with the interrupt threshold and an interrupt mode, the interrupt mode including interrupt and polling.” and Table 1, type of interrupt source network port has an interrupt mode of interrupt and thus will not be delayed as it does not have the polling interrupt mode) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the type of the exterior device that causes an interrupt is in the table which routes the interrupt to a specific destination core depending on the device and is not delayed.
based on determining that the second device type is not on the list of device types for which interrupts are to be delayed, transmit the second interrupt to the [processor]; ([0009] “The method comprises: pre-configuring a default processing core and a scheduling core group corresponding to an interrupt device, wherein the default processing core is one core in the scheduling core group; configuring the interrupt controller to route the interrupt device to the corresponding default processing core; and controlling the interrupt controller to route the interrupt device to one or multiple cores in the scheduling core group to which the default processing core belongs, when the number of interrupts of the interrupt device exceeds an interrupt threshold or a processing amount of the default processing core exceeds an interrupt load.” and Table 1, type of interrupt source network port has an interrupt mode of interrupt and thus will not be delayed as it does not have the polling interrupt mode) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the type of the exterior device that causes an interrupt is in the table which routes the interrupt to a specific destination core depending on the device and is not delayed.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add determine that a first device type associated with the first device is on a list of device types for which interrupts are to be delayed, based on determining that … the first device type is on the list of device types for which interrupts are to be delayed, determine that a second device type associated with the second device is not on the list of device types for which interrupts are to be delayed, and based on determining that the second device type is not on the list of device types for which interrupts are to be delayed, transmit the second interrupt to the [processor] as seen in Zhao’s invention into Sankaran’s invention because these modifications allow “obvious to try” solutions with a reasonable expectation of success such that differentiation of handling interrupts is based on the type of device they are received from so that a user can decide which device interrupts will wake up an idle VM.
In addition, Koryakin discloses:
based on determining that the virtual machine is in the idle state … delay the first interrupt … (Col. 3, Lines 34-36 “In another aspect, the exemplary method includes delaying the timer device interrupts when the virtual processor is in the idle state. ” and Col. 5, Lines 63-67 “According to an exemplary aspect, the disclosed system and method is provided to delay or even ignore certain types of asynchronous events that would otherwise wake up the processor from the idle state when there are no “ready to execute” processes/threads.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the interrupt is delayed when the virtual processor is in the idle state.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add based on determining that the virtual machine is in the idle state, delay the interrupt as seen in Koryakin’s invention into Sankaran’s invention because these modifications allow applying a known technique to a known device ready for improvement to yield predictable results such that interrupts do not wake an idle VM if it is unnecessary, thus saving resources/power until the VM actually needs to be awoken.
Regarding claim 2, Sankaran discloses the non-transitory computer-readable medium of claim 1, wherein the interrupt register is located in a memory area for a hypervisor configured to manage the virtual machine. ([0041-0043] “The posted-interrupt descriptor, or any other data structure to which the IRTE for a posted interrupt request refers, may be stored in system memory 140, or in any other storage area in system 100… Software, such as a VMM, may allocate a posted-interrupt descriptor for each virtual processor that may be the target of external interrupt requests. FIG. 7 illustrates one embodiment of a posted-interrupt descriptor. Posted-interrupt descriptor 700 in FIG. 7 includes bit-fields 710, 720, 730, and 740. Bit-field 710 may include the lowest 32 bytes of the 64-byte posted-interrupt descriptor to form a 256-bit posted interrupt request register (“pIRR”). Each bit of the pIRR may correspond to one of 256 virtual interrupt vectors for the virtual processor corresponding to the posted-interrupt descriptor. Each bit of the pIRR may be set to post an interrupt request for the corresponding virtual interrupt vector.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the posted-interrupt descriptor can be stored in system memory and the posted interrupt request register (pIRR) where the VMM/hypervisor can access it to manage VMs.
Regarding claim 5, Sankaran discloses the non-transitory computer-readable medium of claim 2, wherein the interrupt register is a posted interrupt register of a virtual central processing unit associated with the virtual machine. ([0041-0043] “The posted-interrupt descriptor, or any other data structure to which the IRTE for a posted interrupt request refers, may be stored in system memory 140, or in any other storage area in system 100… Software, such as a VMM, may allocate a posted-interrupt descriptor for each virtual processor that may be the target of external interrupt requests. FIG. 7 illustrates one embodiment of a posted-interrupt descriptor. Posted-interrupt descriptor 700 in FIG. 7 includes bit-fields 710, 720, 730, and 740. Bit-field 710 may include the lowest 32 bytes of the 64-byte posted-interrupt descriptor to form a 256-bit posted interrupt request register (“pIRR”). Each bit of the pIRR may correspond to one of 256 virtual interrupt vectors for the virtual processor corresponding to the posted-interrupt descriptor. Each bit of the pIRR may be set to post an interrupt request for the corresponding virtual interrupt vector.” and [0045] “Bit-field 722 (“Dest-ID”) may include 32 bits to identify the destination of the interrupt request, which, for example, may be the local APIC for the physical processor on which the virtual processor that is the target of the interrupt request is running. The physical processor to which the target virtual processor has temporal affinity may change as virtual processors are migrated, so this field may be reprogrammed, by the VMM, with a new local APIC identifier in connection with a migration for load balancing or any other reason. The physical processor to which a target virtual processor has temporal affinity at any given time may be called the “notify-CPU” in this description, as it will be the physical processor to which a notify event will be sent when there are pending posted interrupts for that virtual processor.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the posted-interrupt descriptor can be stored in system memory and the posted interrupt request register (pIRR), and the VMM ensures the physical processor and virtual processor are linked so it is a register for the virtual processor’s interrupts.
Regarding claim 9, it is a method claim having the same limitations as cited in non-transitory computer-readable medium claim 1. Thus, claim 9 is also rejected under the same rationale as addressed in the rejection of claim 1 above.
Regarding claim 16, it is a system claim having the same limitations as cited in non-transitory computer-readable medium claim 1. Thus, claim 16 is also rejected under the same rationale as addressed in the rejection of claim 1 above.
Regarding claim 17, it is a system claim having the same limitations as cited in non-transitory computer-readable medium claim 2. Thus, claim 17 is also rejected under the same rationale as addressed in the rejection of claim 2 above.
Regarding claim 20, it is a system claim having the same limitations as cited in non-transitory computer-readable medium claim 5. Thus, claim 20 is also rejected under the same rationale as addressed in the rejection of claim 5 above.
6. Claims 3-4, 10-12, and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Sankaran et al. (U.S. Pub. No. 2016/0117190) – hereinafter “Sankaran”, Zhao et al. (U.S. Pub. No. 2011/0145461) – hereinafter “Zhao” and Koryakin et al. (U.S. Patent No. 10,180,855) – hereinafter “Koryakin”, further in view of Aggarwal et al. (U.S. Pub. No. 2019/0114196) – hereinafter “Aggarwal”.
Regarding claim 3, Sankaran discloses the non-transitory computer-readable medium of claim 1, but does not explicitly disclose:
wherein the first interrupt is associated with adding the first device to the virtual machine.
However, Aggarwal discloses:
wherein the first interrupt is associated with adding the first device to the virtual machine. ([0132] “Once the live migration is complete, if the new server running guest VM 802 has an S-IOV capable device, then the administrator can “hot-add” (e.g., connect) VDev 1 804 back into the guest VM. This action can be trapped by the VDCM 402 triggering an interrupt as a result of the ‘hot-add.’”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the hot-add of a device to the VM triggers an interrupt.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add wherein the first interrupt is associated with adding the first device to the virtual machine as seen in Aggarwal’s invention into Sankaran’s invention because these modifications allow applying a known technique to a known device ready for improvement to yield predictable results such that it is known when devices are added into a VM as it can be handled in a different way than for example software interrupts.
Regarding claim 4, Sankaran discloses the non-transitory computer-readable medium of claim 1, but does not explicitly disclose:
wherein the first interrupt is associated with removing the first device from the virtual machine.
However, Aggarwal discloses:
wherein the first interrupt is associated with removing the first device from the virtual machine. ([0125] “VDCM 402 is capable of taking traps on certain inputs from the guest VM. In order to support live migration, VDCM 402 traps into the interrupts that trigger the “hot-unplug” of VDev 1 804 in guest VM 1 802 when the live migration occurs.” and [0130] “When the VM is live migrated, any device interfaces that are tied to physical function 232 are “hot-unplugged” (e.g., disconnected). In the S-IOV architecture, the VDEV is hot-unplugged or ejected from the guest VM.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the hot-unplug of a device from the VM triggers an interrupt.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add wherein the first interrupt is associated with removing the first device from the virtual machine as seen in Aggarwal’s invention into Sankaran’s invention because these modifications allow applying a known technique to a known device ready for improvement to yield predictable results such that it is known when devices are added into a VM as it can be handled in a different way than for example software interrupts.
Regarding claim 10, it is a method claim having the same limitations as cited in non-transitory computer-readable medium claim 3. Thus, claim 10 is also rejected under the same rationale as addressed in the rejection of claim 3 above.
Regarding claim 11, it is a method claim having the same limitations as cited in non-transitory computer-readable medium claim 4. Thus, claim 11 is also rejected under the same rationale as addressed in the rejection of claim 4 above.
Regarding claim 12, it is a method claim having the same limitations as cited in non-transitory computer-readable medium claim 5. Thus, claim 12 is also rejected under the same rationale as addressed in the rejection of claim 5 above.
Regarding claim 18, it is a system claim having the same limitations as cited in non-transitory computer-readable medium claim 3. Thus, claim 18 is also rejected under the same rationale as addressed in the rejection of claim 3 above.
Regarding claim 19, it is a system claim having the same limitations as cited in non-transitory computer-readable medium claim 4. Thus, claim 19 is also rejected under the same rationale as addressed in the rejection of claim 4 above.
7. Claims 8 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Sankaran et al. (U.S. Pub. No. 2016/0117190) – hereinafter “Sankaran”, Zhao et al. (U.S. Pub. No. 2011/0145461) – hereinafter “Zhao”, and Koryakin et al. (U.S. Patent No. 10,180,855) – hereinafter “Koryakin”, further in view of Li (U.S. Pub. No. 2017/0083363).
Regarding claim 8, Sankaran discloses the non-transitory computer-readable medium of claim 1, further comprising program code that is executable by the processor but does not explicitly disclose:
in response to detecting the second interrupt, determine that the virtual machine is in the awake state.
However, Li discloses:
in response to detecting the second interrupt, determine that the virtual machine is in the awake state. ([0046] “Step 105: The virtual machine monitor writes the M pieces of second interrupt information and the identifier of the virtual machine corresponding to the M pieces of second interrupt information into the virtual CPU interrupt interface such that after determining that the virtual machine corresponding to the M pieces of second interrupt information is running, the virtual CPU interrupt interface sends the M pieces of second interrupt information to a processor corresponding to the virtual machine corresponding to the M pieces of second interrupt information.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the VM corresponding to the second interrupt is awake/running upon receiving the second interrupt.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add in response to detecting the second interrupt, determine that the virtual machine is in the awake state as seen in Li’s invention into Sankaran’s invention because these modifications allow the use of a known technique to improve similar devices in the same way such that multiple interrupt handling and automatic waking upon multiple interrupts is ensured so a multitude of interrupts do not stack while the VM is in the idle state.
Regarding claim 15, it is a method claim having the same limitations as cited in non-transitory computer-readable medium claim 8. Thus, claim 15 is also rejected under the same rationale as addressed in the rejection of claim 8 above.
8. Claims 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Sankaran et al. (U.S. Pub. No. 2016/0117190) – hereinafter “Sankaran”, Zhao et al. (U.S. Pub. No. 2011/0145461) – hereinafter “Zhao”, and Koryakin et al. (U.S. Patent No. 10,180,855) – hereinafter “Koryakin”, further in view of Zhang et al. (U.S. Pub. No. 2016/0274814) – hereinafter “Zhang”.
Regarding claim 21, Sankaran discloses the non-transitory computer-readable medium of claim 1, but does not explicitly disclose:
wherein the virtual machine transitions from the idle state to the awake state independently of the first interrupt.
However, Zhang discloses:
wherein the virtual machine transitions from the idle state to the awake state independently of the first interrupt. ([0023] “In embodiments, VMM 206 may be configured to request memory manager 208 to de-allocate unused and used memory of a virtual machine 212/214, in response to a determination that the virtual machine 212/214 is transitioning from an active state to a low activity state or an idle state.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the VM transitions from idle state to the active state based on the necessity of the VM by the user.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add wherein the virtual machine transitions from the idle state to the awake state independently of the first interrupt as seen in Zhang’s invention into Sankaran’s invention because these modifications allow applying a known technique to a known device ready for improvement to yield predictable results such that the VM can naturally transition state without always having to awake on interrupt if the interrupt is not of high priority.
Regarding claim 22, it is a method claim having the same limitations as cited in non-transitory computer-readable medium claim 21. Thus, claim 22 is also rejected under the same rationale as addressed in the rejection of claim 21 above.
Regarding claim 23, it is a system claim having the same limitations as cited in non-transitory computer-readable medium claim 21. Thus, claim 23 is also rejected under the same rationale as addressed in the rejection of claim 21 above.
Regarding claim 24, Sankaran discloses the method of claim 9, further comprising:
in response to detecting the transition of the virtual machine from the idle state to the awake state, releasing the delay of the first interrupt by transmitting the first interrupt from the interrupt register to the virtual machine. ([0098] “Example 3 includes the subject matter of Example 2, further comprising storing the interrupt in a buffer upon determining that the virtual processor is operating in a pre-empted state and delivering the interrupt to the virtual processor upon the virtual processor transitioning from the pre-empted state to the running state.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the virtual machine is determined to be in the awake/running state based on transitioning from the pre-empted state to the running state, thus the interrupt is delivered/transmitted to the virtual processor of the virtual machine.
Sankaran does not explicitly disclose:
detecting a transition of the virtual machine from the idle state to the awake state;
However, Zhang discloses:
detecting a transition of the virtual machine from the idle state to the awake state; ([0023] “In embodiments, VMM 206 may be configured to request memory manager 208 to de-allocate unused and used memory of a virtual machine 212/214, in response to a determination that the virtual machine 212/214 is transitioning from an active state to a low activity state or an idle state.”) The citation is interpreted to read on the claimed invention because under broadest reasonable interpretation, the VM transitions from idle state to the active state based on the necessity of the VM by the user.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to add detecting a transition of the virtual machine from the idle state to the awake state as seen in Zhang’s invention into Sankaran’s invention because these modifications allow applying a known technique to a known device ready for improvement to yield predictable results such that the VM can naturally transition state without always having to awake on interrupt if the interrupt is not of high priority.
Conclusion
9. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Such prior art includes Bhandari Aditya et al. (EP 3685262 B1) which discloses a hypervisor managing interrupts in a virtual environment based around sleep/idle and awake/active states and Mansell et al. (U.S. Pub. No. 2010/0023666 A1) which discloses virtual interface hardware that includes registers storing uncompleted interrupts and data on these interrupts associated with a virtual machine in use.
Examiner has cited particular columns/paragraphs/sections and line numbers in the references applied and not relied upon to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
When responding to the Office action, applicant is advised to clearly point out the patentable novelty the claims present in view of the state of the art disclosed by the reference(s) cited or the objections made. A showing of how the amendments avoid such references or objections must also be present. See 37 C.F.R. 1.111(c).
When responding to this Office action, applicant is advised to provide the line and page numbers in the application and/or reference(s) cited to assist in locating the appropriate paragraphs.
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/D.T./Examiner, Art Unit 2198
/PIERRE VITAL/Supervisory Patent Examiner, Art Unit 2198