DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The replacement drawings were received on 06/27/2025. These drawings are not acceptable to overcome the drawing objections made in the Non-Final Office Action mailed on 03/27/2025. Those objections are reiterated below along with additional drawing objections.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the feature(s) canceled from the claim(s):
Claim 3, line 3: “forming a patterned mask layer on the dielectric layer”
Claim 4, line 4: “forming a trench structure, a body region and a source region in the epitaxial layer”. The limitation implies a sequence, as the trench structure, body region, and source region must be formed in the epitaxial layer. The sequence must be shown in the drawings.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 14 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 14, lines 1-3 recite “…wherein at least part of the conducting path located in the doped region has a transverse dimension smaller than a minimum process dimension allowed by a manufacturing equipment for performing the etching”. The Examiner does not find explicit support for this limitation in the original disclosure. Paragraph [0004] of the specification states “a smaller size of the CONT hole requires a better manufacturing equipment…”, but there is not support for the quoted limitation in lines 1-3 of claim 4. Appropriate correction is required. No new matter should be added.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14, lines 1-3 recite “…wherein at least part of the conducting path located in the doped region has a transverse dimension smaller than a minimum process dimension allowed by a manufacturing equipment for performing the etching”. This limitation is unclear in light of the limitations of claim 1 on which it depends. For example, claim 1, lines 6-7 recite: “etching the semiconductor layer through the opening to form a conduction hole…”, followed by “filling the conduction hole with conductive material to form the conducting path”. Since the etching step in claim 1 creates the conduction hole in which the conducting path is formed, it is unclear how “as least part of the conducting path… has a transverse dimension smaller than a minimum process dimension allowed by a manufacturing equipment for performing the etching”. As best understood based on [0005] of the specification, the limitation will interpreted as “wherein at least part of the conducting path located in the doped region has a transverse dimension smaller than a transverse dimension of the opening”. Appropriate correction is required. No new matter should be added.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-2, 4-6, 8 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh in US 2014/0291753 A1 (hereinafter Hsieh).
Regarding claim 1, Hsieh teaches in FIGS. 3A-3D and related text, a method for manufacturing a conducting path (310, FIG. 3A, [0030]) in a doped region (306, FIG. 3A, [0030]), comprising:
forming a contact interlayer (311, FIG. 3B, [0030]) on a semiconductor layer (301, FIG. 2, [0012]), which includes the doped region (doped region 306 is inside semiconductor layer 301, [0012], inasmuch as is shown in FIG. 3a of Applicant’s disclosure);
forming an opening (opening with width CO’, FIG. 3B, [0031]) in the contact interlayer (311; FIG. 3B);
forming a side wall (312, FIG. 3D, [0030]) on a sidewall of the opening;
etching the semiconductor layer (306 of semiconductor layer 301 is etched in FIG. 3E, [0031], inasmuch as is shown in FIG. 3e of Applicant’s disclosure) through the opening to form a conduction hole extending to the doped region (FIG. 3E, [0031]); and
filling the conduction hole with conductive material (metal plug 310, FIG. 3A, [0030]) to form the conducting path,
wherein, the side wall (312) is positioned between the conductive material (310) and the sidewall of the opening (FIG. 3A), thus being used for reducing a transverse dimension of the conducting path (width SBCO’<CO’ in FIG. 3A)
Hsieh does not explicitly teach in the embodiment of FIGS. 3A-3B the contact interlayer is a dielectric layer.
However, Hsieh teaches in the embodiment of FIG. 5A the contact interlayer 503’ ([0033]) is a dielectric layer (non-doped silicate glass, [0033]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the contact interlayer in the embodiment of FIG. 3A-3D such that it is a dielectric material, as taught in the embodiment of FIG. 5A, in order to affirm that the contact interlayer is formed of a dielectric material.
Regarding claim 2, Hsieh teaches the method according to claim 1. Hsieh further teaches wherein a step of forming the side wall on the sidewall of the opening comprises:
forming a barrier layer (dielectric layer, FIG. 3C, [0031]) on a surface of the contact interlayer and in the opening;
removing a portion of the barrier layer which is located on the surface of the contact interlayer, and removing a portion of the barrier layer which is located at the bottom of the opening (FIG. 3D, [0031]), wherein the side wall (312) is formed by a portion of the barrier layer which is located on the sidewall of the opening (FIG. 3D).
Hsieh does not explicitly teach in the embodiment of FIGS. 3A-3B the contact interlayer is a dielectric layer.
However, Hsieh teaches in the embodiment of FIG. 5A the contact interlayer 503’ ([0033]) is a dielectric layer (non-doped silicate glass, [0033]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the contact interlayer in the embodiment of FIG. 3A-3D such that it is a dielectric material, as taught in the embodiment of FIG. 5A, in order to create a trench MOSFET device ([0033]).
Regarding claim 4, Hsieh teaches in 3A-3D and related text, A manufacturing method of a trench-type MOSFET device (300, FIG. 3A, [0030]), comprising:
forming an epitaxial layer (301, FIG. 3A, [0030]) on a first surface of a semiconductor substrate (upper surface of 302, FIG. 3A, [0030]);
forming a trench structure (304/307/308 are formed in a gate trench, FIG. 3A, [0030]), a body region (306, FIG. 3A, [0030]) and a source region (305, FIG. 3A, [0030]) in the epitaxial layer (301; body region 306 and source region 305 are formed inside epitaxial layer 301, [0030]), wherein the body region (306) is in contact with the trench structure (304/307/308), and the source region (305) is located in the body region (306);
forming a contact interlayer (311, FIG. 3B, [0030]) on a surface of the epitaxial layer (301);
forming an opening (opening with width CO’, FIG. 3B, [0031]) in the contact interlayer (311; FIG. 3B);
forming a side wall (312, FIG. 3D, [0030]) on a sidewall of the opening;
etching the epitaxial layer (306 of semiconductor layer 301 is etched in FIG. 3E, [0031], inasmuch as is shown in FIG. 3e of Applicant’s disclosure) through the opening to form a conduction hole extending to the body region (306, FIG. 3E, [0031]); and
filling the conduction hole with conductive material (metal plug 310, FIG. 3A, [0030]) to form a conducting path,
wherein the side wall (312) is positioned between the conductive material (310) and the sidewall of the opening (FIG. 3A), thus being used for reducing a transverse dimension of the conducting path (width SBCO’<CO’ in FIG. 3A).
Hsieh does not explicitly teach in the embodiment of FIGS. 3A-3B the contact interlayer is a dielectric layer.
However, Hsieh teaches in the embodiment of FIG. 5A the contact interlayer 503’ ([0033]) is a dielectric layer (non-doped silicate glass, [0033]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the contact interlayer in the embodiment of FIG. 3A-3D such that it is a dielectric material, as taught in the embodiment of FIG. 5A, in order to affirm that the contact interlayer is formed of a dielectric material.
Regarding claim 5, Hsieh teaches the manufacturing method according to claim 4. Hsieh further teaches wherein a cell region of the trench-type MOSFET device (see annotated FIG. 3A below) is a region surrounded by an outer boundary of the body region (306 on both sides of cell region), and the conducting path (310) is in contact with the outer boundary of the body region (310 is in physical and electrical contact with 306).
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Annotated FIG. 3A (Hsieh)
Regarding claim 6, Hsieh teaches the manufacturing method according to claim 5. Hsieh further teaches wherein a step of forming the side wall on the sidewall of the opening comprises:
forming a barrier layer (dielectric layer, FIG. 3C, [0031]) on a surface of the contact interlayer and in the opening;
removing a portion of the barrier layer which is located on the surface of the contact interlayer, and removing a portion of the barrier layer which is located at the bottom of the opening (FIG. 3D, [0031]), wherein the side wall (312) is formed by a portion of the barrier layer which is located on the sidewall of the opening (FIG. 3D).
Hsieh does not explicitly teach in the embodiment of FIGS. 3A-3B the contact interlayer is a dielectric layer.
However, Hsieh teaches in the embodiment of FIG. 5A the contact interlayer 503’ ([0033]) is a dielectric layer (non-doped silicate glass, [0033]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the contact interlayer in the embodiment of FIG. 3A-3D such that it is a dielectric material, as taught in the embodiment of FIG. 5A, in order to create a trench MOSFET device ([0033]).
Regarding claim 8, Hsieh teaches the manufacturing method according to claim 5. Hsieh further teaches wherein after a step of filling the conduction hole (hole of width SBCO’ in FIG. 3E) with conductive material to form the conducting path (310), the manufacturing method further comprises: forming a second conductive layer (314, FIG. 3A, [0030]) on a second surface of the semiconductor substrate (lower surface of 302; this step is shown inasmuch as is shown in Applicant’s FIG. 4).
Regarding claim 13, Hsieh teaches the method according to claim 1. Hsieh further teaches wherein a side surface of the conducting path (310) extends smoothly from a top of the side wall (312) to a bottom of the conductive hole (hole with width SBCO’, FIG. 3A/3E), without forming a stepped structure.
Regarding claim 14, Hsieh teaches the method according to claim 1. Hsieh further teaches wherein at least part of the conducting path (310) located in the doped region (306) has a transverse dimension (SBCO’, FIG. 3A) smaller than a minimum process dimension (CO’, FIG. 3A) allowed by a manufacturing equipment for performing the etching (the limitation is understood as 310 having a transverse dimension smaller than a transverse dimension of the opening, as explained in the rejection made under 35 U.S.C. 112(b) in the Instant Office Action).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Hsieh in US 2014/0291753 A1 (hereinafter Hsieh) in view of Hshieh in US 2006/0273382 A1 (hereinafter Hshieh).
Regarding claim 3, Hsieh teaches the method according to claim 1. Hsieh further teaches wherein a step of forming the opening in the contact interlayer comprises a dry oxide etch ([0031]).
Hsieh does not explicitly teach the contact interlayer is a dielectric layer; and forming a patterned mask layer on the dielectric layer; forming the opening by transferring a pattern of the mask layer to the dielectric layer through the mask layer.
Hsieh teaches in the embodiment of FIG. 5A the contact interlayer 503’ ([0033]) is a dielectric layer (non-doped silicate glass, [0033]).
Hshieh teaches in FIG. 3F and related text, forming a patterned mask layer on a dielectric layer (240, [0024]); forming an opening (242, [0024]) by transferring a pattern of the mask layer to the dielectric layer (240) through the mask layer using an oxide etch ([0024]).
Hsieh and Hshieh are analogous art to the claimed invention because they are directed to trench MOSFET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsieh in view of Hshieh because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Hsieh:
such that the contact interlayer is a dielectric material, as taught by Hsieh in the embodiment of FIG. 5A, in order to create a trench MOSFET device ([0033]); and
to include forming a patterned mask layer on the dielectric layer; forming the opening by transferring a pattern of the mask layer to the dielectric layer through the mask layer, as taught by Hshieh, with the purpose of selectively etching openings in the dielectric layer in order to form contact trenches. Additionally, the use of patterned mask layers to form openings is well known in the art.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Hsieh in US 2014/0291753 A1 (hereinafter Hsieh) in view of Cai et al. in US 2019/0109216 (hereinafter Cai).
Regarding claim 7, Hsieh teaches the manufacturing method according to claim 5. Hsieh further teaches wherein the trench structure comprises: a trench located in the epitaxial layer (304/307/308 are formed in a gate trench in epitaxial layer 301, FIG. 3A, [0030]); a first gate conductor (307, [0030]), a gate oxide layer (308, [0030]), and the gate oxide layer (308) is located on an upper-part sidewall of the trench.
Hsieh does not explicitly teach a second gate conductor and an insulating layer in the trench, the insulating layer covers around the sidewall of the trench and the first gate conductor is surrounded by the insulating layer, and the second gate conductor is located on a portion, which is located in an upper part of the trench, of the insulating layer.
Cai teaches in FIG. 1 and related text, a trench structure (102/104/105/108/109, [0012]) comprises: a second gate conductor (109, [0012]) and an insulating layer (102/105, [0012]) in the trench, the insulating layer (102/105) covers around the sidewall of the trench and a first gate conductor (104, [0012]) is surrounded by the insulating layer (102/105), and the second gate conductor (109) is located on a portion, which is located in an upper part of the trench, of the insulating layer (102/105).
Hsieh and Cai are analogous art to the claimed invention because they are directed to trench MOSFET devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hsieh in view of Cai because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the trench structure of Hsieh to include a second gate conductor and an insulating layer in the trench, the insulating layer covers around the sidewall of the trench and the first gate conductor is surrounded by the insulating layer, and the second gate conductor is located on a portion, which is located in an upper part of the trench, of the insulating layer, as taught by Cai, with the purpose of providing a shield electrode to reduce gate-drain capacitance (Cai, [0003]).
Response to Arguments
Applicant’s remarks on page 8 regarding the status of the claims in the Instant Application are acknowledged. Applicant requests in the first paragraph of page 8 that claims 9-12, which have been withdrawn in response to the restriction requirement mailed on 01/03/2025, be rejoined and examined in as part of the Instant Office Action.
In response, the Examiner will not allow rejoinder of claims 9-12 in the Instant Office Action since claims 1-8 and 13-14 stand rejected.
Applicant’s arguments on pages 8-9 regarding the drawing objections made in the Non-Final Office Action mailed on 03/27/2025 (hereinafter previous Office Action) are acknowledged. Applicant has submitted a replacement drawing sheet for FIG. 4 in which reference characters are now doubly labeled (e.g. 335 [Wingdings font/0xE0] 335(220), 341[Wingdings font/0xE0] 341(230), etc.), and refers to the specification for alleged support of the sequence of the claimed method steps.
In response, the Examiner does not find the arguments or replacement drawing sheet acceptable to overcome the drawing objection in the previous Office Action. Since claim 4 is a method claim, the drawings must show every feature (i.e. method step) of the invention specified in the claims. Therefore, claim features which imply a sequence, such as “forming a trench structure, a body region and a source region in the epitaxial layer” as recited in line 4, must be clearly shown in the proper sequence or the features cancelled from the claim. The drawing objection is maintained, and an additional drawing objection is noted related to claim 3 (see the Drawings section on page 2).
Applicant’s remarks on pages 10-11 regarding amendments in response to claim objections and rejections under 35 USC 112 made in the previous Office Action are acknowledged.
In response, the Examiner finds the amendments sufficient to provide clarity enough to overcome the objections and rejections under USC 112 and hereby withdraws those objections/rejections in the Instant Office Action.
Applicant’s arguments on pages 11-18 with respect to rejections under 35 USC 102 and 103 of claims 1 and 4, respectively, have been considered but are moot because the new ground of rejection does not rely on the specific combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant’s arguments on page 18 regarding the dependent claims are acknowledged. Applicant argues dependent claims 2-3, 5-8, and 13-14 should be allowed based on their dependency on independent claims 1 and 4.
In response, this argument is moot since the Examiner does not identify any allowable subject matter in independent claims 1 and 4.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHEN LEE JOHNSON JR whose telephone number is (571)270-3217. The examiner can normally be reached Mon-Fri: 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571)272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S.L.J./Examiner, Art Unit 2811
/ORI NADAV/Primary Examiner, Art Unit 2811
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