Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed 09/14/2022 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. It has been placed in the application file, but the information referred to therein has not been considered. This objection specifically refers to the Non-Patent Literature document titled “A Self-timed Ring Based True Random Number Generator”.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the clock mentioned in the 35 USC 112(b) rejection based on MPEP 2173.05(a) below must be shown or the features canceled from the claims. No new matter should be entered.
The drawings are also objected to under 37 CFR 183(a) for of the following reasons: regarding Figure 4A, NM3 is drawn as PMOS, it should be drawn as NMOS; PM4 is drawn as NMOS, it should be drawn as PMOS. Regarding Figure 4B, NM1 and NM2 are drawn as PMOS, they should be drawn as NMOS.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 11 is objected to under 37 CFR 1.71(a) because of the following informality: on line 4, "a token that does not change the output state of the previous clock cycle" should read "a token that changes the output state of the previous clock cycle". Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 6, 11 and 16 all reference “a clock” in relation to a self-timed ring oscillator (STRO). MPEP 2173.05(a) states every term used in a claim should be apparent from the prior art or from the specification and drawings at the time the application is filed. Self-timed rings (STR) are a known term in the art. Prior art features STRO that do not contain a clock beyond sampling. See Choe et al., “A Self-Timed Ring based TRNG with Feedback Structure for FPGA Implementation”, Figure 1; Martin et al., “A New TRNG Based on Coherent Sampling With Self-Timed Rings”, Figure 3; Zhang et al., “A Self-Timed Ring Based True Random Number Generator on FPGA”, Figures 1 and 2; Gimenez et al., “Self-timed Ring based True Random Number Generator: Threat model and countermeasures”, Figures 1, 3 and 5; and Elissati et al., “Self-Timed Rings: A Promising Solution for Generating High-Speed High Resolution Low-Phase Noise Clocks”, Figures 1, 2, 4 and 5. The specification only describes a STRO like that which is described in the prior art, which does not include a clock.
The only clock that is mentioned in the specification or the drawings is the sampling clock SCLK in the sampling circuit shown in Figure 2C. A clock is not shown in relation to any of the STR in the specification’s Figures 1, 2A, 3A, 4B, or 5. Therefore, the claims are indefinite.
Claims 2-10 are rejected by virtue of their dependency on claim 1. Claims 12-15 are rejected by virtue of their dependency on claim 11. Claims 17-20 are rejected by virtue of their dependency on claim 16.
A response to this rejection could include amendments to the claim deleting language from claims 1, 6, 11 and 16 concerning the clock or clock cycles in relation to a STRO.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 9-10, 16 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Cherkaoui et al., “A Self-timed Ring Based True Random Number Generator”, hereinafter Cherkaoui, in view of Cryptography Stack Exchange, “How to mix external entropy to a random number generator?”, hereinafter Stack Exchange, further in view of Amiri et al., “Combinational Logic Design Practices (3)”, hereinafter Amiri, and further in view of Kaysici et al., “Duty Cycle Correction Circuit and Its Application for High Speed Random Number Generation”, hereinafter Kaysici.
Regarding claim 1, Cherkaoui discloses a self-timed ring (STR) having a plurality of ring stages each configured to generate, in response to a clock, either a bubble that does not change an output state of a previous clock cycle, or a token that changes the output state of the previous clock cycle (Figure 6) and a sampling circuit configured to sample a random number using a logic operation from the duty-corrected output values (Figure 4, Entropy extractor).
Cherkaoui does not disclose an initial random number generator.
However, Stack Exchange discloses adding an initial random number generator (RNG) configured to generate an initial random number and combining the outputs. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a second STRO and combine their inputs via XOR because “The xor of two random sources has at least as much entropy as the maximum of the entropies of both sources, as long as both random sources are independent.” (answer by itsme) Combining two independent sources will at minimum have the entropy of both sources.
Cherkaoui and Stack Exchange together do not disclose configuring the STRO to receive the output of the initial random number generator.
However, Amiri discloses daisy chaining XOR gates together to form one output (Figure 3a). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit disclosed by Cherkaoui and Stack Exchange to use the daisy chain configuration to standardize the interface between the second RNG and the post-processing, increasing interoperability.
Cherkaoui, Stack Exchange and Amiri together do not disclose a duty correction circuit.
However, Kaysici discloses a duty corrector configured to adjust a duty of an output value of each of the ring stages (Figure 3). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit disclosed by Cherkaoui, Stack Exchange and Amiri to add a duty correction circuit as disclosed by Kaysici to improve the throughput of the random number generator by 12.3 times (Section V).
Regarding claim 2, Cherkaoui discloses a true random number generator (TRNG) (Abstract).
Regarding claim 9, Kaysici discloses the duty corrector includes a flip-flop configured to output a divided clock using an output value of each of the plurality of ring stages as the clock (Figure 3).
Regarding claim 10, Cherkaoui discloses the sampling circuit includes flip-flops configured to perform an XOR operation on two adjacent divided clocks among the plurality of ring stages, and output, in response to a sampling clock, a value obtained by performing the XOR operation as a corresponding bit (Figure 4, Entropy extractor).
Regarding claim 16, it is a method claim corresponding to apparatus claims 1 and 2, and is rejected for the same reasons.
Regarding claims 19 and 20, they are method claims corresponding to apparatus claim 1 and are rejected for the same reasons.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Cherkaoui, Stack Exchange, Amiri, and Kaysici as applied to claim 1 above, and further in view of Murray et al. (US 11,126,404), hereinafter Murray.
Regarding claim 3, the combination of Cherkaoui, Stack Exchange, Amiri, and Kaysic does not disclose the initial random number generator being a pseudorandom number generator (PRNG).
However, Murray discloses mixing a PRNG (Figure 1, 14, referred to as a “deterministic random number generator” (DRNG)) with a TRNG (Figure 1, 12) using an XOR function (Figure 1, 20).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use modify the circuit disclosed by the combination of Cherkaoui, Stack Exchange, Amiri, and Kaysici to replace the initial STRO with a PRNG because a PRNG and a TRNG have different failure conditions (Column 2, lines 9-14), increasing resilience.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Cherkaoui, Stack Exchange, Amiri and Kaysici as applied to claim 1 above, and further in view of Moreira et al., "Impact of C-Elements in Asynchronous Circuits”, hereinafter Moreira.
Regarding claim 6, Cherkaoui discloses that each of the plurality of ring stages is configured to receive a first input value that is an output value of another ring stage and a second input value that is an output value of another ring stage, and outputs an output value (Figure 5); but the combination of Cherkaoui, Stack Exchange, Amiri and Kaysici do not specifically disclose the architecture of the STRO.
However, Moreira discloses that when the first input value and the second input value are the same, each of the plurality of ring stages outputs the first input value, and when the first input value and the second input value are not the same, each of the plurality of ring stages maintains the output value (Figure 1).
Regarding claim 7, Moreira discloses that each of the plurality of ring stages includes: a first p-channel metal oxide semiconductor (PMOS) transistor having a source connected to a power supply terminal and a gate that receives the second input value (Figure 2(c), ILF0); a second PMOS transistor having a source connected to a drain of the first PMOS transistor and a gate that receives the first input value (Figure 2(c), ILF1); a third PMOS transistor having the source connected to the power supply terminal, a drain configured to output an output value of each of the plurality of ring stages, and a gate connected to a drain of the second PMOS transistor (Figure 2(c), OD0); a fourth PMOS transistor having the source connected to the power supply terminal, a drain connected to the drain of the second PMOS transistor, and a gate connected to the drain of the third PMOS transistor (Figure 2(c), SK0); a first n-channel metal oxide semiconductor (NMOS) transistor having the drain connected to the drain of the second PMOS transistor and the gate that receives the first input value (Figure 2(c), ILF2); a second NMOS transistor having a drain connected to a source of the first NMOS transistor, a source connected to a ground terminal, and the gate that receives the second input value (Figure 2(c), ILF3); a third NMOS transistor having a drain connected to the drain of the third PMOS transistor, the source connected to the ground terminal, and a gate connected to the drain of the second PMOS transistor (Figure 2(c), OD1); and a fourth NMOS transistor having the drain connected to the drain of the second PMOS transistor, the source connected to the ground terminal, and the gate connected to the drain of the third PMOS transistor (Figure 2(c), SK1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit disclosed by Cherkaoui, Stack Exchange, Amiri, and Kaysici to use the weak feedback architecture disclosed by Moreira for the STRO to minimize the cell area and parasitic capacitance (Table I).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Cherkaoui, Stack Exchange, Amiri and Kaysici as applied to claim 16 above, and further in view of Oerlemans (US 6,807,553).
Regarding clam 17, Cherkaoui, Stack Exchange, Amiri and Kaysici do not disclose that each ring of the STROs would be of different length.
However, Oerlemans discloses ring oscillators the number of stages in each ring differ from each other (Figure 1: 10, 20 and 30). Oerlemans and Cherkaoui are considered analogous because they are both true random number generators based on stages. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the oscillators as disclosed by Cherkaoui, Stack Exchange, Amiri and Kaysici to prevent the oscillators from locking together (Column 2, lines 16-23, preventing the TRNG from becoming deterministic (Column 1, lines 44-46).
Allowable Subject Matter
Claims 4-5, 8 and 18 would be allowable if rewritten to overcome the rejections under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Regarding claims 4, the prior art of record does not teach or suggest a combination as claimed including where the STR oscillator is configured to set, in an initialization mode, an initial output value of each of the plurality of ring stages using the initial random number. Cherkaoui teaches a FPGA implementation of STRO, but does not disclose setting the initial state. Figure 4 does not show control signals that would set the initial state and none are described in sections III and IV. None of the STROs cited in the 35 USC 112(b) rejection above disclose control signals that would set the initial state. Claim 5 would be allowable by virtue of its dependency on claim 4.
Regarding claim 8, the prior art of record does not teach or suggest a combination as claimed including: a fifth NMOS transistor having a drain connected to a source of the third NMOS transistor, the source connected to the ground terminal, and a gate that receives the activation signal; and a sixth NMOS transistor having a drain connected to a source of the fourth NMOS transistor, the source connected to the ground terminal, and the gate that receives the activation signal. Moreira teaches multiple STRO implementations, but does not disclose the CMOS configuration as claimed relating PM5, PM6, NM5, NM6 or an activation signal. None of the implementations in Figure 2 feature the claimed CMOS configuration or activation signal, and none are described in sections III or IV. Shams et al., "Modeling and Comparing CMOS Implementations of the C-Element", teaches additional implementations of Muller C-elements, but does not disclose the CMOS configuration as claimed relating PM5, PM6, NM5, NM6 or an activation signal. None of the implementations in Figure 3 feature the claimed CMOS configuration or an activation signal, and none are described in sections III or IV. Kurokawa (US 10,418,980) discloses a C-element that includes a third signal L, but there are no extra PMOS transistors beyond the input and the inverters. None are shown in Figure 1A or described in column 5, line 59 to column 7, line 55.
Regarding claim 18, it is a method claim corresponding to apparatus claim 4, and would be allowable for the same reasons.
Claims 11-15 would be allowable if rewritten or amended to overcome the rejections under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action. Claim 11 would be allowable for the same reason as claims 4 and 18 as described above, and claims 12-15 would be allowable by virtue of their dependency on claim 11.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Le Quere (US 6,714,955) discloses a TRNG used to seed a hardware PRNG. Mascagni (US 10,503,475) discloses using a TRNG to initialize a PRNG.
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/M.S./
Matthew StrappExaminer, Art Unit 2182 (571) 272-9343
/ANDREW CALDWELL/Supervisory Patent Examiner, Art Unit 2182
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