DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 20 are pending.
Response to Arguments
Applicant's arguments filed 18 February 2026 have been fully considered but they are not persuasive.
Applicant argues the rejection of claim 15 under 35 U.S.C. 112 2nd paragraph, stating that the term “second half-width mode” is expressly defined in the claim set and the specification. However, the Examiner respectfully disagrees. Claim 15 and parent independent claim 9 do not previously recite or define a “second half-width mode” in such a way as to provide proper antecedent basis for such a limitation. Additionally, although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). It is unclear, from the claims as written, what Applicant intends to claim utilizing the term “the second half-width mode.” Therefore, the scope of claim 15 is unclear and the claim is indefinite under 35 U.S.C 112 2nd paragraph.
Applicant argues that the prior art of record fails to teach or suggest a “first-half width mode under which a subset of the plurality of DQ lines of the first memory channel operates as a half-width bus and the first memory channel is enabled to access all the plurality of memory banks of the device” as recited be claim 1. Specifically, Applicant states that Riho (US Patent No. 8,243,486) fails to teach the above limitation. However, the Examiner respectfully disagrees. In the rejection of claim 1 in the office action mailed 18 November 2025, the Examiner relies on Bains (US Patent Application Publication No. 2016/0092383) to teach the above limitation. Specifically, the Examiner states “wherein the DRAM device is configured to be selectively operated in a first half-width mode (Bains; Figure 7 Items 708 and 710) under which a subset of the plurality of DQ lines for the first memory channel operate as a first half-width DQ data bus (Bains; Figure 4, Paragraphs [0047] – [0049]) and the first memory channel is enabled to access all the plurality of memory banks (Bains; Paragraph [0050]).” The cited portions of Bains teach the above limitations of claim 1. Therefore, the prior art of record teaches the limitations of at least claim 1.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 15 recites the limitation "the second half-width mode" in lines 1 and 2 of the claim. There is insufficient antecedent basis for this limitation in the claim. Claim 15 depends directly from independent claim 9. However, independent claim 9 does not recite a “second half-width mode.” Instead, claim 14 is the first claimed recitation of a “second half-width mode.” Claim 7 recites similar limitations to claim 15, and depends directly from claim 6, which recites similar limitations to claim 14. Therefore, in order to understand the context of the claimed limitations and consistent with the previous claim dependency trend, the Examiner has interpreted claim 15 and depending directly from claim 14.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4 – 10, 13 – 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. 2016/0092383 (hereinafter Bains) in view of US Patent No. 8,243,486 (hereinafter Riho).
As per claim 1, Bains teaches a Dynamic Random Access Memory (DRAM) device (Bains; Figure 1 Item 120, Figure 2 Item 200, Figure 3 Item 300, Figure 4 Item 400, Figure 5 Item 500, Figure 6 Item 600, Paragraph [0019]), comprising: a plurality of bank groups (Bains; Figure 3 Item 302-0 and 302-1, Figure 4 Item 402-0 and 402-1, Figure 5 Items 502-0 and 502-1, Figure 6 Items 602-0 and 602-1), each bank group comprising multiple memory banks (Bains; Figure 3 Item 302-0 and 302-1, Figure 4 Item 402-0 and 402-1, Figure 5 Items 502-0 and 502-1, Figure 6 Items 602-0 and 602-1); and memory channel input/output (I/O) circuitry for first (Bains; Figure 3 “DQ_A NIBBLE 0,” “C/A_A,” and “DQ_A NIBBLE 1,” Figure 4 “DQ_A BYTE 0,” “C/A_A,” and “DQ_A BYTE 1,” Figure 5 “DQ_A BYTE 0,” “C/A_A,” and “DQ_A BYTE 1,” Figure 6 “DQ_A BYTE 0,” “MUX 510-A,” “C/A_A,” and “DQ_A BYTE 1”) and second memory channels (Bains; Figure 3 “DQ_B NIBBLE 0,” “C/A_B,” and “DQ_B NIBBLE 1,” Figure 4 “DQ_B BYTE 0,” “C/A_B,” and “DQ_B BYTE 1,” Figure 5 “DQ_B BYTE 0,” “C/A_B,” and “DQ_B BYTE 1,” Figure 6 “DQ_B BYTE 0,” “MUX 510-B,” “C/A_B,” and “DQ_B BYTE 1”), the memory channel I/O circuitry for each of the first and second memory channels comprising a plurality of signal lines including one or more clock signal lines (Bains; Paragraph [0045]), a set of Command/Address (C/A) signal lines (Bains; Figure 3 “C/A_A” and “C/A_B,” Figure 4 “C/A_A” and “C/A_B,” Figure 5 “C/A_A” and “C/A_B,” and Figure 6 “C/A_A” and “C/A_B”), and a plurality of DQ lines for read data and write data (Bains; Figure 3 “DQ_A NIBBLE 0,” “DQ_A NIBBLE 1,” “DQ_B NIBBLE 0,” and “DQ_B NIBBLE 1,” Figure 4 “DQ_A BYTE 0,” “DQ_A BYTE 1,” “DQ_B BYTE 0,” and “DQ_B BYTE 1,” Figure 5 “DQ_A BYTE 0,” “DQ_A BYTE 1,” “DQ_B BYTE 0,” and “DQ_B BYTE 1,” and Figure 6 “DQ_A BYTE 0,” “DQ_A BYTE 1,” “DQ_B BYTE 0,” and “DQ_B BYTE 1”), wherein the DRAM device is configured to be selectively operated in a first half-width mode (Bains; Figure 7 Items 708 and 710) under which a subset of the plurality of DQ lines for the first memory channel operate as a first half-width DQ data bus (Bains; Figure 4, Paragraphs [0047] – [0049]) and the first memory channel is enabled to access all the plurality of memory banks (Bains; Paragraph [0050]) (See “Response to Arguments” presented above).
Bains does not explicitly teach wherein each memory bank includes a plurality of memory cells arranged in rows and columns.
However, Riho teaches a memory system in which a DRAM device includes memory banks including a plurality of memory cells arranged in rows and columns (Riho; Col 6 Lines 52 – 55).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Bains to include the cell, row, and column arrangement because doing so is a well-known and commonly used arrangement in DRAM memory devices (Riho; Col 6 Lines 52 – 55).
As per claim 4, Bains in combination with Riho teaches the invention as described per claim 1 (see rejection of claim 1 above). Bains teaches implementing the DRAM memory device being organized in groups in any of a number of different ways (Bains; Paragraph [0033]).
Bains in combination with Riho does not explicitly teach wherein the DRAM device includes 32 banks arranges in 8 bank groups.
However, the Examiner submits that implementing the DRAM device including 32 banks arranged in 8 bank groups would be obvious to try. Bains teaches implementing the DRAM memory device being organized in groups in any of a number of different ways (Bains; Paragraph [0033]). While not explicitly describing 32 banks arranged in 8 bank groups, it would be obvious to try different amounts of banks and bank groups in order to fine tune system performance, cost, size, and complexity. A finite number of possible amounts of banks and bank groups would be reasonable before the cost, size, or complexity of the system became undesirable.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Bains in combination with Riho to include the DRAM including 32 banks arranged in 8 bank groups because doing so would have been obvious to try in order to balance and tune system performance, cost, size, and complexity.
As per claims 5 and 8, Bains in combination with Riho teaches the invention as described per claims 1 and 6 (see rejections of claim 1 above and claim 6 below). Bains teaches wherein the half-width data bus has a width of “N/2” bits (Bains; Paragraph [0016]).
Bains in combination with Riho does not explicitly teach wherein the first half-width data bus has a width of 12 bits.
However, the Examiner submits that implementing the first half-width data bus as having a width of 12 bits would be obvious to try. Bains teaches wherein the half-width data bus has a width of “N/2” bits (Bains; Paragraph [0016]). While not explicitly describing a width of 12 bits, it would be obvious to try different bus widths in order to fine tune system performance, cost, size, and complexity. A finite number of possible bus widths would be reasonable before the cost, size, or complexity of the system became undesirable.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Bains in combination with Riho to include the 12 bit bus width because doing so would have been obvious to try in order to balance and tune system performance, cost, size, and complexity.
As per claims 6 and 14, Bains also teaches wherein the DRAM device is configured to be selectively operated in a second half-width mode (Bains; Figure 5) under which a subset of the plurality of DQ lines for each of the first and second memory channels operate as a half-width DQ data bus (Bains; Figure 5), wherein when the DRAM device is operated in the second half-width mode, the first and second memory channels are enabled to access respective first (Bains; Figure 5 Items 502-0 and 502-1) and second (Bains; Figure 5 Items 504-0 and 504-1) of the plurality of memory banks, wherein none of the plurality of memory banks is included in the first and second portions of memory banks.
As per claims 7 and 15, Bains also teaches wherein when the DRAM device is operated in the second half-width mode the first memory channel and second memory channel are enabled to operate independently to concurrently transfer data over their respective half-width data buses (Bains; Paragraphs [0053] and [0054]).
As per claim 9, Bains teaches a memory module comprising: module memory channel input/output (I/O) circuitry (Bains; Figure 1 Item 124) configured to interface with first and second memory channels (Bains; Paragraph [0032]) for a memory controller (Bains; Figure 1 Item 112), comprising a first plurality of signal lines (Bains; Figure 1 Item 130) including one or more clock signal lines (Bains; Paragraphs [0045] and [0055]), a set of Command/Address (C/A) signal lines (Bains; Paragraph [0023]), and a plurality of DQ lines for read data and write data (Bains; Paragraph [0023]); and a plurality of Dynamic Random Access Memory (DRAM) devices (Bains; Figure 1 Item 120, Figure 2 Item 200, Figure 3 Item 300, Figure 4 Item 400, Figure 5 Item 500, Figure 6 Item 600, Paragraph [0019]), each comprising, a plurality of bank groups (Bains; Figure 3 Item 302-0 and 302-1, Figure 4 Item 402-0 and 402-1, Figure 5 Items 502-0 and 502-1, Figure 6 Items 602-0 and 602-1), each bank group comprising multiple memory banks (Bains; Figure 3 Item 302-0 and 302-1, Figure 4 Item 402-0 and 402-1, Figure 5 Items 502-0 and 502-1, Figure 6 Items 602-0 and 602-1); device memory channel I/O circuitry for a first device memory channel (Bains; Figure 3 “DQ_A NIBBLE 0,” “C/A_A,” and “DQ_A NIBBLE 1,” Figure 4 “DQ_A BYTE 0,” “C/A_A,” and “DQ_A BYTE 1,” Figure 5 “DQ_A BYTE 0,” “C/A_A,” and “DQ_A BYTE 1,” and Figure 6 “DQ_A BYTE 0,” “MUX 510-A,” “C/A_A,” and “DQ_A BYTE 1”) comprising a second plurality of signal lines including one or more clock signal lines (Bains; Paragraph [0045]), a set of C/A signal lines (Bains; Figure 3 “C/A_A,” Figure 4 “C/A_A,” Figure 5 “C/A_A,” and Figure 6 “C/A_A”), and a set of DQ lines (Bains; Figure 3 “DQ_A NIBBLE 0” and “DQ_A NIBBLE 1,” Figure 4 “DQ_A BYTE 0” and “DQ_A BYTE 1,” Figure 5 “DQ_A BYTE 0” and “DQ_A BYTE 1,” and Figure 6 “DQ_A BYTE 0” and “DQ_A BYTE 1”) for read and write data, wherein for each DRAM device the device memory channel I/O circuitry for the first device memory channel is coupled to the module memory channel I/O circuitry for the first or second memory channel (Bians; Figure 2), and wherein at least one of the plurality of DRAM devices is configured to be selectively operated in a first half-width mode (Bains; Figure 7 Items 708 and 710) under which a subset of the plurality of DQ lines for the first device memory channel operate as a first half-width DQ data bus (Bains; Figure 4, Paragraphs [0047] – [0049]) and the first memory channel is enabled to access all the plurality of memory banks in the DRAM device (Bains; Paragraph [0050]).
Bains does not explicitly teach wherein each memory bank includes a plurality of memory cells arranged in rows and columns.
However, Riho teaches a memory system in which a DRAM device includes memory banks including a plurality of memory cells arranged in rows and columns (Riho; Col 6 Lines 52 – 55).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Bains to include the cell, row, and column arrangement because doing so is a well-known and commonly used arrangement in DRAM memory devices (Riho; Col 6 Lines 52 – 55).
As per claim 10, Bains also teaches wherein each of the plurality of DRAM devices is configured to be selectively operated in the first half-width (Bains; Figure 7 Items 708 and 710), and wherein a first portion of the plurality of DRAM devices are coupled to the module memory I/O circuitry for the first memory channel (Bains; Paragraph [0021]) and a second portion of the plurality of DRAM devices are coupled to the module memory channel I/O circuitry for the second memory channel (Bains; Paragraph [0021]).
As per claim 13, Bains also teaches where a DRAM device includes device memory channel I/O circuitry for a second device memory channel comprising a third plurality of signal lines including one or more clock signal lines (Bains; Paragraph [0045]), a set of C/A signal lines (Bains; Figure 3 “C/A_B,” Figure 4 “C/A_B,” Figure 5 “C/A_B,” and Figure 6 “C/A_B”), and a set of DQ lines (Bains; Figure 3 “DQ_B NIBBLE 0” and “DQ_B NIBBLE 1,” Figure 4 “DQ_B BYTE 0” and “DQ_B BYTE 1,” Figure 5 “DQ_B BYTE 0” and “DQ_B BYTE 1,” and Figure 6 “DQ_B BYTE 0” and “DQ_B BYTE 1”) for read and write data.
As per claim 16, Bains teaches a system comprising: a memory controller (Bains; Figure 1 Item 114) having first and second memory channel interfaces having I/O circuitry (Bains; Figure 1 Item 114) for first and second memory channels (Bains; Paragraph [0032]), each memory channel interface comprising a plurality of signal lines (Bains; Figure 1 Item 130) including one or more clock signal lines (Bains; Paragraphs [0045] and [0055]), a set of Command/Address (C/A) signal lines (Bains; Paragraph [0023]), and a plurality of DQ lines for read data and write data (Bains; Paragraph [0023]); and a plurality of Dynamic Random Access Memory (DRAM) devices (Bains; Figure 1 Item 120, Figure 2 Item 200, Figure 3 Item 300, Figure 4 Item 400, Figure 5 Item 500, Figure 6 Item 600, Paragraph [0019]), each operatively coupled to the first or second memory channel interface for the memory controller (Bains; Figure 2) and including, a plurality of bank groups (Bains; Figure 3 Item 302-0 and 302-1, Figure 4 Item 402-0 and 402-1, Figure 5 Items 502-0 and 502-1, Figure 6 Items 602-0 and 602-1), each bank group comprising multiple memory banks (Bains; Figure 3 Item 302-0 and 302-1, Figure 4 Item 402-0 and 402-1, Figure 5 Items 502-0 and 502-1, Figure 6 Items 602-0 and 602-1); device memory channel I/O circuitry for a first device memory channel (Bains; Figure 3 “DQ_A NIBBLE 0,” “C/A_A,” and “DQ_A NIBBLE 1,” Figure 4 “DQ_A BYTE 0,” “C/A_A,” and “DQ_A BYTE 1,” Figure 5 “DQ_A BYTE 0,” “C/A_A,” and “DQ_A BYTE 1,” and Figure 6 “DQ_A BYTE 0,” “MUX 510-A,” “C/A_A,” and “DQ_A BYTE 1”) comprising a second plurality of signal lines including one or more clock signal lines (Bains; Paragraph [0045]), a set of C/A signal lines (Bains; Figure 3 “C/A_A,” Figure 4 “C/A_A,” Figure 5 “C/A_A,” and Figure 6 “C/A_A”), and a set of DQ lines (Bains; Figure 3 “DQ_A NIBBLE 0” and “DQ_A NIBBLE 1,” Figure 4 “DQ_A BYTE 0” and “DQ_A BYTE 1,” Figure 5 “DQ_A BYTE 0” and “DQ_A BYTE 1,” and Figure 6 “DQ_A BYTE 0” and “DQ_A BYTE 1”) for read and write data, wherein at least one of the plurality of DRAM devices is configured to be selectively operated in a first half-width mode (Bains; Figure 7 Items 708 and 710) under which a subset of the plurality of DQ lines for the first device memory channel operate as a first half-width DQ data bus (Bains; Figure 4, Paragraphs [0047] – [0049]) and the first memory channel is enabled to access all the plurality of memory banks in the DRAM device (Bains; Paragraph [0050]).
Bains does not explicitly teach wherein each memory bank includes a plurality of memory cells arranged in rows and columns.
However, Riho teaches a memory system in which a DRAM device includes memory banks including a plurality of memory cells arranged in rows and columns (Riho; Col 6 Lines 52 – 55).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Bains to include the cell, row, and column arrangement because doing so is a well-known and commonly used arrangement in DRAM memory devices (Riho; Col 6 Lines 52 – 55).
As per claim 17, Bains in combination with Riho also teaches wherein the plurality of DRAM devices comprises a plurality of DRAM dies (Bains; Paragraph [0017]) (Riho; Col 3 Lines 47 – 52) that are stacked above, below, or both above and below a compute die (Riho; Col 17 Lines 14 – 30) including the memory controller (Riho; Col 3 Lines 36 – 46), wherein the DRAM dies and the compute die are interconnected with through silicon vias (TSVs) (Riho; Col 3 Lines 47 – 50, Col 17 Lines 22 – 26).
As per claim 18, Bains in combination with Riho also teaches wherein the memory controller is integrated in a System on a Chip (SoC) (Bains; Paragraph [0020]) including a processor (Bains; Figure 1 Item 110, Paragraph [0020]) and the plurality of DRAM devices comprise DRAM chips (Bains; Paragraph [0017]), further comprising a board to which the SoC and the plurality of DRAM chips are mounted, the board including wiring coupling the DRAM chips to the first and second memory channel interfaces for the memory controller (Bains; Paragraphs [0064] – [0070]).
As per claim 19, Bains in combination with Riho also teaches wherein the memory controller is integrated in a System on a Chip (SoC) (Bains; Paragraph [0020]) including a processor (Bains; Figure 1 Item 110, Paragraph [0020]) and the plurality of DRAM devices comprise DRAM chips (Bains; Paragraph [0017]) that are mounted to a memory module (Bains; Paragraph [0017]) having I/O circuitry comprising first Bains; Figure 3 “DQ_A NIBBLE 0,” “C/A_A,” and “DQ_A NIBBLE 1,” Figure 4 “DQ_A BYTE 0,” “C/A_A,” and “DQ_A BYTE 1,” Figure 5 “DQ_A BYTE 0,” “C/A_A,” and “DQ_A BYTE 1,” Figure 6 “DQ_A BYTE 0,” “MUX 510-A,” “C/A_A,” and “DQ_A BYTE 1”) and second memory channel interfaces (Bains; Figure 3 “DQ_B NIBBLE 0,” “C/A_B,” and “DQ_B NIBBLE 1,” Figure 4 “DQ_B BYTE 0,” “C/A_B,” and “DQ_B BYTE 1,” Figure 5 “DQ_B BYTE 0,” “C/A_B,” and “DQ_B BYTE 1,” Figure 6 “DQ_B BYTE 0,” “MUX 510-B,” “C/A_B,” and “DQ_B BYTE 1”), configured to interconnect with the I/O circuitry of the first and second memory channels on the memory controller, further comprising a board to which the SoC and the plurality of DRAM chips are mounted, the board including wiring coupling the DRAM chips to the first and second memory channel interfaces for the memory controller (Bains; Paragraphs [0064] – [0070]).
Claim(s) 2, 3, 11, 12, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. 2016/0092383 (hereinafter Bains) in view of US Patent No. 8,243,486 (hereinafter Riho), and further in view of US Patent No. 11,894,099 (hereinafter Kim).
As per claims 2, 11, and 20, Bains in combination with Riho teaches the invention as described per claims 1, 9, and 16 (see rejections of claims 1,9, and 16 above). Bains also teaches wherein the DRAM device is a Low-Power Double Data Rate Synchronous DRAM (SDRAM) device (Bains; Paragraph [0019]).
Bains in combination with Riho does not teach wherein the DRAM device is a Low-Power Double Data Rate sixth generation (LPDDR6) Synchronous DRAM (SDRAM) device.
However, Kim teaches a memory system in which a low-power double data rate (LPDDR) SDRAM can be a LPDDR6 SDRAM device (Kim; Col 9 Lines 19 – 36).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Bains in combination with Riho to include the LPDDR6 SDRAM device because doing so allows for taking advantage of a well-known LPDDR standard (Kim; Col 9 Lines 19 – 36).
As per claim 3, Bains in combination with Riho and Kim teaches the invention as described per claim 2 (see rejection of claim 2 above). Bains teaches implementing the DRAM device as a LPDDR SDRAM device having a variety of data line quantity options (x4, x8, x16, and x32) (Bains; Paragraphs [0017] – [0019] and [0022]). Kim also teaches implementing the LPDDR SDRAM as a LPDDR6 SDRAM memory device (Kim; Col 9 Lines 19 – 36).
Bains in combination with Riho and Kim does not explicitly teach wherein the DRAM device is a x24 LPDDR6 SDRAM device having 24 DQ lines.
However, the Examiner submits that implementing the DRAM device as a x24 LPDDR6 SDRAM device having 24 DQ lines would be obvious to try. Bains teaches implementing the DRAM device as a LPDDR SDRAM device having a variety of data line quantity options (x4, x8, x16, and x32) (Bains; Paragraphs [0017] – [0019] and [0022]). While not explicitly describing an x24 device with 24 DQ lines, it would be obvious to try different data line quantities in order to fine tune system performance, cost, size, and complexity. A finite number of possible data line quantities would be reasonable before the cost, size, or complexity of the system became undesirable.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Bains in combination with Riho and Kim to include the x24 LPDDR6 SDRAM because doing so would have been obvious to try in order to balance and tune system performance, cost, size, and complexity.
As per claim 12, Bains in combination with Riho teaches the invention as described per claim 10 (see rejection of claim 10 above). Bains also teaches wherein the DRAM device is a Low-Power Double Data Rate Synchronous DRAM (SDRAM) device (Bains; Paragraph [0019]).
Bains in combination with Riho does not teach wherein each of the plurality of DRAM devices comprises an x24 LPDDR6 SDRAM device having 24 DQ lines.
However, Kim teaches a memory system in which a low-power double data rate (LPDDR) SDRAM can be a LPDDR6 SDRAM device (Kim; Col 9 Lines 19 – 36).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Bains in combination with Riho to include the LPDDR6 SDRAM device because doing so allows for taking advantage of a well-known LPDDR standard (Kim; Col 9 Lines 19 – 36).
Bains in combination with Riho and Kim does not explicitly teach wherein each of the plurality of DRAM devices is a x24 LPDDR6 SDRAM device having 24 DQ lines.
However, the Examiner submits that implementing the DRAM device as a x24 LPDDR6 SDRAM device having 24 DQ lines would be obvious to try. Bains teaches implementing the DRAM device as a LPDDR SDRAM device having a variety of data line quantity options (x4, x8, x16, and x32) (Bains; Paragraphs [0017] – [0019] and [0022]). While not explicitly describing an x24 device with 24 DQ lines, it would be obvious to try different data line quantities in order to fine tune system performance, cost, size, and complexity. A finite number of possible data line quantities would be reasonable before the cost, size, or complexity of the system became undesirable.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Bains in combination with Riho and Kim to include the x24 LPDDR6 SDRAM because doing so would have been obvious to try in order to balance and tune system performance, cost, size, and complexity.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD B FRANKLIN whose telephone number is (571)272-0669. The examiner can normally be reached M-F 8:30am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/RICHARD B FRANKLIN/ Examiner, Art Unit 2181
/IDRISS N ALROBAYE/ Supervisory Patent Examiner, Art Unit 2181