DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show angle β2-2 at first transition 1115 in FIG. 1 as described in the specification at paragraph [53]. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. See MPEP § 608.02(d).
The drawings are further objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character not mentioned in the description: β1 in FIG. 1.
The drawings are further objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference signs mentioned in the description: base layer 121 mentioned in paragraph [44] of the specification (it is believed that this should be amended to read base layer 112); sidewall 1112 mentioned in paragraph [44] of the specification (it is believed that this should be amended to read sidewall 1121); top layer 11 mentioned in paragraph [52] of the specification (it is believed that this should be amended to read top layer 111).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following minor typographical informalities:
At paragraph [30], “Several single chip power semiconductor device” should read “Several single chip power semiconductor devices”;
At paragraph [30], “a (higher) power transmission facilities” should read “a (higher) power transmission facility”;
At paragraph [0039], “Other arrangement may be provided” should read “Other arrangements may be provided”;
At paragraph [56], “artefacts” may be amended to read “artifacts”, although the current British spelling is acceptable if preferred by the applicant;
At paragraph [75], “power semiconductor switches applications” should read “power semiconductor switch applications”.
Appropriate correction is required.
Claim Interpretation
The claims of the present application refer, at various instances, to “an angle” with respect to “a plane”. Using the broadest reasonable interpretation consistent with the specification (see Phillips v. AWH Corp., 415 F.3d 1303, 1316 (Fed. Cir. 2005); MPEP 2111), the “plane” is herein interpreted as any arbitrary plane, and the “angle” is herein interpreted either as being either the acute angle (A in the annotation below) or the supplementary obtuse angle (B in the annotation below).
[AltContent: connector][AltContent: connector][AltContent: textbox (A)][AltContent: textbox (B[img-media_image1.png])][AltContent: textbox (Plane)]
Claim Rejections - 35 USC § 102
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 2, 4 – 8, 10 – 13, 15 – 16, 19, and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ushijima, Takashi, US 2017/0062340 A1 (hereinafter “Ushijima”). FIG. 10 of Ushijima is reproduced below for reference.
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Regarding claim 1, Ushijima discloses a power semiconductor device (see FIGS 1 – 3, paras. [0030] – [0031], semiconductor device 10 including power semiconductor element 22), comprising:
a semiconductor body (see FIGS. 2 – 3, paras. [0031] – [0032], semiconductor element 22 of semiconductor device 10); and
a first terminal coupled to the semiconductor body (see FIGS. 2 – 3 and 10, paras. [0037] – [0043], combined first and second electrode layers 14, 18),
wherein the first terminal has a first side adjoining an encapsulation (see FIGS. 18 – 19, paras. [0060] – 0062], resin mold 102, to which second electrode layer 18 adjoins) and a second side adjoining the semiconductor body (see id., the semiconductor body (10, 22) adjoins first electrode layer 14),
the first terminal comprising: at the first side, a top layer (see FIG. 10, second electrode layer 18); and
at the second side, a base layer coupled to the top layer (see id., first electrode layer 14),
wherein at least one of a sidewall of the top layer or a sidewall of the base layer is arranged in an angle smaller than 85° with respect to a plane (see FIG. 10, para. [0040], angle θ being 35 to 40 degrees relative to the horizontal plane).
Regarding claim 2, Ushijima discloses the power semiconductor device of claim 1 as above, and further discloses wherein at least one of the sidewall of the top layer (18) or the sidewall of the base layer (14) continuously extends at said angle smaller than 85 (see FIG. 10, para. [0040], angle θ being 35 to 40 degrees).
Regarding claim 4, Ushijima discloses the power semiconductor device of claim 1 as above, and further discloses wherein at least one of the top layer (18) sidewall or the base layer (14) sidewall extends substantially linearly (see FIG. 10, para. [0040], angle θ being 35 to 40 degrees).
Regarding claim 5, Ushijima discloses the power semiconductor device of claim 1 as above, and further discloses wherein the encapsulation (102) is coupled to at least one of the top layer sidewall or the base layer sidewall (see FIGS. 18 – 19, and note applicant’s definition of “coupled to” at paragraph [27] of the specification pertaining to mechanical coupling via intermediate elements(s)).
Regarding claim 6, Ushijima discloses the power semiconductor device of claim 1 as above, and further discloses wherein the top layer (18) and the base layer comprise (14) a metal (see paras. [0038] and [0041]).
Regarding claim 7, Ushijima discloses the power semiconductor device of claim 1 as above, and further discloses wherein the semiconductor body comprises a semiconductor material (see para. [0031], disclosing as examples Si or SiC).
Regarding claim 8, Ushijima discloses the power semiconductor device of claim 1 as above, wherein at least one of a first transition, between the top layer (18) sidewall and a surface portion of the base layer (14), occurs at an angle greater than 95° with respect to the plane (see FIG. 10 and paras. [0045] and [0050], approximately at boundary “T”, the supplementary angle to θ would be 125 to 130 degrees at the upper surface of the groove portion 50 of layer 14); or a second transition, between the base layer sidewall and a surface portion of a further layer below the base layer, occurs at an angle greater than 95° with respect to the plane (this alternative limitation need not be addressed herein).
Regarding claim 10, Ushijima discloses the power semiconductor device of claim 8 as above, wherein at least one of the top layer sidewall has an upper portion and a lower portion, the lower portion of the top layer (18) sidewall forming said first transition (see FIG. 10; the upper portion is interpreted as any arbitrary portion (such as the upper half) of the second electrode layer 18); or the base layer sidewall has an upper portion and a lower portion, the lower portion of the base layer sidewall forming said second transition (this alternative limitation need not be addressed herein).
Regarding claim 11, Ushijima discloses the power semiconductor device of claim as above. The power semiconductor device of claim 10, wherein at least one of the upper portion of the top layer sidewall is arranged in a first angle with respect to the plane, and the lower portion of the top layer sidewall is arranged in a second angle with respect to the plane, wherein the second angle is greater than the first angle (see FIG. 10 and para. [0040]; referring again to angle θ as the first angle (35 – 40 degrees) and it supplementary angle as the second angle (125 – 130 degrees)); or the upper portion of the base layer sidewall is arranged in a third angle with respect to the plane, and the lower portion of the base layer sidewall is arranged in a fourth angle with respect to the plane, wherein the fourth angle is greater than the third angle (this alternative limitation need not be addressed herein).
Regarding claim 12, Ushijima discloses a power semiconductor device (see FIGS 1 – 3, paras. [0030] – [0031], semiconductor device 10 including power semiconductor element 22), comprising:
a semiconductor body (see FIGS. 2 – 3, paras. [0031] – [0032], semiconductor element 22 of semiconductor device 10); and
a first terminal coupled to the semiconductor body (see FIGS. 2 – 3 and 10, paras. [0037] – [0043], combined first and second electrode layers 14, 18),
wherein the first terminal has a first side adjoining an encapsulation (see FIGS. 18 – 19, paras. [0060] – 0062], resin mold 102, to which second electrode layer 18 adjoins) and a second side adjoining the semiconductor body (see id., the semiconductor body (10, 22) adjoins first electrode layer 14), the first terminal comprising:
a layer stack of at least two layers (see FIG. 10, first and second electrode layers 14, 18),
wherein a transition between a sidewall of an upper layer of the at least two layers and a surface portion of a lower layer of the at least two layers occurs at an angle greater than 95° with respect to a plane (see FIG. 10 and paras. [0045] and [0050], approximately at boundary “T”, the supplementary angle to θ would be 125 to 130 degrees at the upper surface of the groove portion 50 of layer 14).
Regarding claim 13, Ushijima discloses the power semiconductor device of claim 12 as above, and further discloses wherein the transition is formed by a portion of the upper layer (18) (see FIG. 10, approximately at boundary “T”).
Regarding claim 15, Ushijima discloses the power semiconductor device of claim 12 as above, wherein each layer of the at least two layers (14, 18) comprises a metal (see paras. [0038] and [0041]).
Regarding claim 16, Ushijima discloses a method of producing a power semiconductor device (see FIGS 1 – 3, paras. [0030] – [0031], semiconductor device 10 including power semiconductor element 22; see also FIG. 10 and para. [0055], referring to “a process of manufacturing a semiconductor device 10), comprising:
forming a semiconductor body (see FIGS. 2 – 3, paras. [0031] – [0032], semiconductor element 22 of semiconductor device 10); and
forming a first terminal over the semiconductor body (see FIGS. 2 – 3 and 10, paras. [0037] – [0043], combined first and second electrode layers 14, 18),
wherein the first terminal has a first side for adjoining an encapsulation (see FIGS. 18 – 19, paras. [0060] – 0062], resin mold 102, to which second electrode layer 18 adjoins) and a second side adjoining the semiconductor body (see id., the semiconductor body (10, 22) adjoins first electrode layer 14), the first terminal comprising:
at the first side, a top layer (see FIG. 10, second electrode layer 18); and
at the second side, a base layer coupled to the top layer (see id., first electrode layer 14),
wherein at least one of a sidewall of the top layer or a sidewall of the base layer is arranged in an angle smaller than 85° with respect to a plane (see FIG. 10, para. [0040], angle θ being 35 to 40 degrees relative to the horizontal plane).
Regarding claim 19, Ushijima discloses a method of producing a power semiconductor device (see FIGS 1 – 3, paras. [0030] – [0031], semiconductor device 10 including power semiconductor element 22; see also FIG. 10 and para. [0055], referring to “a process of manufacturing a semiconductor device 10), comprising:
forming a semiconductor body (see FIGS. 2 – 3, paras. [0031] – [0032], semiconductor element 22 of semiconductor device 10); and
forming a first terminal over the semiconductor body (see FIGS. 2 – 3 and 10, paras. [0037] – [0043], combined first and second electrode layers 14, 18),
wherein the first terminal has a first side for adjoining an encapsulation (see FIGS. 18 – 19, paras. [0060] – 0062], resin mold 102, to which second electrode layer 18 adjoins) and a second side adjoining the semiconductor body (see id., the semiconductor body (10, 22) adjoins first electrode layer 14), the first terminal comprising:
a layer stack of at least two layers (see FIG. 10, first and second electrode layers 14, 18),
wherein a transition between a sidewall of an upper layer of the at least two layers and a surface portion of a lower layer of the at least two layers occurs at an angle greater than 95° with respect to a plane (see FIG. 10 and paras. [0045] and [0050], approximately at boundary “T”, the supplementary angle to θ would be 125 to 130 degrees at the upper surface of the groove portion 50 of layer 14).
Regarding claim 22, Ushijima discloses the method of claim 19 as above, and further discloses comprising depositing a metal to form the upper layer (18) (see para. [0041] and [0055]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3, 9, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Ushijima.
Regarding claim 3, Ushijima discloses the power semiconductor device of claim 1 as above, but does not explicitly disclose wherein at least one of the top layer sidewall or the base layer sidewall has a total extension of at least 2 micrometers (µm).
Where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (i.e., prima facie obvious). (See Gardner v. TEC Syst., Inc., 725 F.2d 1338 (Fed. Cir. 1984); MPEP 2144.04(IV)(A).) Upon review of applicant’s specification, paragraph [47] lists the claimed dimensions simply as an embodiment, with no special relevance as to performance disclosed. Accordingly, there is nothing of record to suggest that the claimed dimensions would cause the power semiconductor device to perform differently than a prior art device, such as disclosed in Ushijima. Accordingly, the relative dimensions recited in claim 3 would have been prima facie obvious to a person having ordinary skill in the art before the effective filing date of the present application.
Regarding claim 9, Ushijima discloses the power semiconductor device of claim 8 as above, but does not explicitly disclose wherein at least one of the first transition or the second transition has a vertical extension of at least 400 nanometers (nm) and a lateral extension of at least 250 nm.
As noted above, where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (i.e., prima facie obvious). (See Gardner v. TEC Syst., Inc., supra; MPEP 2144.04(IV)(A).) Upon review of applicant’s specification, paragraph [54] lists the claimed dimensions simply as an example, with no special relevance as to performance disclosed. Accordingly, there is nothing of record to suggest that the claimed dimensions would cause the power semiconductor device to perform differently than a prior art device, such as disclosed in Ushijima. Accordingly, the relative dimensions recited in claim 9 would have been prima facie obvious to a person having ordinary skill in the art before the effective filing date of the present application.
Regarding claim 14, Ushijima discloses the power semiconductor device of claim 12 as above, but does not explicitly disclose wherein the transition has a vertical extension of at least 400 nanometers (nm) and a lateral extension of at least 250 nm.
Again, as noted above, where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (i.e., prima facie obvious). (See Gardner v. TEC Syst., Inc., supra; MPEP 2144.04(IV)(A).) Upon review of applicant’s specification, paragraph [54] lists the claimed dimensions simply as an example, with no special relevance as to performance disclosed. Accordingly, there is nothing of record to suggest that the claimed dimensions would cause the power semiconductor device to perform differently than a prior art device, such as disclosed in Ushijima. Accordingly, the relative dimensions recited in claim 14 would have been prima facie obvious to a person having ordinary skill in the art before the effective filing date of the present application.
Claims 17 – 18, and 20 – 21, respectively, are rejected under 35 U.S.C. 103 as being unpatentable over Ushijima as applied to claims 16 and 19, respectively, above, and further in view of Gatterbauer, Johann, et al., US 2020/0111754 A1 (hereinafter “Gatterbauer”).
Regarding claim 17, Ushijima discloses the method of claim 16 as above, and further discloses, comprising forming the top layer (see FIG. 10 and para. [0055], second electrode layer 18). Ushijima does not explicitly disclose, however, wherein forming the top layer comprises: providing a resist layer; and processing the resist layer comprising forming at least one opening, in the resist layer, defined by a resist layer sidewall arranged in an angle greater than 95° with respect to the plane.
In a related art, Gatterbauer discloses a process in the fabrication of power semiconductor devices for selective metal etching using a photoresist (see paras. [0034] – [0036]). It is prima facie obvious to combining prior art elements according to known methods to yield predictable results. (See KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 415 – 21 (2007); MPEP 2143(I)(A).) Given that, as disclosed in Gatterbauer, photoresist masking and etching to form a feature of a particular shape, is well known in the art, it would therefore have been prima facie obvious to a person having ordinary skill in the art before the effective filing date of the present application to use photoresist masking/etching, as in Gatterbauer, to achieve the desired greater than 95 degree angle of the sidewall of the top layer (see also Ushijima, FIG. 10 and paras. [0045] and [0050], approximately at boundary “T”, the supplementary angle to θ would be 125 to 130 degrees at the upper surface of the groove portion 50 of layer 14).
Regarding claim 18, Ushijima in view of Gatterbauer is relied on for the method of claim 17 as above, and with respect to the limitation of wherein processing the resist layer comprises: controlling a focal plane during an exposure of the resist layer to form the resist layer sidewall at said angle greater than 95° with respect to the plane, it is noted that, as Gatterbauer exemplifies, it is prima facie obvious to apply a known technique (such as photoresist exposure) to a known device (metal layer) in a predictable way. (See KSR v. Teleflex, supra; MPEP 2143(I)(C) – (D).) Accordingly, controlling a well-known process as demonstrated in Gatterbauer to achieve a particular design shape as taught in Ushijima would have been prima facie obvious to a person having ordinary skill in the art before the effective filing date of the present application.
Regarding claim 20, Ushijima discloses the method of claim 19 as above, and further discloses forming the transition (see FIG. 10 and para. [0045], approximately at boundary “T”). Ushijima, however, does not explicitly disclose wherein forming the transition comprises: providing a resist layer; and subjecting the resist layer to a pre-treatment processing act.
It is prima facie obvious to combining prior art elements according to known methods to yield predictable results. (See KSR v. Teleflex, supra; MPEP 2143(I)(A).) Given that, as disclosed in Gatterbauer (see paras. [0034] – [0036]), photoresist masking and etching (wherein etching is interpreted herein as the pre-treatment processing act) to form a feature of a particular shape (i.e., the transition), is well known in the art, it would therefore have been prima facie obvious to a person having ordinary skill in the art before the effective filing date of the present application to use photoresist masking/etching, as in Gatterbauer, to achieve the desired transition (see also Ushijima, FIG. 10 and paras. [0045] and [0050], approximately at boundary “T”).
Regarding claim 21, Ushijima in view of Gatterbauer is relied on for the method of claim 20 as above, and this combination of references further discloses wherein the pre-treatment processing act comprises at least one of a wet etch processing act or a dry etch processing act (see paras. [0034] – [0036] of Gatterbauer and rejection of claim 20, supra).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
Matsushita, Kenichi, et al., US 2022/0085154 A1, disclosing a semiconductor part, a terminal insulating film, a first protective film, a second electrode, a terminal electrode, a first insulating film, and a second protective film, in an IGBT useful as a power semiconductor (see, e.g., FIG. 6); and
Chowdhury, Srabanti, et al., US 2014/0231823 A1, disclosing an electrode in a recess, the electrode including an extending portion over the first sidewall; a portion of the electrode-defining layer is between the extending portion and the III-N material structure, wherein the first sidewall forms a first effective angle relative to the surface of the III-N material structure and the second sidewall forms a second effective angle relative to the surface of the III-N material structure, the second effective angle being larger than the first effective angle (see, e.g., FIG. 18); and
Stecher, Matthias, DE 10 2004 061308 A1, disclosing a semiconductor component that has passivation layer, which covers a metal area below it and has a “tear capture” structure, wherein the tear capture structure prevents the reproduction of the tear in the passivation layer above the metal area towards the metal area, which is adjacent to the isolation area (see, e.g., FIG. 7).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ryan Fortin whose telephone number is 703-756-5649. The examiner can normally be reached on Monday – Friday from 8:30 AM to 12:30 PM and from 2:30 PM to 6:30 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo, can be reached at telephone number 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.T.F./
Examiner, Art Unit 2897
/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897