DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-14, 17, and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2021/0218376) and Manku (US 2008/0007334), and further in view of Chang et al. (US 2023/0123305).
Referring to Claim 2, Park teaches an electronic device comprising:
an antenna (see antenna connected to 110 in fig. 1); and
an amplifier communicatively coupled to the antenna (see paragraph 38 which shows an amplifier part of communication unit which is connected to antenna in fig. 1), the amplifier comprising a first amplification circuitry (see amplifier 210 in fig. 2) comprising
a first transistor configured to amplify a signal (see transistor 312-1 and amplifier 310 in fig. 3), and
a second transistor (see transistor 312-2 in fig. 3).
Park does not teach the second transistor configured to neutralize a first parasitic capacitance associated with the first transistor via a first neutralization capacitance, and a first resistive element coupled to a first source of the second transistor. Manku teaches the second transistor configured to neutralize a first parasitic capacitance associated with the first transistor via a first neutralization capacitance (see paragraph 28 of the applicant’s specification which shows parasitic capacitance neutralized by connecting gates of transistors together and transistors 46 and 42 of fig. 8 of Manku have coupled gates), and a first resistive element coupled to a first source of the second transistor (see sources of transistors 46 and 48 coupled to resistor 50 in fig. 8 further noting that the device 120 of fig. 8 is an amplifier). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Manku to the device of Park in order to improve the amplifying characteristics and overall performance of the device.
The combination of Park and Manku does not teach a first switch configured to couple the first amplification circuit to the antenna to vary a gain of the amplifier. Chang teaches a first switch configured to couple the first amplification circuit to the antenna to vary a gain of the amplifier (see switch N2 in fig. 3 connected to antenna 301 further noting that the switch N2 is also connected to the source of transistors N1 and N3 and the source of N2 is connected to ground, a formation similar to what is shown in the switch 140 of fig. 7 of the applicant’s invention). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Chang to the modified device of Park and Manku in order to better conserve power by regulating the gain.
Referring to Claim 11, Park teaches amplification circuit comprising:
a first amplification transistor configured to amplify a signal (see transistors 312-1 in amplifier 310 in fig. 3).
Park does not teach a first neutralization transistor coupled to the first amplification transistor and configured to neutralize a parasitic capacitance associated with the first amplification transistor; and
a first resistive element coupled to a first source of the first neutralization transistor and a ground, the first resistive element configured to block at least a portion of current flowing from the first source to the ground.
Manku teaches a first neutralization transistor coupled to the first amplification transistor and configured to neutralize a parasitic capacitance associated with the first amplification transistor (see paragraph 28 of the applicant’s specification which shows parasitic capacitance neutralized by connecting gates of transistors together and transistors 46 and 42 of fig. 8 of Manku have coupled gates); and
a first resistive element coupled to a first source of the first neutralization transistor and a ground, the first resistive element configured to block at least a portion of current flowing from the first source to the ground (see sources of transistors 46 and 48 coupled to resistor 50 in fig. 8 which is also coupled to ground further noting that the device 120 of fig. 8 is an amplifier). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Manku to the device of Park in order to improve the amplifying characteristics and overall performance of the device.
The combination of Park and Manku does not teach a first switch configured to activate the amplification circuitry to vary a gain of the amplifier. Chang teaches a first switch configured to couple the first amplification circuit to the antenna to vary a gain of the amplifier (see switch N2 in fig. 3 connected to antenna 301 further noting that the switch N2 is also connected to the source of transistors N1 and N3 and the source of N2 is connected to ground, a formation similar to what is shown in the switch 140 of fig. 7 of the applicant’s invention). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Chang to the modified device of Park and Manku in order to better conserve power by regulating the gain.
Referring to Claim 17, Park teaches a transceiver (see transceiver 110 in fig. 1), comprising:
a plurality of amplification circuits (see amplifiers 210 and 220 in fig. 2), each amplification circuit of the plurality of amplification circuits comprising
a first transistor configured to amplify a signal (see transistor 312-1 and amplifier 310 in fig. 3), and
a second transistor (see transistor 312-2 in fig. 3).
Park does not teach the second transistor configured to neutralize a first parasitic capacitance associated with the first transistor, and a first resistive element coupled to a source of the second transistor and a ground, the first resistive element configured to block at least a portion of current flowing from the source of the second transistor. Manku teaches the second transistor configured to neutralize a first parasitic capacitance associated with the first transistor (see paragraph 28 of the applicant’s specification which shows parasitic capacitance neutralized by connecting gates of transistors together and transistors 46 and 42 of fig. 8 of Manku have coupled gates), and a first resistive element coupled to a source of the second transistor and a ground, the first resistive element configured to block at least a portion of current flowing from the source of the second transistor (see sources of transistors 46 and 48 coupled to resistor 50 in fig. 8 where the resistor is coupled to ground and further noting that the device 120 of fig. 8 is an amplifier). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Manku to the device of Park in order to improve the amplifying characteristics and overall performance of the device.
The combination of Park and Manku does not teach a first switch configured to activate the amplification circuitry to vary a gain of the plurality of amplification circuits. Chang teaches a first switch configured to couple the first amplification circuit to the antenna to vary a gain of the plurality of amplification circuits (see switch N2 in fig. 3 connected to antenna 301 further noting that the switch N2 is also connected to the source of transistors N1 and N3 and the source of N2 is connected to ground, a formation similar to what is shown in the switch 140 of fig. 7 of the applicant’s invention). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Chang to the modified device of Park and Manku in order to better conserve power by regulating the gain.
Referring to Claim 3, Manku also teaches a third transistor configured to amplify the signal (see transistor 44 in fig. 8), and a fourth transistor configured to neutralize a second parasitic capacitance associated with the third transistor via a second neutralization capacitance (see paragraph 28 of the applicant’s specification which shows parasitic capacitance neutralized by connecting gates of transistors together and transistors 48 and 44 of fig. 8 of Manku have coupled gates), wherein the fourth transistor comprises a second source coupled to a third source of the third transistor (see transistors 44 and 48 having coupled sources in fig. 8).
Referring to Claim 4, Manku also teaches the second transistor comprising a first gate coupled to a second gate of the first transistor (see 42 and 46 having coupled gates in fig. 8), and
a first drain coupled to a second drain of the third transistor (see drain of transistor 48 in fig. 8 coupled to drain of transistor 42).
Referring to Claim 5, Manku also teaches the fourth transistor comprising a first gate coupled to a second gate of the second transistor (see 44 and 48 having coupled gates in fig. 8), and a first drain coupled to a second drain of the first transistor (see drain of transistor 46 in fig. 8 coupled to drain of transistor 44).
Referring to Claim 6, Manku also teaches the first resistive element coupled to ground (see resistor 50 in fig. 8 coupled to ground).
Referring to Claim 7, Manku also teaches the first resistive element configured to block current flow from the first source of the second transistor and a second source of a third transistor to the ground (see resistor 50 between sources of transistors 46 and 48 and ground in fig. 8), wherein the third transistor is configured to neutralize a second parasitic capacitance (see paragraph 28 of the applicant’s specification which shows parasitic capacitance neutralized by connecting gates of transistors together and transistors 46 and 42 of fig. 8 of Manku have coupled gates).
Referring to Claim 8, Manku also teaches the first resistive element coupled to a source of the first transistor (see resistor 50 between sources of transistors 42 and 44 and ground in fig. 8).
Referring to Claim 9, Manku also teaches the second source of the first transistor coupled to the first switch, and the first switch is configured to enable the first amplification circuitry to amplify the signal (see paragraph 25 which shows a control circuit coupled to the resistor and therefore, coupled to the sources of the first and second transistors where the control circuit is described to include switches).
Referring to Claim 10, Manku also teaches the first switch comprising a metal oxide semiconductor field-effect transistor (MOSFET) (see paragraph 25 which shows MOSFETs).
Referring to Claim 12, Manku also teaches wherein the amplification circuitry comprises a second amplification transistor and a second neutralization transistor coupled to the second amplification transistor (see transistors 44 and 48 in fig. 3), the amplification circuitry being configured to cancel a first voltage swing received at the first source of the first amplification transistor, a second source of the first neutralization transistor, or both, via a second voltage swing received at a third source of the second amplification transistor, a fourth source of the second neutralization transistor, or both (see paragraph 30 of the applicant’s specification which shows the cancelling of voltage swing due to sources of transistors meeting at a common node and coupled to a resistor and the sources of transistors 46 and 48 are met at a common node and coupled to resistor 50).
Referring to Claim 13, Manku also teaches the first neutralization transistor comprises a first gate coupled to a second gate of the first amplification transistor (see 42 and 46 having coupled gates in fig. 8), and a first drain coupled to a second drain of the second amplification transistor (see drain of transistor 48 in fig. 8 coupled to drain of transistor 42).
Referring to Claim 14, Manku also teaches the second neutralization transistor comprising a third gate coupled to a fourth gate of the second amplification transistor (see 44 and 48 having coupled gates in fig. 8), and a third drain coupled to a fourth drain of the first amplification transistor (see drain of transistor 46 in fig. 8 coupled to drain of transistor 44).
Referring to Claim 23, Park teaches second amplification circuitry (see amplifier 220 in fig. 2) comprising
a third transistor configured to amplify the signal (see transistor 322-1 and amplifier 320 in fig. 3), and
a fourth transistor (see transistor 322-2 in fig. 3).
Manku teaches the fourth transistor configured to neutralize a second parasitic capacitance associated with the third transistor via a second neutralization capacitance (see paragraph 28 of the applicant’s specification which shows parasitic capacitance neutralized by connecting gates of transistors together and transistors 46 and 42 of fig. 8 of Manku have coupled gates), and a second resistive element coupled to a second source of the fourth transistor (see sources of transistors 46 and 48 coupled to resistor 50 in fig. 8 further noting that the device 120 of fig. 8 is an amplifier). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Manku to the device of Park in order to improve the amplifying characteristics and overall performance of the device.
Chang teaches a second switch configured to couple the second amplification circuitry to the antenna to vary the gain of the amplifier (see switch N2 in fig. 3 connected to antenna 301 further noting that the switch N2 is also connected to the source of transistors N1 and N3 and the source of N2 is connected to ground, a formation similar to what is shown in the switch 140 of fig. 7 of the applicant’s invention). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Chang to the modified device of Park and Manku in order to better conserve power by regulating the gain.
Claim(s) 15-16 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park, Manku, and Chang, and further in view of Jin (US 2017/0346449).
Referring to Claim 15, the combination of Park, Manku, and Chang does not teach wherein a first parasitic capacitance associated with the first amplification transistor is exhibited between the second gate of the first amplification transistor and the fourth drain of the first amplification transistor, and a second parasitic capacitance associated with the first neutralization transistor is exhibited between the first gate of the first neutralization transistor and the first drain of the first neutralization transistor. Jin teaches wherein a first parasitic capacitance associated with the first amplification transistor is exhibited between the second gate of the first amplification transistor and the fourth drain of the first amplification transistor, and a second parasitic capacitance associated with the first neutralization transistor is exhibited between the first gate of the first neutralization transistor and the first drain of the first neutralization transistor (see fig. 1B which shows Cgd between the drain and gate of transistor M1, Cds between the drain and source, and Cgs between the gate and source and paragraph 48 which shows all capacitors with parasitic capacitance). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Jin to the modified device of Park, Manku, and Chang in order to reduce noise and distortion output from the device.
Referring to Claim 16, Jin also teaches wherein a first parasitic capacitance of the second amplification transistor is exhibited between the first gate of the first amplification transistor and the second drain of the second amplification transistor, and a second parasitic capacitance associated with the second neutralization transistor is exhibited between third gate of the second neutralization transistor and the third drain of the second neutralization transistor (see fig. 1B which shows Cgd between the drain and gate of transistor M1, Cds between the drain and source, and Cgs between the gate and source and paragraph 48 which shows all capacitors with parasitic capacitance). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Jin to the modified device of Park, Manku, and Chang in order to reduce noise and distortion output from the device.
Referring to Claim 18, Jin also teaches wherein, in operation, the second transistor exhibits a second parasitic capacitance between a gate of the second transistor and a drain of the second transistor, a third parasitic capacitance between the gate of the second transistor and the source of the second transistor, and a fourth parasitic capacitance between the drain of the second transistor and the source of the second transistor (see fig. 1B which shows Cgd between the drain and gate of transistor M1, Cds between the drain and source, and Cgs between the gate and source and paragraph 48 which shows all capacitors with parasitic capacitance). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Jin to the modified device of Park, Manku, and Chang in order to reduce noise and distortion output from the device.
Claim(s) 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park, Manku, and Chang, and further in view of Beaudin et al. (US 2018/0226932).
Referring to Claim 19, the combination of Park, Manku, and Chang does not teach wherein a first matching network of a plurality of matching networks communicatively coupled to an amplification circuit of the plurality of amplification circuits is configured to absorb the third parasitic capacitance, and a second matching network of the plurality of matching networks communicatively coupled to the amplification circuit is configured to absorb the fourth parasitic capacitance. Beaudin teaches wherein a first matching network of a plurality of matching networks communicatively coupled to an amplification circuit of the plurality of amplification circuits is configured to absorb the third parasitic capacitance, and a second matching network of the plurality of matching networks communicatively coupled to the amplification circuit is configured to absorb the fourth parasitic capacitance (see matching networks 304a-f coupled to amplifiers 308, 310, and 312 as described in paragraph 131 and paragraph 38 which shows the absorption of parasitic capacitances). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the teachings of Beaudin to the modified device of Park, Manku, and Chang in order to increase the efficiency of the amplifiers.
Referring to Claim 20, Manku also teaches each amplification circuit configured to neutralize the first parasitic capacitance associated with the first transistor via the second parasitic capacitance (see paragraph 28 of the applicant’s specification which shows parasitic capacitance neutralized by connecting gates of transistors together and transistors 46 and 42 of fig. 8 of Manku have coupled gates).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-9 and 11-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4-7, 9-11, 13, 14, and 16 of U.S. Patent No. 12,362,779. Although the claims at issue are not identical, they are not patentably distinct from each other because many of the limitations of the pending claims are also in the claims of the patent.
Regarding Claims 2 and 3, both the pending claim and claim 1 of the patent teach an antenna, transceiver, and first and second transistors. Claim 1 of the patent teaches third and fourth transistors, but that is taught in pending claim 3. The resistive element in pending claim 1 is taught in claim 4 of the patent.
Regarding Claim 11, all elements of pending claim 11 are in claim 8 of the patent.
Regarding Claim 17, all elements of pending claim 17 are in claim 13 of the patent.
Claim 4 is taught in claim 8 of the patent.
Claim 5 is taught in claim 8 of the patent.
Claim 6 is taught in claim 4 of the patent.
Claim 7 is taught in claim 5 of the patent.
Claim 8 is taught in claim 6 of the patent.
Claim 9 is taught in claim 7 of the patent.
Claim 12 is taught in claim 14 of the patent.
Claim 13 is taught in claim 13 of the patent.
Claim 14 is taught in claim 13 of the patent.
Claim 15 is taught in claim 9 of the patent.
Claim 16 is taught in claim 16 of the patent.
Claim 18 is taught in claim 9 of the patent.
Claim 19 is taught in claim 10 of the patent.
Claim 20 is taught in claim 11 of the patent.
Response to Arguments
Applicant’s arguments with respect to claim(s) 2-20 and 23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed 11/24/2025 have been fully considered but they are not persuasive. The Double Patenting rejection is maintained because despite the amendment, all of the key similarities between the pending claims and the claim of the patent stated above still exists.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE YUN whose telephone number is (571)272-7860. The examiner can normally be reached 9am-5pm.
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/EUGENE YUN/Primary Examiner, Art Unit 2648