DETAILED ACTION
Contents
I. Notice of Pre-AIA or AIA Status 4
II. Priority 4
III. Pertinent Prosecution History 4
IV. Claim Status 6
V. Reissue Requirements 6
VI. Oath/Declaration 8
VII. Specification Objections 8
VIII. Claim Objections 9
IX. Claim Interpretation 11
A. Lexicographic Definitions 11
B. 35 U.S.C § 112 6th Paragraph 12
(1) Functional Phrase – “Processor”/ “Hardware Processor” 13
(2) Functional Phrase – “Disaggregated Memory Manager” 20
C. 'Sources' for the 'Broadest Reasonable Interpretation' 27
(1) Disaggregated Memory 28
(2) Access Pattern 28
X. Claim Rejections – 35 U.S.C. § 112 29
A. 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph 29
(1) New Matter 29
B. 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph 31
XI. Claim Rejections - 35 USC § 251 34
A. Original Patent Requirement 34
XII. Claim Rejections – 35 U.S.C. §§ 102/103 37
A. Claims 23, 24, 27, 28, 31 and 32 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Wu et al. (U.S. Publication No. 2010/0241673)(“Wu”). 38
B. Claims 1-4, 6, 7, 11, 12, 15-20, 25, 26, 29 and 30 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Wu et al. (U.S. Publication No. 2010/0241673)(“Wu”). 48
C. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (U.S. Publication No. 2010/0241673)(“Wu”) as applied to claims 1-4, 6, 7, 11, 12, 15-20, 25, 26, 29 and 30 above, and further in view of Douglis et al. (U.S. Patent No. 11,093,397)(“Douglis”)…. 70
D. Claims 8-10 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (U.S. Publication No. 2010/0241673)(“Wu”) as applied to claims 1-4, 6, 7, 11, 12, 15-20, 25, 26, 29 and 30 above, and further in view of MO et al. (U.S. Patent No. 11,093,397)(“MO”). 75
E. Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (U.S. Publication No. 2010/0241673)(“Wu”) as applied to claims 1-4, 6, 7, 11, 12, 15-20, 25, 26, 29 and 30 above, and further in view of Kimmel et al. (U.S. Patent No. 9,134,917)(“Kimmel”). 78
XIII. Response to Arguments 79
A. Drawings Objection(s) 79
B. 35 U.S.C. § 112, Second Paragraph, Rejections 80
C. Original Patent Requirement 81
D. 35 U.S.C. § 102/103 Rejections 83
XIV. Conclusion 85
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to pre-AIA 35 U.S.C. 102 and 103 (or as subject to AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Applicant filed the instant reissue application 17/945,982 (“‘982 Reissue Application”) on 15 September 2022 for U.S. Application No. 16/185,833 (“‘833 Application"), filed 09 November 2018, now U.S. Patent No. 10,789,090 (“‘090 Patent”), issued 29 September 2020, which claims foreign priority to Korean Patent Application No. 10-2018-0110719, filed 17 September 2018 (“KPA ‘719”) and Korean Patent Application No. 10-2017-0148511, filed 09 November 2017 (“KPA ‘511”).
Thus, the Examiner concludes that for examination purposes the instant ‘982 Reissue Application has an effective filing data of 09 November 2017, which is the filing date of the KPA ‘511 Application.
Pertinent Prosecution History
As set forth supra, Applicant filed the application for the instant ‘982 Reissue Application on 15 September 2022. The Examiner finds that the instant ‘982 Reissue Application included a preliminary amendment (“Sept 2022 Preliminary Amendment”) to the claims (“Sept 2022 Claim Amendment”). The Sept 2022 Claim Amendment included an amendment: amending original claims 1, 15 and 18, providing original claims 2-4, 6 and 7; canceling of original claims 5, 8-14, 16, 17, 19 and 20; and adding new claims 21 and 22.
The Office issued a non-Final Office action on 07 March 2025 (“March 2025 Non-Final Office Action”).
On 09 June 2025, Applicant filed a Response to Non-Final Office Action (“June 2025 Response”). The June 2025 Response contained: “Remarks,” “Amendments to the Specification” (“June 2025 Spec Amendment”), and “Amendments to the Claims” (“June 2025 Claim Amendment”) including: original1 claims 1-20, new claims 23-32; and canceled new claims 21-22. The June 2025 Response indicated that claims 1, 15 and 18 were being placed back into their original issued form. (June 2025 Applicant Response at 10). In examination of the June 2025 Claim Amendment, while claims 1, 15 and 18 are indicated as “Original,” as required by 37 CFR 1.173(b)(2), the Examiner finds that: (1) claim 15 still has claimed subject matter indicated as omitted by being enclosed in brackets; and (2) claim 18 has claimed subject matter indicated by two (2) beginning brackets without correlating end brackets. (See June 2025 Claim Amendment).
On 01 July 2025, the Office and Applicant had an interview (“July 2025 Interview”) discussing the issue of the “bracketing” of claims 15 and 18 in the June 2025 Claim Amendment (see Interview Summary mailed with the instant Final Office Action (“July 2025 Int. Summary”)). Applicant confirmed that claims 1, 15 and 18 are amended back into their original issued form and the Office indicated that claim 1, 15 and 18 will be examined as such. (See July 2025 Int. Summary).
Claim Status
The Examiner finds that the claim status in the instant ‘982 Reissue Application is as follows:
Claim(s) 1-20 (Original)
Claim(s) 23-32 (New)
Claim(s) 21 and 22 (New and canceled)
Thus, the Examiner concludes that claims 1-20 and 23-32 are pending in the instant ‘982 Reissue Application. Claims 1-20 and 23-32 are examined (“Examined Claims”).
Reissue Requirements
For reissue applications filed before September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the law and rules in effect on September 15, 2012. Where specifically designated, these are “pre-AIA ” provisions.
For reissue applications filed on or after September 16, 2012, all references to 35 U.S.C. 251 and 37 CFR 1.172, 1.175, and 3.73 are to the current provisions.
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceed-ing in which the ‘090 Patent is or was involved. These proceedings would include interferences, reissues, reexaminations, post-grant proceedings and litigation.
Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is mate-rial to patentability of the claims under consideration in this reissue appli-cation.
These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
The Examiner notes that Amendment practice for Reissue Applications is NOT the same as for non-provisional applications. See MPEP §§ 1413 and 1453. Reissue application amendments must comply with 37 CFR 1.173, while non-provisional application amendments must comply with 37 CFR 1.121. Particularly,
Manner of making amendments under 37 CFR 1.173:
All markings (underlining and bracketing) are made relative to the original patent text, 37 CFR 1.173(g) (and not relative to the prior amendment).
For amendments to the abstract, specification and claims, the deleted matter must be enclosed in brackets, and the added matter must be underlined. See 37 CFR 1.173(d).
For amendments to the drawings, any changes to a patent drawing must be submitted as a replacement sheet of drawings which shall be an attachment to the amendment document. Any replacement sheet of drawings must be in compliance with § 1.84 and shall include all of the figures appearing on the original version of the sheet, even if only one figure is amended. Amended figures must be identified as "Amended," and any added figure must be identified as "New." In the event that a figure is canceled, the figure must be surrounded by brackets and identified as "Canceled." All changes to the drawing(s) shall be explained, in detail, beginning on a separate sheet accompanying the papers including the amendment to the drawings. See 37 CFR 1.173(d)(3).
The Examiner further notes that all amendments to the instant ‘982 Reissue Application must comply with 37 CFR 1.173(b)-(g).
Oath/Declaration
As per the MPEP, an error statement provided by Applicant in the “Remarks” section of a response is proper when the original error statement, and in return, the originally filed Oath/Declaration was deemed proper. (See MPEP §§ 1414.03.I and 1444.III.A). The Examiner finds that the June 2025 Response states,
A reissue is sought because the patent owner seeks to broaden at least one claim. “A reissue claim is ‘broadened’ where at least one limitation of the patent claims is either completely eliminated or is only presented in a broader way in the reissue claim relative to the broadest patented claim(s).” MPEP §1412.02. Here, new independent claims 23, 31, and 32 each qualifies as a claim being broadened with respect to original claims 1, 15, and 18 for at least two reasons:
1. the limitation “based on an operation of a virtual machine” is completely eliminated from the step “detecting a memory access pattern in a virtual machine node”, and
2. the limitation that “the memory access pattern” be “variably set based on a time at which the operation of the virtual machine is performed” is completely eliminated.
(June 2025 Response at 11; emphasis added). The Examiner finds that the Office deems the error statement compliant because the limitations of: (1) “based on an operation of a virtual machine;” and (2) “the memory access pattern [being] “variably set based on a time at which the operation of the virtual machine is performed” are not present in the newly provided claims 23, 31 and 32, filed in the June 2025 Claim Amendment.
Specification Objections
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
The Examiner finds that new claim 31 recites:
a hardware processor controlling the memory, wherein
the hardware processor detects a memory access pattern in a virtual machine node, and performs a memory operation by using a memory block in consideration of the memory access pattern.
(June 2025 Claim Amendment at claim 31); and new claim 32 recites
a hardware processor controlling the memory, wherein
the hardware processor detects a memory access pattern in a virtual machine node, and performs a memory operation by using a memory block in consideration of the memory access pattern.
wherein a disaggregated memory manager of the virtual machine node detects, via a hardware processor, a memory access pattern, and performs a memory operation by using a memory block in consideration of the memory access pattern
(Id. at claim 32). The Examiner finds that the ‘090 Patent provides insufficient antecedent basis for the claimed subject matter. (See ‘090 Patent at c.10, ll.20-56; see Figure 9; emphasis on “the processor 920 may be a hardware unit corresponding to each program, each mode, and a manager of FIG. 1 described above”).
Applicant should either amend the claim recitations of a “hardware processor” to be simply: (1) a “processor,” as previously provided; or (2) to the processor comprising a separate hardware unit for each program step, as disclosed.
Claim Objections
Applicant is advised that should claims 3 and 4 be found allowable, claims 25 and 26 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
In addition, MPEP § 1453 states,
pursuant to 37 CFR 1.173(c), each claim amendment must be accompanied by an explanation of the support in the disclosure of the patent for the amendment (i.e., support for all changes made in the claim(s), whether insertions or deletions). The failure to submit an explanation will generally result in a notification to applicant that the amendment before final rejection is not completely responsive (see 37 CFR 1.135(c)).
(MPEP § 1453; emphasis added). The Examiner finds that Applicant has not provided sufficient explanation of support for at least the amendments to claims 31 and 32 instantly provided in the June 2025 Claim Amendment, as set forth in 37 CFR 1.173(c). (Id.) While the June 2025 Response provides direction for the Examiner to find support for the claim amendment, the Examiner finds that the direction is not sufficient. Specifically, while the June 2025 Response cites to sections of the ‘090 Patent which are directed to “processor” and “hardware,” the Examiner finds that the citations do not provide support for the processor for performing the functions to be specifically a stand-alone “hardware processor.” (June 2025 Response at 11).
Moreover, the May 2025 Claim Amendment does not comply with 37 CFR 1.173(b)(2) and is objected to because Applicant has not provided the correct parenthetical expression for the claims. Specifically, instantly provided original claim 13 is indicated as “(Original)” when it should instead, in light of the non-designated amendment thereof, be indicated as “(Original, Amended).” (See 37 CFR 1.173(b); and MPEP §§ 1453.II, V.D-E). (See § X.A.(1), infra, for further explanation)
Furthermore, claims 1, 15 and 31 are objected to because of the following informalities: Claims 1, 15 and 31 recite “a disaggregated memory” twice, in line 1-2. The Examiner finds it unclear to how many “disaggregated memory” element structures there are. The Examiner recommends that Applicant amend the second “a disaggregated memory” to instead read – the disaggregated memory – as is similarly recited in new claim 23.
Appropriate correction is required.
Claim Interpretation
During examination, claims are given the broadest reasonable interpretation consistent with the specification and limitations in the specification are not read into the claims. See MPEP § 2111, MPEP § 2111.01 and In re Yamamoto et al., 222 USPQ 934 (Fed. Cir. 1984). Under a broadest reasonable interpretation, words of the claim must be given their plain meaning, unless such meaning is inconsistent with the specification. See MPEP § 2111.01(I). It is further noted it is improper to import claim limitations from the specification, i.e., a particular embodiment appearing in the written description may not be read into a claim when the claim language is broader than the embodiment. See MPEP § 2111.01(II). Therefore, unless one of the exceptions applies below, Examiners will interpret the limitations of the pending and examined claims using the broadest reasonable interpretation.
Lexicographic Definitions
A first exception to the prohibition of reading limitations from the specification into the claims is when the Applicant for patent has provided a lexicographic definition for the term. (See MPEP § 2111.01(IV)). After careful review of the original specification, the prosecution history, and unless expressly noted otherwise by the Examiner, the Examiner finds that he is unable to locate any lexicographic definitions (either express or implied) with reasonable clarity, deliberateness, and precision. Because the Examiner is unable to locate any lexicographic definitions with reasonable clarity, deliberateness, and precision, the Examiner concludes that Applicant is not his/her own lexicographer. (Id.)
35 U.S.C § 112 6th Paragraph
A second exception to the prohibition of reading limitations from the specification into the claims is when the claimed feature is written as a means-plus-function or a step-plus-function. See 35 U.S.C. § 112(6th ¶) and MPEP §§ 2181-2183. As noted in MPEP § 2181, a three prong test is used to determine the scope of a means-plus-function or step-plus-function limitation in a claim:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as "configured to" or "so that"
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
The Examiner finds herein that claims 15, 18, 31 and 32 include one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. §112 (6th ¶) because the claim limitations uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Each such limitation will be discussed in turn as follows:
Functional Phrase – “Processor”/ “Hardware Processor”
A first means-plus-function phrase is recited in claims 15 and 31 (and included in each of dependent claims 16 and 17) which recites “processor/hardware processor …” or hereinafter “Functional Phrase 1” or “FP1.” The Examiner determines herein that FP1 does meet the three prong test and thus will be interpreted as a means-plus-function limitation under 35 U.S.C. §112(6th ¶).
The Examiner finds that claim 15 expressly recites:
a processor [for] controlling the memory,
wherein the processor detects a memory access pattern in a virtual machine node based on an operation of a virtual machine, and
performs a memory operation by using a memory block in consideration of the memory access pattern,
wherein the memory access pattern is variably set based on a time at which the operation of the virtual machine is performed, and
wherein the memory block dynamically changes in size based on the memory access pattern, including the memory block dynamically increasing in size when the memory operation includes a load operation that loads the memory block from the remote memory to the local memory
[emphasis added]; and claim 31 expressly recites:
a hardware processor [for] controlling the memory,
wherein the hardware processor detects a memory access pattern in a virtual machine node, and
performs a memory operation by using a memory block in consideration of the memory access pattern,
wherein the memory block dynamically changes in size based on the memory access pattern, including the memory block dynamically increasing in size when the memory operation includes a load operation that loads the memory block from the remote memory to the local memory
i. 3-Prong Analysis: Prong (A)
FP1 meets invocation prong (A) because "means ... for" type language is recited. The Examiner first finds that “processor/hardware processor” is a generic placeholder or nonce term equivalent to “means” because the term “processor/hardware processor” conveys some structures, but not any specific structures related to the function.
Additionally, the Examiner has reviewed the prosecution history and the relevant prior art of record herein and find that “processor/hardware processor” as used in the claims does not provide an art-recognized structure to perform the claimed function.
The Examiner finds that a processor is definable as (1) a system or mechanism that accepts a program as input, prepares it for execution, and executes the process so defined with data to produce results, or (2) a computer program that includes the compiling, assembling, translating, and related functions for a specific programming language, for example, Cobol processor, Fortran processor.2 A processor is also definable as the part of a computer system that operates on data.3 Accordingly, the Examiner finds processor/hardware processor can be defined or interpreted as either a system or mechanism that accepts a program and executes the program process with data to acquire a result, or a computer program. Accordingly, the Examiner finds that processor implies little more than a generic processor in association with a special function. Rather more than a simple processor would be required to perform the function recited in FP1.
Accordingly, the Examiner finds nothing in the specification, prosecution history or the prior art to construe “processor/hardware processor …” in FP1 as the name of a sufficiently definite structure for performing the functions recited in FP1 so as to take the overall claim limitation out of the ambit of §112(6th ¶). See Williamson v. Citrix Online, L.L.C., 115 USPQ2d 1105, 1112 (Fed. Cir. 2015).
In light of the above, the Examiner concludes that the term “processor/hardware processor …” is a generic placeholder having no specific structure associated therewith. Because “processor/hardware processor …” is merely a generic placeholder having no specific structure associated therewith, the Examiner concludes that FP1 meets invocation Prong (A).
ii. 3-Prong Analysis: Prong (B)
Based upon a review of FP1, the Examiner finds the following claimed function(s) as:
[C]ontrolling the memory;
[D]etect[ing]s a memory access pattern in a virtual machine node; and
[P]erform[ing] a memory operation by using a memory block in consideration of the memory access pattern,
wherein the memory block dynamically changes in size based on the memory access pattern, including the memory block dynamically increasing in size when the memory operation includes a load operation that loads the memory block from the remote memory to the local memory
Because FP1 recites the above recited Functions, the Examiner concludes that FP1 meets Invocation Prong (B).
iii. 3-Prong Analysis: Prong (C)
Based upon a review of the entire Functional Phrase 1, the Examiner finds that Functional Phrase 1 does not contain sufficient structure for performing the entire claimed function that is set forth within Functional Phrase 1. In fact, the Examiner finds that Functional Phrase 1 recites very little structure (if any) for performing the claimed function. Specifically, while Functional Phrase 1 cites a processor/hardware processor, the processor is recited generically in association with special functions and thus the phrase does not recite sufficient structure for performing this special function.
Because Functional Phrase 1 does not contain sufficient structure for performing the entire claimed function, the Examiner concludes that Functional Phrase 1 meets invocation Prong (C).
Because Functional Phrase 1 meets the 3-prong analysis as set forth in MPEP § 2181 I, the Examiner concludes that Functional Phrase 1 invokes 35 U.S.C § 112 6th paragraph.
Corresponding structure for Functional Phrase 1
Once a claimed phrase invokes 35 U.S.C. § 112 6th paragraph, the next step is to determine the corresponding structure. (MPEP § 2181 II). In order to satisfy the requirements of 35 U.S.C. § 112, second paragraph, there must be identified in the applications’ disclosure a single structure and/or algorithm which performs the function of FP1.
The Examiner has carefully reviewed the original disclosure to determine the corresponding structure for FP1. In reviewing the original disclosure, the Examiner finds that the ‘090 Patent discloses:
In addition, according to an embodiment of the present invention, an apparatus for managing a disaggregated memory in a virtual system may include: a memory; and a processor controlling the memory. Herein, the processor may detect a memory access pattern based on an operation of a virtual machine in a virtual machine node, and perform a memory operation by using a memory block in consideration of the memory access pattern. Herein, the memory access pattern may be variably set based on a time at which the operation of the virtual machine is performed, and the memory block may dynamically change in size based on the memory access pattern.
(‘090 Patent at c.2, ll.35-46; emphasis added);
In an embodiment, the subject performing the above operation may be a processor. In other words, a memory and a processor may be present in an apparatus, and the processor may perform operations of managing the disaggregated memory on the basis of entities disclosed in FIG. 1 by organically operating in association with the memory.
(Id. at c.9, ll.34-40; emphasis added);
FIG. 8 is a view showing a method of managing a disaggregated memory.
(Id. at c.9, ll.22-23; emphasis added);
FIG. 9 is a view showing a configuration of an apparatus for managing a disaggregated memory. Referring to FIG. 9, a disaggregated memory managing apparatus 900 may be configured with a memory 910 and a processor 920. Herein, in an embodiment, the processor 920 may be a hardware unit corresponding to each program, each mode, and a manager of FIG. 1 described above. In other words, the configuration of FIG. 1 may be a logical entity and operate on the basis of the processor 920 described above.
(Id. at c.10, ll.20; emphasis added);
The method or algorithm descried in a relevance to the embodiments disclosed in the present specification may be implemented in a hardware module, a software module, or a combination thereof which is executed by a processor
(Id. at c.10, ll.42-45; emphasis added). In summary, the Examiner finds that the ‘090 Patent discloses an embodiment being implemented by hardware, firmware, software or combinations thereof. (Id. at c.12, ll.54-56). As set forth above, a processor/hardware processor can be defined or interpreted as either a system or mechanism that accepts a program and executes the program process with data to acquire a result, or a computer program. (See § IX.B.(1).i, supra). Thus, the Examiner finds that method being a series of steps, establishing an algorithm, being performed by a specialized processor. (See ‘090 Patent at Figure 8).
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With respect to the steps of the algorithm, in examination of examination of Figure 8 of the ‘090 Patent below, the Examiner find that steps S810 and S820 of Figure 5 are relevant to the determination of the structure of FP1. The Examiner finds that step S810 variably sets the access pattern on the basis of; 1) a time of at which the operation of the virtual machine is performed (‘090 Patent at Abstract; c.2, ll.27-29, 42-44; c.9, ll.46-49; original claims 1, 15, 18); or 2) according to other components, broadly (id. at c.9, ll.49-52; also see c.1, ll.52-55 discussion on how access patterns potentially vary). However, while the ‘090 Patent discloses detecting and access pattern, the Examiner finds that detecting an access pattern based upon time or other components is not a simple calculation.
First, the Examiner can find insufficient disclosure to what exactly the “detecting” and “performing” steps are and what the results thereof would be. From this perspective, and in examination of Figure 8 of the ‘090 Patent above, while one of ordinary skill in the art would recognize the exemplary steps/processes for “detecting [a] memory access pattern…” and “performing [a[ memory operation…”, the Examiner finds that the ‘090 Patent provides the “detecting” and “performing” steps as being determined by a black box. (See Figure 8 for the exemplary “black box” structure of the prediction function of the unit proper). The Examiner finds that the ‘090 Patent fails to disclose or discuss the exact criteria and/or algorithms of “detecting [a] memory access pattern…” and “performing [a[ memory operation…” and how their results are utilized to detect an access pattern and/or perform a memory operation in consideration of the detected access pattern. (See discussion supra). Moreover, the Examiner finds it unclear to whether steps S810 and S820 require more information or functionality to perform the required claimed functionality. Thus, the Examiner concludes that the functions and ‘090 Patent fail to clearly link and associate corresponding structure to FP1.4
In light of the finding that Functional Phrase 1 invokes 35 U.S.C. § 112 6th paragraph, Functional Phrase 1 is construed to cover the corresponding structure described in the specification and equivalents thereof. From this perspective, the Examiner construes the structure and/or algorithm for performing the claimed function as a software component, that can be executed by a processor, or a hardware component that can perform the claimed operations, as recited, without any regards to any particular algorithms, or its equivalent
Functional Phrase – “Disaggregated Memory Manager”
A second means-plus-function phrase is recited in claims 18 and 32 (and included in each of dependent claims 19 and 20) which recites “manager …” or hereinafter “Functional Phrase 2” or “FP2.” The Examiner determines herein that FP2 does meet the three prong test and thus will be interpreted as a means-plus-function limitation under 35 U.S.C. §112(6th ¶).
The Examiner finds that claim 18 expressly recites:
a disaggregated memory manager of the virtual node
detects a memory access pattern, and
performs a memory operation by using a memory block in consideration of the memory access pattern,
wherein the memory block dynamically changes in size based on the memory access pattern, including the memory block dynamically increasing in size when the memory operation includes a load operation that loads the memory block from the remote memory to the local memory
[emphasis added]; claim 32 expressly recites:
a disaggregated memory manager of the virtual node
detects, via a hardware processor, a memory access pattern based on an operation of the virtual machine, and
performs a memory operation by using a memory block in consideration of the memory access pattern,
wherein the memory access pattern is variably set based on a time at which the operation of the virtual machine is performed, and
wherein the memory block dynamically changes in size based on the memory access pattern, including the memory block dynamically increasing in size when the memory operation includes a load operation that loads the memory block from the remote memory to the local memory
[emphasis added].
i. 3-Prong Analysis: Prong (A)
FP2 meets invocation prong (A) because "means ... for" type language is recited. The Examiner first finds that “manager” is a generic placeholder or nonce term equivalent to “means” because the term “manager” conveys some structures, but not any specific structures related to the function.
Additionally, the Examiner has reviewed the prosecution history and the relevant prior art of record herein and find that “manager” as used in the claims does not provide an art-recognized structure to perform the claimed function. The Examiner finds that a manager is definable as “any program that is designed to perform a certain set of housekeeping tasks related to computer operation, such as the maintenance of files.”5 Moreover, the Examiner further notes that the phrase “disaggregated memory” does not impart or disclose any structure for the phrase in light of the phrase imparting the same functionality. Accordingly, the Examiner finds that manager implies little more than a generic program in association with a special function. Rather more than a simple manager would be required to perform the function recited in FP2. This is further evidenced above by the other claim set referencing the same functions being performed by a different element (i.e., a “processor, per se). (See § IX.B.(1), supra).
Accordingly, the Examiner finds nothing in the specification, prosecution history or the prior art to construe “manager…” in FP2 as the name of a sufficiently definite structure for performing the functions recited in FP2 so as to take the overall claim limitation out of the ambit of §112(6th ¶). See Williamson v. Citrix Online, L.L.C., 115 USPQ2d 1105, 1112 (Fed. Cir. 2015).
In light of the above, the Examiner concludes that the term “manager…” is a generic placeholder having no specific structure associated therewith. Because “manager …” is merely a generic placeholder having no specific structure associated therewith, the Examiner concludes that FP2 meets invocation Prong (A).
ii. 3-Prong Analysis: Prong (B)
Based upon a review of FP2, the Examiner finds the following claimed function(s) as:
[D]etect[ing]s a memory access pattern; and
[P]erform[ing] a memory operation by using a memory block in consideration of the memory access pattern,
wherein the memory block dynamically changes in size based on the memory access pattern, including the memory block dynamically increasing in size when the memory operation includes a load operation that loads the memory block from the remote memory to the local memory
Because FP2 recites the above recited Functions, the Examiner concludes that FP2 meets Invocation Prong (B).
iii. 3-Prong Analysis: Prong (C)
Based upon a review of the entire Functional Phrase 2, the Examiner finds that Functional Phrase 2 does not contain sufficient structure for performing the entire claimed function that is set forth within Functional Phrase 2. In fact, the Examiner finds that Functional Phrase 2 recites very little structure (if any) for performing the claimed function. Specifically, while Functional Phrase 2 cites a manager, the manager is recited generically in association with special functions and thus the phrase does not recite sufficient structure for performing this special function.
Because Functional Phrase 2 does not contain sufficient structure for performing the entire claimed function, the Examiner concludes that Functional Phrase 2 meets invocation Prong (C).
Because Functional Phrase 2 meets the 3-prong analysis as set forth in MPEP § 2181 I, the Examiner concludes that Functional Phrase 2 invokes 35 U.S.C § 112 6th paragraph.
Corresponding structure for Functional Phrase 2
Once a claimed phrase invokes 35 U.S.C. § 112 6th paragraph, the next step is to determine the corresponding structure. (MPEP § 2181 II). In order to satisfy the requirements of 35 U.S.C. § 112, second paragraph, there must be identified in the applications’ disclosure a single structure and/or algorithm which performs the function of FP2.
The Examiner has carefully reviewed the original disclosure to determine the corresponding structure for FP2. In reviewing the original disclosure, the Examiner finds that the ‘090 Patent discloses:
according to an embodiment of the present invention, a virtual system for managing a disaggregated memory may include: a virtual machine node controlling an operation of a virtual machine; and a memory node controlling a memory operation. Herein, a disaggregated memory manager of the virtual machine node may detect a memory access pattern based on an operation of the virtual machine, and perform a memory operation by using a memory block in consideration of the memory access pattern. Herein, the memory access pattern may be variable set based on a time at which the operation of the virtual machine is performed, and the memory block may dynamically change in size based on the memory access patter
(‘090 Patent at c.2, ll.53-65; emphasis added);
FIG. 1 is a view showing a configuration of a disaggregated memory manager.
(Id. at c.4, ll.18-19; c.5, ll.27-28; emphasis added);
In detail, in the virtual system, a disaggregated memory manager 118 may be present. Herein, the disaggregated memory manager 118 may process remote memory access occurring in a virtual machine node 110. In an embodiment, when the virtual machine node 110 wants to access a remote memory, the disaggregated memory manager 118 may load the remote memory to a local memory. In addition, the disaggregated memory manager 118 may store the local memory to the remote memory. In an embodiment, the disaggregated memory manager 118 may store a first memory page 121 of the local memory to the remote memory on the basis of an operation of the virtual machine node 110. Herein, the first memory page 121 may be an arbitrary memory page present in the local memory, but it is not limited to the above embodiment. In other words, the disaggregated memory manager 118 may store the local memory to the remote memory. In addition, the disaggregated memory manager 118 may load a second memory page 122 present in the remote memory to the local memory on the basis of an operation of the virtual machine node 110. Herein, the second memory page 122 may be an arbitrary memory page present in the remote memory, but it is not limited to the above embodiment. Herein, the disaggregated memory manager 118 may map the loaded local memory to an address space used by the virtual machine node 110, and by the same, the virtual machine node 110 may use the loaded local memory. In other words, kernel or application programs operating in a virtual machine are enabled to access the corresponding memory. Meanwhile, the disaggregated memory manager 118 may store a memory that is not accessed by the virtual machine node 110 in the remote memory. In other words, the disaggregated memory manager 118 may determine a memory that is used by the virtual machine node 110, load the same to the local memory, and store an unused memory in the remote memory.
(Id. at c.5, ll.29-65; emphasis added);
the disaggregated memory manager 118 operating in a virtual machine may continuously determine spatial locality of a memory managed during which the virtual machine is in operation. Accordingly, the disaggregated memory manager may perform loading, storing, mapping and un-mapping to a guest physical address (GPA), etc. which are memory operations. Herein, the disaggregated memory manager may perform the operation in a grout unit of continuous memory pages having a spatial locality when performing the above operations.
(Id. at c.6, ll.57-67; emphasis added);
Referring to FIG. 8, in S810, a memory access pattern may be detected on the basis of an operation of a virtual machine in a virtual machine node. Herein, as described with reference to FIGS. 1 to 7, the disaggregated memory manager may perform memory access processing on the basis of the operation of the virtual machine. Herein, in an embodiment, the virtual machine node, memory node, etc. of FIG. 1 may be a logical configuration. In addition, the disaggregated memory manager may also be a logical configuration, and may be an entity representing a subject of managing the disaggregated memory. In an embodiment, the subject performing the above operation may be a processor. In other words, a memory and a processor may be present in an apparatus, and the processor may perform operations of managing the disaggregated memory on the basis of entities disclosed in FIG. 1 by organically operating in association with the memory.
(Id. at c.9, ll.24-40; emphasis added);
FIG. 8 is a view showing a method of managing a disaggregated memory.
(Id. at c.9, ll.22-23; emphasis added);
FIG. 9 is a view showing a configuration of an apparatus for managing a disaggregated memory. Referring to FIG. 9, a disaggregated memory managing apparatus 900 may be configured with a memory 910 and a processor 920. Herein, in an embodiment, the processor 920 may be a hardware unit corresponding to each program, each mode, and a manager of FIG. 1 described above. In other words, the configuration of FIG. 1 may be a logical entity and operate on the basis of the processor 920 described above.
(Id. at c.10, ll.20; emphasis added);
The method or algorithm descried in a relevance to the embodiments disclosed in the present specification may be implemented in a hardware module, a software module, or a combination thereof which is executed by a processor.
(Id. at c.10, ll.42-45; emphasis added). In summary, the Examiner finds that the ‘090 Patent discloses an embodiment being implemented by hardware, firmware, software or combinations thereof. As set forth above, a processor can be defined or interpreted as either a system or mechanism that accepts a program and executes the program process with data to acquire a result, or a computer program. (See § IX.B.(1).i, supra). Thus, the Examiner finds that method being a series of steps, establishing an algorithm, being performed by a specialized processor. (See ‘090 Patent at Figure 8).
With respect to the steps of the algorithm, in examination of examination of Figure 8 of the ‘090 Patent below, the Examiner find that steps S810 and S820 of Figure 8 are relevant to the determination of the structure of FP2. The Examiner finds that step S810 variably sets the access pattern on the basis of; 1) a time of at which the operation of the virtual machine is performed (‘090 Patent at Abstract; c.2, ll.27-29, 42-44; c.9, ll.46-49; original claims 1, 15, 18); or 2) according to other components, broadly (id. at c.9, ll.49-52; also see c.1, ll.52-55 discussion on how access patterns potentially vary). However, while the ‘090 Patent discloses detecting and access pattern, the Examiner finds that detecting an access pattern based upon time or other components is not a simple calculation.
First, the Examiner can find insufficient disclosure to what exactly the “detecting” and “performing” steps are and what the results thereof would be. From this perspective, and in examination of Figure 8 of the ‘090 Patent above, while one of ordinary skill in the art would recognize the exemplary steps/processes for “detecting [a] memory access pattern…” and “performing [a[ memory operation…”, the Examiner finds that the ‘090 Patent provides the “detecting” and “performing” steps as being determined by a black box. (See Figure 8 for the [AltContent: textbox (Figure 8 of '090 Patent)]
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exemplary “black box” structure of the prediction function of the unit proper). Moreover, the Examiner finds that the “disaggregated memory manager” disclosed in Figure 1 of the ‘090 Patent is also a black box. The Examiner finds that the ‘090 Patent fails to disclose or discuss the exact criteria and/or algorithms of “detecting [a] memory access pattern…” and “performing [a[ memory operation…” and how their results are utilized to detect an access pattern and/or perform a memory operation in consideration of the detected access pattern. (See discussion supra). Moreover, the Examiner finds it unclear to whether steps S810 and S820 require more information or functionality to perform the required claimed functionality. Thus, the Examiner concludes that the functions and ‘090 Patent fail to clearly link and associate corresponding structure to FP2.6
In light of the finding that Functional Phrase 2 invokes 35 U.S.C. § 112 6th paragraph, Functional Phrase 2 is construed to cover the corresponding structure described in the specification and equivalents thereof. From this perspective, the Examiner construes the structure and/or algorithm for performing the claimed function as a program component, that can be executed by a processor, that can perform the claimed operations, as recited, without any regards to any particular algorithms, or its equivalent.
'Sources' for the 'Broadest Reasonable Interpretation'
For terms not lexicographically defined by Applicant, the Examiner hereby adopts the following interpretations under the broadest reasonable interpretation standard. In other words, the Examiner has provided the following interpretations simply as express notice of how he is interpreting particular terms under the broadest reasonable interpretation standard. Additionally, these interpretations are only a guide to claim terminology since claim terms must be interpreted in context of the surrounding claim language.7 In accordance with In re Morris, 127 F.3d 1048, 1056, 44 USPQ2d 1023, 1029 (Fed. Cir. 1997) (“Morris”), the Examiner points to these other “sources” to support his interpretation of the claims. Finally, the following list is not intended to be exhaustive in any way:
Disaggregated Memory
The Examiner finds that the ‘090 Patent states,
[m]eanwhile, the memory 910 may be configured with a local memory and a remote memory as shown in FIG. 1. In other words, the memory 910 may be a disaggregated memory form, and operate on the basis of a disaggregated memory as described above.
(‘090 Patent at c.10, ll.30-35; emphasis). In addition, the Examiner finds that commonly owned U.S. Patent No. 10,754,547 (“‘547 Patent”) states
[i]n order to support the large capacity memory using the commodity volume server, used is a disaggregated memory structure technology in which memories distributed among different physical computing devices (for example, severs) operate as a single memory.
(‘547 Patent at c.1, ll.60-64; emphasis). From this perspective, the Examiner first finds that the “disaggregated memory” is memories of a distributed architecture system that operate as a single memory.
Access Pattern
The Examiner finds that the ‘090 Patent states,
pre-fetching based on a memory access pattern of an application program widely used in a micro-architecture is required. However, a memory access pattern of the application programs varies according to application, time, position, and capacity of a local memory, and thus static temporal profiling is limited in optimizing the system
(‘090 Patent at c.1, ll.52-55; emphasis). From this perspective, the Examiner first finds that “access pattern” is a characteristic of a particular application that varies according to application, time, position, and capacity of a local memory.
Claim Rejections – 35 U.S.C. § 112
35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
New Matter
Claims 13 and 14 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for pre-AIA the inventor(s), at the time the application was filed, had possession of the claimed invention.
The Examiner finds that claim 13 recites,
wherein the memory block has a size of 2n times of a memory page and dynamically changes in size, wherein n is a constant.
(June 2025 Claim Amendment at claim 13; emphasis added). The Examiner finds that recitation to the method comprising a memory block that has a size of 2n times of a memory page is not sufficiently described in the ‘090 Patent. To support the Examiner’s position, the Examiner finds that the ‘090 Patent states:
[i]n addition, a size of the corresponding memory may dynamically vary, and the size may have a size that is multiple of 211 (n is a constant) of a page defined in a micro-architecture.
(‘090 Patent at c.7, l.6-9). Similarly, original claim 13 recites,
wherein the memory block has a size of 211 times of a memory page and dynamically changes in size, wherein n is a constant.
(Id. at claim 13). In the Sept 2022 Claim Amendment, original claim 13 was canceled, thus, only the disclosure was objected to. (See March 2025 Non-Final Office Action at § VII). Specifically, the March 2025 Non-Final Office Action objected to the disclosure of the ‘090 Patent asserting that “211” should read – 2n – instead. In the instant June 2025 Spec Amendment, Applicant has corrected this issue.
However, the instant June 2025 Claim Amendment returns claim 13 back to its original state. (June 2025 Claim Amendment at claim 13). Contrary to placing claim 13 back to its original form, Applicant has instead replaced “211” with “2n.” Hence, since the claims now specifically require “2” to be multiplied by “n” instead of raised to the power of “n,” the Examiner finds the claim requirement as new matter.
Thus, as such, the Examiner concludes that there is insufficient indication in the specification that Applicant had possession of a method comprising a memory block that has a size of 2n times of a memory page, as recited.
Claim 14 is similarly rejected based on its dependency from dependent claim 13.
35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall