Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Final Office Action
DETAILED ACTION
Examiner’s Notes
(a) Claim date: 03/13/2026 (not amendment).
(b) Comment: The rejections are maintained.
Applicant’s argument and Examiner’s Response
Applicant’s arguments have been fully considered; however, some/all are NOT found to be persuasive because of the following reasons:
Applicant:
I. Claims Rejections under 35 U.S.C. Q 112
Claim 11 stands rejected under 35 U.S.C. § 112(a) for lack of written description.
Applicant traverses the rejection.
The Action states, at pp. 3-6, that the term "architectural configuration" is unclear and misleading. Applicant disagrees.
[0014] describes "a flexible hybrid multi-bit flip-flop architecture for low power and high-performance applications. In this architecture, several different single-bit flip-flops can be merged together to form a multi-bit flip-flop for better area and timing, while nevertheless preserving the power consumption close to that of a standard uniform architecture." The Specification at para.
[0017] describes that "different kinds or configurations of SBFFs that can be flexibly merged together," and that "a single MBFF can feature different variants of SBFFs, thereby enabling MBFFs of different shapes, sizes, and performance ratings to be flexibly constructed and placed." Moreover, the Specification, at paras.
[0045]-[0056] and as shown in FIGs. 4-9, describe different architectural configurations of ACTIVE 716595611v3 single-bit flip flops. Therefore, the Specification provides adequate written description support of the claimed subject matter so that a person of ordinary skill in the art (POSITA) can recognize what is claimed. Thus, Applicant respectfully requests favorable reconsideration of the claim and withdrawal of the rejection.
Examiner:
MPEP 2173.02: Zletz, 893 F.2d at 322, 13 USPQ2d at 1322. For example, if the language of a claim, given its broadest reasonable interpretation, is such that a person of ordinary skill in the relevant art would read it with more than one reasonable interpretation, then a rejection under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph is appropriate.
Using various examples below, the examiner will be trying to establish that “the language of a claim, given its broadest reasonable interpretation, is such that a person of ordinary skill in the relevant art would read it with more than one reasonable interpretation”.
First, an ordinary skilled in the art of digital logic design would agree that the pertinent art (digital logic design) is a very highly specified field. Topics under this art often requires sufficient disclosure with technical support for distinct interpretations. In order to explain examiners point of view, let’s begin with some examples:
Consider the following two examples below:
(1) Two houses are placed next to each other; each having different architectural configuration.
(2) Two digital logic gates are placed next two each other; each having different architectural configuration.
An ordinary skilled in the pertinent art would have a reasonable understanding of statement #1, but not statement #2. This is because, the utility of a house with a minor architectural change does not vary as much as a digital logic does. For the digital logic, some additional questions will arrive.
Such as:
(a) Do the different architecture have identical/different logic functions?
(b) Do the different architecture have identical/different layout structure?
(c) Do the different architecture have identical/different supply (Vcc, Gnd) or timing requirement?
(d) and so on.
Let’s provide another example. Consider well known architecture of JK an RS flip-flop as given below.
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Both are single bit flip-flop, and both are well known by the ordinary skilled in the art. They have distinct difference architecture having different usage of logic gates and interconnects. Also, their truth tables are different.
Now, lets consider the following two statements:
(1) A logic function comprised of two-bit flip-flop, wherein, each flip-flop having different architecture.
(2) A logic function comprised of two-bit flip-flop, wherein, the first flip-flop has JK architecture and the second flip-flop has RS architecture.
Between the two statements, only the statement #2 will be fully understood by an ordinary skilled and not the statement #1.
Now, lets analyze the claim limitations:
1. (Withdrawn) A method for constructing hybrid multi-bit flip-flops, the method comprising: configuring a first single-bit flip-flop in a first architectural configuration; configuring a second single-bit flip-flop in a second architectural configuration that is distinct from the first architectural configuration of the first single-bit flip-flop; and connecting the first single-bit flip-flop and the second single-bit flip-flop to form a hybrid multi-bit flip-flop.
Let’s try to interpret the claim limitations in view of the applicant’s disclosure:
(1) Both the first and the second single-bit flip-flop uses identical logic architecture (both JK or both RS), however, they are distinct because the logic gates are placed in different physical/logical/layout/power/placement/timing/… orientations.
(2) Both the first and the second single-bit flip-flop uses distinctly different logic architecture (one is JK and the other is RS).
In summary, the claim limitation will have various reasonable interpretations in view of the disclosure, when given broadest reasonable interpretations. Therefore, rejection is maintained.
Applicant:
II. Claim Rejections under 35 U.S.C. Q 102
Independent claim 11 stands rejected under 35 U.S.C. § 102(a)(1) as allegedly being
anticipated by U.S. Pat. App. 20210357567 ("Sherlekar"). Applicant respectfully disagrees that any of the pending claims is anticipated by Sherlekar.
Claim 11 recites, in pertinent part, "a first single-bit flip-flop having a first architectural configuration; and a second single-bit flip-flop that is connected to the first single-bit flip-flop and that has a second architectural configuration that is distinct from the first architectural configuration." (Emphasis added.) The Action states that Sherlekar discloses "a first single-bit flip-flop 110a and a second single-bit flip flop 110b" used to implement a FlexMBFF." (Action at p. 8.) The Action also states that Sherlekar discloses "selecting a control block of desired characteristics (e.g., implemented with specified VT transistors and specified drive strength to achieve target performance for the flip-flop bits in the FlexMBFF instance." (Action at p. 11.) Moreover, the Action states that Sherlekar discloses FIGs. lA and 1B illustrate the area benefit obtained by sharing a control block between multiple flip-flops when combined in a FlexMBFF." (Action at pp. 11-12.)
For at least the following reasons, Sherlekar does not disclose the above recited features of claim 11.
Sherlekar discloses that:
FlexMBFF approach further permits construction of MBFFs with any specified bit-count, further improving upon current libraries which provide only a subset of bit counts-for example, 2, 4, 8, and 16. Moreover, the FlexMBFF approach permits incrementally changing an existing MBFF by adding or removing one or more flip-flop bits, or modifying one or more flip-flop bits or the control
block, without completely dismantling the MBFF.
(Sherlekar at [0019].) Sherlekar also discloses that the "Flip-flops come in several varieties, including D flip-flops, T flip-flops, and JK flip-flops, of which any of one can be combined into a multi-bit flip-flop." (Sherlekar at [0002] (emphasis added).)
Sherlekar does not disclose "a second single-bit flip-flop that is connected to the first
single-bit flip-flop and that has a second architectural configuration that is distinct from the first architectural configuration," as recited in claim 11. Sherlekar does not disclose that any one of the different types of flip-flops having different architectures can be combined together to form the "FlexMBFF." Instead, Sherlekar discloses that "any of one" of the same flip-flop (e.g., D flip-flops, T flip-flops, and JK flip-flops) can be combined into the "FlexMBFF." Accordingly, Sherlekar discloses that each of the flip-flops in the "FlexMBFF" are "uniform multi-bit flip flops" (e.g., the same flip-flop) and does not disclose that each of the flip-flops can be distinct from each other in the "FlexMBFF." Therefore, Sherlekar does not disclose "a second single-bit flip-flop that is connected to the first single-bit flip-flop and that has a second architectural configuration that is distinct from the first architectural configuration," as recited in claim 11.
Therefore, Sherlekar does not disclose the "hybrid multi-bit flip flops," as recited in amended claim 11.
Examiner:
It appears that the applicant is interpreting the claim limitation based on ONLY the applicant’s disclosure, and without giving other broadest reasonable interpretations in view of the disclosure. As explained earlier, it is a common practice in the art of VLSI circuit design to use various types of flip-flops, depending on their advantages/disadvantages. When given broadest reasonable claim interpretation, the invention claims simply boils down to: “two different types of flip-flops that are connected together to optimize some functionality”, which the prior art sufficiently teaches (as below). Therefore, the rejections are maintained.
Claim Rejections - 35 USC § 112
35 U.S.C. 112(b):
The following is a quotation of 35 U.S.C. 112(b):
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter, which the applicant regards as his invention.
MPEP 2173.02: Zletz, 893 F.2d at 322, 13 USPQ2d at 1322. For example, if the language of a claim, given its broadest reasonable interpretation, is such that a person of ordinary skill in the relevant art would read it with more than one reasonable interpretation, then a rejection under 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph is appropriate.
35 U.S.C. 112(a):
The following is a quotation of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Based on the examiner’s analysis (described below), the applicant failed to enable any person skilled in the art to which it pertains without any undue experiments. Therefore, the listed claims are further rejected.
(a) Claim 11, limitation “first single-bit flip-flop having a first architectural configuration” is unclear. For similar reason limitation “second single-bit flip-flop … has a second architectural configuration” is also unclear.
Applicant’s pertinent disclosures:
[0019] A method for constructing hybrid multi-bit flip-flops can include configuring a first single-bit flip-flop in a first architectural configuration, configuring a second single-bit flip- flop in a second architectural configuration that is distinct from the first architectural configuration of the first single-bit flip-flop, and connecting the first single-bit flip-flop and the second single-bit flip-flop to form a hybrid multi-bit flip-flop.
[0026] In some examples, the first architectural configuration includes a high-performance architectural configuration that features a latency between a clock signal and a data pin below a predetermined threshold.
[0027] In some examples, the first architectural configuration includes a compact area architectural configuration that is substantially smaller in area size than the high- performance architectural configuration.
[0028] In some examples, the first architectural configuration includes a clock delay configuration.
Examiner’s analysis:
(i) First: The usage of the terminology for the claim limitation “architectural configuration” is misleading. One ordinary skilled in the pertinent art would NOT interpret this limitation as intended in the applicant’s discloser (highlighted above). An architecture generally refers to “physical structure” of “form”. It may not necessarily refer to some of the commonly used terminologies, such as: a “design method”, “design specification”, or “design rules” and etc.
Let’s see the google definition of architecture:
“In chip design, architecture refers to the overall design and logical structure of a chip, including the instruction set architecture (ISA) that defines how the chip processes data, and the microarchitecture, which details the specific hardware implementation.”
Let’s analyze the applicant’s supporting disclosure:
The applicant’s disclosure in Para [0029] “first architectural configuration includes a high-performance architectural configuration” makes no sense.
Similarly, the applicant’s disclosure in Para [0027] “first architectural configuration includes a clock delay configuration” also makes no sense.
Now, let consider some of sentences as examples, that would actually make sense:
For Para. [0029] “first design configuration includes a high-performance clock-network architectural configuration”
For Para. [0027] “first design configuration includes an optimized clock delay configuration”.
(ii) Second, the scope of the limitation is indefinite. If the applicant intended to include all possible design variation, including: logical design, placement, process variation, timing optimization, and so on; then, there would an infinite number of possibilities of the so called “first architectural configuration” and “second architectural configuration”. The difference between these two also going to be infinite.
In summary, the said claims failed both 112(a) and 112(b) requirements, therefore rejected.
(b) Claim 11, limitation “hybrid multi-bit flip-flop” and “uniform multi-bit flip-flop” are unclear.
Applicant’s pertinent disclosures:
[0016] Several modern chip designs are facing this problem. In such cases, it would be desirable, and easier, to replace a standard uniform MBFF with a hybrid version. As discussed further below, the hybrid version of the MBFF (which is formed of SBFFs having substantially different architectures, configurations, performance qualities, or sizes, for example) can have minimal area impact and close to no impact on the clock tree when used to perform the single bit substitution instead of traditional debanking. Usage of the hybrid MBFFto avoid the disruptive debanking procedure would result in a significant boost in improvement to the current design flows practices in this field.
Examiner’s analysis:
First, all/some of the terminology found in the “unclear limitations” are NOT well-known or commonly-utilized in the pertinent art. Second, the applicant disclosure did NOT define or describe the terminology enough, in a manner, so that one in ordinary skilled in the art could distinctly interpret these limitations at the time of this invention.
The applicant simply hinted that a hybrid version MBFF can be better in many aspects, compared to a uniform MBFF. But this much disclosure is not sufficient to distinctly interpret the claim limitation.
For better explanation, let’s consider the following hypothetical statements:
(i) “a power transistor is better than a CMOS transistor”.
(ii) “a hybrid transistor is better than a uniform transistor”.
For the statement (i), an ordinary skilled person will be partially confused. For the statement (ii), an ordinary skilled person will be completely confused. In order for one ordinary skilled person to understand the statement, one needs to know what makes a transistor to become “uniform” or “hybrid”.
In summary, from the applicant disclosure, what makes a MBFF to be “uniform” or to be “hybrid” is not clear.
Claim Rejections - 35 USC 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:A person shall be entitled to a patent unless:(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.Claims 11-19, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by the prior art of Reference “(SHERLEKAR, US 20210357567 A1)”.(As to claim 11, Reference discloses):11. A hybrid multi-bit flip-flop comprising [0002: “multi-bit flip-flop”, Also refer to 0005: “a FlexMBFF family that includes a plurality of control blocks and a plurality of flip flop blocks with different characteristics”. The FlexMBFF of the reference is functionally equivalent of the claim limitation “hybrid multi-bit flip-flop”. Please refer to Para. 24, 25, 28 and 30 for additional supports]:
a first single-bit flip-flop having a first architectural configuration [0027: “FIG. 1A shows a first single-bit flip-flop 110a and a second single-bit flip-flop 110b, used to implement a FlexMBFF”]; and
a second single-bit flip-flop that is connected to the first single-bit flip-flop [0027: “FIG. 1A shows a first single-bit flip-flop 110a and a second single-bit flip-flop 110b, used to implement a FlexMBFF”] and
that has a second architectural configuration that is distinct from the first architectural configuration [0030: “a first software representation of a FlexMBFF with characteristic set X and a second software representation of a FlexMBFF with characteristic set X but with a different relative arrangement of the bit-slice blocks or flip-flop components 120, can be considered two instances of one MBFF”].
(As to claim 12, Reference discloses):12. The hybrid multi-bit flip-flop of claim 11, wherein the hybrid multi-bit flip-flop consumes power at substantially equal to or less than a uniform multi-bit flip-flop [0037: “Performance, power and reliability considerations may reduce the range of control block drive strengths that can be used for a given set of flip-flop bit-slice blocks”].
(As to claim 13, Reference discloses):13. The hybrid multi-bit flip-flop of claim 11, wherein the hybrid multi-bit flip-flop uses a clock path that is substantially the same as for a uniform multi-bit flip-flop [0023: “clock path to enable injection of useful clock signal skew. The control block may also contain an integrated clock gating logic that may be used to gate the flop bits in the MBFF.”; note: identical clock path is being used for all the MBFF].
(As to claim 14, Reference discloses):14. The hybrid multi-bit flip-flop of claim 11, wherein the multi-bit flip-flop is placed within a semiconductor device such that a timing specification is satisfied [0038: “timing critical flip-flop bits in MBFFs and map the flip-flop bits to higher performance flip-flops/MBFFs.”, “placement”].
(As to claim 15, Reference discloses):15. The hybrid multi-bit flip-flop of claim 14, wherein the multi-bit flip-flop was placed within the semiconductor device while bypassing a procedure for debanking a uniform multi-bit flip-flop into single-bit flip-flops [0032: “Global signals may be routed at a design level, as is the case with pre-built MBFFs. For non stitched MBFFs (e.g., MBFFs without control signals routed internally between flip-flop bits),”].
(As to claim 16, Reference discloses):
16. The hybrid multi-bit flip-flop of claim 14, wherein placing the multi-bit flip-flop was performed during a place-and-route design stage [0020: “placement. The degradation may also happen any time after MBFF mapping, such as during clock insertion, timing/power improvements, and routing”].
(As to claim 17, Reference discloses):
17. The hybrid multi-bit flip-flop of claim 11, wherein the hybrid multi-bit flip-flop is formed of 2xN single-bit flip-flops where N is a natural number [Fig. 1B].
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(As to claim 18, Reference discloses):
18. The hybrid multi-bit flip-flop of claim 11, wherein the first architectural configuration comprises a high-performance architectural configuration that features a latency between a clock signal and a data pin below a predetermined threshold [0029: “selecting a control block of desired characteristics (e.g., implemented with specified VT transistors and specified drive strength to achieve target performance for the flip-flop bits in the FlexMBFF instance)”].
(As to claim 19, Reference discloses):
19. The hybrid multi-bit flip-flop of claim 18, wherein the second architectural configuration comprises a compact area architectural configuration that is substantially smaller in area size than the high-performance architectural configuration [0026: “ FIGS. 1A and 1B illustrate the area benefit obtained by sharing a control block between multiple flip-flops when combined in a FlexMBFF, according to embodiments of the present disclosure.”].
Conclusion
If any prior art made of record in the form PTO-892 and not relied upon, then those arts should simply be considered as pertinent, to the applicant's disclosure.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
The time for reply to a final rejection is as follows (MPEP paragraphs: 7.39, 7.40, 7.40.01, 7.40.02.fti, 7.40.02.aia, 7.41, 7.41.03, 7.42.03.fti, 7.42.031.fti, or 7.42.09):
A shortened statutory period will expire at 3 months from the date of the final rejection or on the date the advisory action is mailed, whichever is later. Thus, a variable reply period will be established. If the last day of "2 months of the date of the final Office action" falls on Saturday, Sunday, or a federal holiday within the District of Columbia, and a reply is filed on the next succeeding day which is not a Saturday, Sunday, or a federal holiday, pursuant to 37 CFR 1.7(a), the reply is deemed to have been filed within the 2 months period and the shortened statutory period will expire at 3 months from the date of the final rejection or on the mailing date of the advisory action, whichever is later (see MPEP § 710.05). In no event can the statutory period for reply expire later than 6 months from the mailing date of the final rejection.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED ALAM at telephone number is (571) 270-1507, fax number is (571) 270-2507 and email address:mohammed.alam@uspto.gov. The examiner can normally be reached on 10AM to 4PM (EST), Monday to Thursday. If attempts to reach the examiner by telephone are unsuccessful, the Examiner’s Supervisor, JACK CHIANG can be reached on (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Mohammed Alam/
Primary Examiner, Art Unit 2851
Prosecution Insights