DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Response to Amendment
Applicant’s amendment appears to have obviated the specification, drawing, and claim objections. Therefore, those objections are withdrawn.
Claim Rejections - 35 USC § 101
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The analysis of the claims will follow the 2019 Revised Patent Subject Matter Eligibility Guidance, 84 Fed. Reg. 50 (“2019 PEG”).
Claim 1
Step 1: The claim recites a method; therefore, it is directed to the statutory category of processes.
Step 2A Prong 1: The claim recites, inter alia:
[D]etermining spatial segmentation of a first tensor … and a second tensor …, the spatial segmentation dividing the first tensor and the second tensor into a plurality of partitions derived in a raster scan fashion, wherein a first partition comprises a number of consecutive elements in a first row, and a second partition comprises the number of consecutive elements in a second row arranged in a zigzagged manner with respect to the first partition, the second tensor … being derived based on [an] output tensor generated by performing convolution on the first tensor: This limitation could encompass mentally segmenting the two tensors by mentally dividing them into partitions. The convolution is a mathematical concept that could be performed mentally given sufficiently simple tensors.
[D]etermining … dependencies of tasks, each of the tasks corresponding to one or more of the plurality of partitions: This limitation could encompass mentally determining the dependencies of the tasks.
[G]enerating … a first task schedule of the tasks that satisfies the dependencies of the tasks: This limitation could encompass mentally generating the task schedule.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. The claim further recites “allocating … a first subset of the tasks, that have completion times at the neural processor satisfying a first timing constraint, to a same first portion of a memory in the neural processor for storage.” This limitation recites the insignificant extra-solution activity of mere data gathering and output. MPEP § 2106.05(g). The claim also recites that the convolution is performed “by a neural processor” and “by a processor”, that the tensors are “of a first layer of a neural network” and “a second layer of the neural network”, and that the tensor on which the convolution is performed is “of the first layer that is a lower layer in a hierarchy of the neural network”. These limitations amount to mere instructions to apply the judicial exception on a generic computer programmed with a generic class of computer algorithm. MPEP § 2106.05(f).
Step 2B: The claim does not contain significantly more than the judicial exception. The allocating limitation, in addition to being insignificant extra-solution activity, also recites the well-understood, routine, and conventional activity of storing or retrieving information in memory. MPEP § 2106.05(d)(II); Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015). Otherwise, the analysis at this step mirrors that of step 2A, prong 2. As an ordered whole, the claim is directed to a mentally performable process of scheduling computational tasks based on their dependencies. Nothing in the claim provides significantly more than this. As such, the claim is not patent eligible.
Claim 2
Step 1: A process, as above.
Step 2A Prong 1: The claim recites the same judicial exceptions as in claim 1.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. The claim further recites “allocating a second subset of the tasks satisfying a second time constraint associated with completion times of the second subset of the tasks at the neural processor to a same second portion of the memory in the neural processor for storage, the first timing constraint requiring the first subset of the tasks to have completion times within a first time frame, and the second time constraint requiring the second subset of the tasks to have completion times within a second time frame.” This limitation recites the insignificant extra-solution activity of mere data gathering and output. MPEP § 2106.05(g).
Step 2B: The claim does not contain significantly more than the judicial exception. The claim further recites “allocating a second subset of the tasks satisfying a second time constraint associated with completion times of the second subset of the tasks at the neural processor to a same second portion of the memory in the neural processor for storage, the first timing constraint requiring the first subset of the tasks to have completion times within a first time frame, and the second time constraint requiring the second subset of the tasks to have completion times within a second time frame.” This limitation recites the well-understood, routine, and conventional activity of storing or retrieving information in memory. MPEP § 2106.05(d)(II); Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015).
Claim 3
Step 1: A process, as above.
Step 2A Prong 1: The claim recites the same judicial exceptions as in claim 2.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. The claim further recites that “the tasks are performed in a streaming manner in the neural processor such that performance of least one of the tasks corresponding to a first partition in the first tensor and performance of at least one of the tasks corresponding to a second partition in the second tensor partially overlap with each other.” This amounts to a mere instruction to apply the judicial exception using a generic computer. MPEP § 2106.05(f).
Step 2B: The claim does not contain significantly more than the judicial exception. The claim further recites that “the tasks are performed in a streaming manner in the neural processor such that performance of least one of the tasks corresponding to a first partition in the first tensor and performance of at least one of the tasks corresponding to a second partition in the second tensor partially overlap with each other.” This amounts to a mere instruction to apply the judicial exception using a generic computer. MPEP § 2106.05(f).
Claim 4
Step 1: A process, as above.
Step 2A Prong 1: The claim recites the same judicial exceptions as in claim 2.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. The claim further recites “releasing the first portion of the memory after an end of the first time frame when the first subset of the tasks is completed, and releasing the second portion of the memory after an end of the second time frame when the second subset of the tasks is completed.” This limitation recites the insignificant extra-solution activity of mere data gathering and output. MPEP § 2106.05(g).
Step 2B: The claim does not contain significantly more than the judicial exception. The claim further recites “releasing the first portion of the memory after an end of the first time frame when the first subset of the tasks are completed, and releasing the second portion of the memory after an end of the second time frame when the second subset of the tasks are completed.” This limitation recites the well-understood, routine, and conventional activity of storing and retrieving information in memory. MPEP § 2106.05(d)(II); Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015).
Claim 5
Step 1: A process, as above.
Step 2A Prong 1: The claim recites, inter alia:
Step 2A Prong 2: This judicial exception is not integrated into a practical application. The claim further recites “adjusting a number of partitions in each of the tasks according to a hardware configuration of the neural processor.” This limitation recites the insignificant extra-solution activity of mere data gathering and output. MPEP § 2106.05(g).
Step 2B: The claim does not contain significantly more than the judicial exception. The claim further recites “adjusting a number of partitions in each of the tasks according to a hardware configuration of the neural processor.” This limitation recites the well-understood, routine, and conventional activity of storing or retrieving information in memory. MPEP § 2106.05(d)(II); Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015).
Claim 6
Step 1: A process, as above.
Step 2A Prong 1: The claim recites, inter alia:
Step 2A Prong 2: This judicial exception is not integrated into a practical application. The claim further recites that the “hardware configuration is associated with a size of a memory of the neural processor.” The adjustment of the number of partitions remains insignificant extra-solution activity under these further assumptions.
Step 2B: The claim does not contain significantly more than the judicial exception. The claim further recites that the “hardware configuration is associated with a size of a memory of the neural processor.” The adjustment of the number of partitions remains well-understood, routine, and conventional activity under these further assumptions for the reasons given in the rejection of claim 5.
Claim 7
Step 1: A process, as above.
Step 2A Prong 1: The claim recites, inter alia, “coalescing two or more of the tasks to generate updated tasks; determining dependencies of the updated tasks; and generating a second task schedule of the updated tasks that satisfies the dependencies of the updated tasks.” These limitations could encompass mentally combining two or more tasks, mentally determining the associated task dependencies, and mentally generating a second task schedule satisfying these dependencies.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. See claim 5 analysis.
Step 2B: The claim does not contain significantly more than the judicial exception. See claim 5 analysis.
Claim 8
Step 1: A process, as above.
Step 2A Prong 1: The claim recites:
[D]etermining a first value of a metric indicating hardware performance when the first task schedule is implemented: This limitation could encompass mentally determining the metric by observing the outputs of the hardware.
[D]etermining a second value of the metric indicating hardware performance when the second task schedule is implemented: This limitation could encompass mentally determining the metric by observing the outputs of the hardware.
[C]omparing the first value and the second value to determine whether the first task schedule or the second task schedule yields a higher hardware performance: This limitation could encompass mentally comparing the two values and mentally determining that one or the other task schedule yields a higher performance.
[C]hoosing one of the first task schedule or the second task schedule that yields the higher hardware performance for operating the neural processor: This limitation could encompass mentally selecting the schedule that yields the higher performance.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. See claim 7 analysis.
Step 2B: The claim does not contain significantly more than the judicial exception. See claim 7 analysis.
Claim 9
Step 1: A process, as above.
Step 2A Prong 1: The claim recites that “the metric indicates a footprint of a portion of the memory utilized for performing the tasks by the neural processor.” Determining values of the metric remains mentally performable under these further limitations.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. See claim 8 analysis.
Step 2B: The claim does not contain significantly more than the judicial exception. See claim 8 analysis.
Claim 10
Step 1: A process, as above.
Step 2A Prong 1: The claim recites the same judicial exceptions as in claim 1.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. The claim further recites “configuring the neural processor to read units of the first tensor or the second tensor of a predetermined size in the raster scan fashion, each of the partitions including a same number of consecutive elements.” This limitation recites the insignificant extra-solution activity of mere data gathering and output. MPEP § 2106.05(g).
Step 2B: The claim does not contain significantly more than the judicial exception. The claim further recites “configuring the neural processor to read units of the first tensor or the second tensor of a predetermined size in a raster scan fashion, each of the partitions including a same number of consecutive elements.” This limitation recites the well-understood, routine, and conventional activity of storing and retrieving information in memory. MPEP § 2106.05(d)(II); Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015).
Claim 11
Step 1: A process, as above.
Step 2A Prong 1: The claim recites “generating a dependency graph representing the dependencies of the tasks corresponding to the plurality of partitions.” This limitation could encompass mentally generating the dependency graph or generating it using a pen and paper.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. See claim 1 analysis.
Step 2B: The claim does not contain significantly more than the judicial exception. See claim 1 analysis.
Claims 12-19
Step 1: The claims recite a non-transitory storage medium; therefore, they are directed to the statutory category of articles of manufacture.
Step 2A Prong 1: The claims recite the same judicial exceptions as in claims 1-4, 6-8, and 10, respectively.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. The analysis at this step mirrors that of claims 1-4, 6-8, and 10, respectively, except insofar as these claims are directed to a “non-transitory storage medium storing instruction[s] thereon, the instructions when executed by a processor caus[ing] the processor to [perform the method]”. However, this is a mere instruction to apply the judicial exception using a generic computer. MPEP § 2106.05(f).
Step 2B: The claim does not contain significantly more than the judicial exception. The analysis at this step mirrors that of claims 1-4, 6-8, and 10, respectively, except insofar as these claims are directed to a “non-transitory storage medium storing instruction[s] thereon, the instructions when executed by a processor caus[ing] the processor to [perform the method]”. However, this is a mere instruction to apply the judicial exception using a generic computer. MPEP § 2106.05(f).1
Claim 20
Step 1: The claim recites an electronic device comprising a system memory and a neural processor circuit; therefore, it is directed to the statutory category of machines.
Step 2A Prong 1: The claim recites the same judicial exceptions as in claim 1.
Step 2A Prong 2: This judicial exception is not integrated into a practical application. The analysis at this step is the same as in claim 1, with the exception that this claim is directed to an “electronic device, comprising: a system memory; a neural processor circuit coupled to the system memory, the neural processor circuit including a memory; and a system processor configured to [perform the method]”. However, this is a mere instruction to apply the judicial exception using a generic computer. MPEP § 2106.05(f).
Step 2B: The claim does not contain significantly more than the judicial exception. The analysis at this step is the same as in claim 1, with the exception that this claim is directed to an “electronic device, comprising: a system memory; a neural processor circuit coupled to the system memory, the neural processor circuit including a memory; and a system processor configured to [perform the method]”. However, this is a mere instruction to apply the judicial exception using a generic computer. MPEP § 2106.05(f).
Claim Rejections - 35 USC § 103
Claims 1-2, 5-7, 10-13, 16-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Bokam et al. (US 20210191765) (“Bokam”) in view of Kurihara et al. (US 9507633) (“Kurihara”) and further in view of Zhang et al. (US 20220191524) (“Zhang”).
Regarding claim 1, Bokam discloses “[a] method for compiling neural network operations associated with a neural network, comprising:
determining spatial segmentation of a first tensor of a first layer of a neural network and a second tensor associated with a second layer of the neural network, the spatial segmentation dividing the first tensor and the second tensor into a plurality of partitions …, the second tensor of the second layer being derived based on [an] output tensor generated by performing convolution on the first tensor of the first layer that is a lower layer in a hierarchy of the neural network by a neural processor (system can partition [spatially segment] the input tensor and the weight tensor of a layer based on the input tensor dimensions and the weight tensor dimensions and the properties of the processor – Bokam, paragraph 54; system can access register dimensions of the processor in order to calculate valid partition sizes for input, weight, and output tensors of each layer of the network [i.e., there are multiple layers arranged in a hierarchy] – id. at paragraph 36; see also Fig. 1 (depicting a CNN with a series of convolutional layers, the output of each layer being the input to the next layer, i.e., the tensor for the second layer is generated based on the convolutional output of a tensor input to the previous layer));
determining, by a processor, dependencies of tasks, each of the tasks corresponding to one or more of the plurality of partitions (upon accessing the properties of the processor and the structure of the network, the system can generate partitions of the input tensor – Bokum, paragraph 21; upon generating the partitions, the system can define a set of operations to execute each layer computation, and the system can then organize the set of operations into a DAG defining dependencies between each operation in the set of operations [i.e., the operations are determined based on the partitions] – id. at paragraphs 22-23); [and]
generating, by the processor, a first task schedule of the tasks that satisfies the dependencies of the tasks (upon generating a graph [containing the dependencies, see mapping of previous limitation] representing execution of a layer of the network on the multicore processor, the system can convert this graph into a schedule assigning each of the operations [tasks] represented by nodes of the graph to individual compute resources – Bokum, paragraph 77) ….”
Bokum appears not to disclose explicitly the further limitations of the claim. However, Kurihara discloses “allocating, by the processor, a first subset of the tasks, that have completion times at the … processor satisfying a first timing constraint, to a same first portion of a memory in the … processor for storage (if Tm and Ts are access end [completion] times at the time of allocation to the main storage and the sub-storage, respectively, if Tm > Ts [first timing constraint] is satisfied, an instruction is given to write the write tasks to the sub-storage [portion of memory], and if Tm < Ts is satisfied, an instruction is given to write the write tasks into the main storage – Kurihara, col. 5, l. 54-col. 6, l. 13).”
Kurihara and the instant application both relate to computing task scheduling and are analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bokum to allocate all tasks that have the same completion time to the same portion of memory, as disclosed by Kurihara, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would prevent access contention for memory shared by multiple processors. See Kurihara, col. 1, ll. 12-14.
Neither Bokum nor Kurihara appears to disclose explicitly the further limitations of the claim. However, Zhang discloses that the “partitions [are] derived in a raster scan fashion, wherein a first partition comprises a number of consecutive elements in a first row, and a second partition comprises the number of consecutive elements in a second row arranged in a zigzagged manner with respect to the first partition (input tensor is partitioned into non-overlapping blocks, and the blocks are processed in a raster scan order – Zhang, paragraph 91; see also Fig. 6 (showing that the blocks/partitions 604-1 through 604-9 are arranged in a zigzag fashion with respect to one another, e.g., 604-4 [second partition] in the second row, left-hand column is zigzagged with respect to 604-3 [first partition] in the first row, right-hand column)) ….”
Zhang and the instant application both relate to partitioning input tensors for machine learning and are analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Bokum and Kurihara to derive the partitions in raster scan/zigzagged fashion, as disclosed by Zhang, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would ensure that the system does not miss any entries of the tensors by reading them in a systematic fashion. See Zhang, paragraph 84.
Claim 12 is a non-transitory storage medium claim corresponding to method claim 1 and is rejected for the same reasons as given in the rejection of that claim. Similarly, claim 20 is a non-transitory storage medium claim corresponding to method claim 1 and is rejected for the same reasons as given in the rejection of that claim, with the exception that claim 20 additionally recites the following elements, all of which are disclosed by Bokam: “a system memory (Bokam Fig. 1 discloses a main memory [system memory]);
a neural processor circuit coupled to the system memory, the neural processor circuit including a memory (Bokam paragraph 17 and Fig. 1 disclose an artificial neural network that is executed on a multicore processor including CPU cores and GPU cores [neural processor circuit] that are connected to main memory; paragraph 27 discloses that the multicore processor includes a set of primary caches for each processor core of the multicore processor [memory included in the neural processor circuit]); and
a system processor (Bokam paragraph 17 and Fig. 1 disclose an artificial neural network that is executed on a multicore processor including CPU cores [system processor] and GPU cores that are connected to main memory) ….”
Regarding claim 2, Bokam, as modified by Kurihara/Zhang, discloses that “generating the first task schedule of the tasks further includes allocating a second subset of the tasks satisfying a second time constraint associated with completion times of the second subset of the tasks at the neural processor to a same second portion of the memory in the neural processor for storage, the first timing constraint requiring the first subset of the tasks to have completion times within a first time frame, and the second time constraint requiring the second subset of the tasks to have completion times within a second time frame (if Tm and Ts are access end [completion] times at the time of allocation to the main storage and the sub-storage, respectively, if Tm > Ts [first timing constraint; first time frame = time longer than Ts] is satisfied, an instruction is given to write the write tasks to the sub-storage [first portion of memory], and if Tm < Ts [second timing constraint; second time frame = time shorter than Ts] is satisfied, an instruction is given to write the write tasks into the main storage [second portion of memory] – Kurihara, col. 5, l. 54-col. 6, l. 13).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bokum to allocate all tasks that have the same completion time to the same portion of memory, as disclosed by Kurihara, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would prevent access contention for memory shared by multiple processors. See Kurihara, col. 1, ll. 12-14.
Claim 13 is a non-transitory storage medium claim corresponding to method claim 2 and is rejected for the same reasons as given in the rejection of that claim.
Regarding claim 5, Bokam, as modified by Kurihara/Zhang, discloses “adjusting a number of partitions in each of the tasks according to a hardware configuration of the neural processor (the system generates a static schedule for the network based on the particular hardware components and layout of the multicore processor – Bokam, paragraph 19; upon accessing the properties of the processor and the structure of the network to be executed on the processor, the system can generate partitions of the input tensor and the weights [i.e., the partitions, including their number, are generated based on the hardware configuration] – id. at paragraph 21).”
Regarding claim 6, Bokam, as modified by Kurihara/Zhang, discloses that “the hardware configuration is associated with a size of a memory of the neural processor (system can access register [memory] dimensions [size] of the processor in order to calculate valid partition sizes for the input tensors, weight tensors, and output tensors – Bokam, paragraph 36).”
Claim 16 is a non-transitory storage medium claim corresponding to method claim 6 and is rejected for the same reasons as given in the rejection of that claim.
Regarding claim 7, Bokam, as modified by Kurihara/Zhang, discloses that “adjusting the number of partitions in each of the tasks according to the hardware configuration of the neural processor includes:
coalescing two or more of the tasks to generate updated tasks (upon generating a schedule for each layer in the network, the system can aggregate these per-layer schedules [aggregated per-layer schedules = coalesced/updated tasks] into a complete schedule for the network– Bokam, paragraph 94);
determining dependencies of the updated tasks (system can modify the per-layer schedules during the aggregation step to coordinate the final memory location of the output tensor of a first layer with the initial memory location of the input tensor of the subsequent layer; ; thus, the system can retroactively modify the set of per-layer schedules [i.e., determine dependencies of the updated tasks] to improve transitions between layer executions – Bokam, paragraph 95; see also paragraph 16 (disclosing that the DAG that creates the schedule contains a set of edges representing dependencies between operations)); and
generating a second task schedule of the updated tasks that satisfies the dependencies of the updated tasks (upon generating a schedule for each layer in the network, the system can aggregate these per-layer schedules into a complete schedule [second schedule satisfying the dependencies] for the network– Bokam, paragraph 94)).”
Claim 17 is a non-transitory storage medium claim corresponding to method claim 7 and is rejected for the same reasons as given in the rejection of that claim.2
Regarding claim 10, neither Bokam nor Kurihara appears to disclose explicitly the further limitations of the claim. However, Zhang discloses that “determining the spatial segmenting of the first tensor and the second tensor into the plurality of partitions includes:
configuring the neural processor to read units of the first tensor or the second tensor of a predetermined size in the raster scan fashion (input tensor is partitioned into non-overlapping blocks; the blocks are processed one by one in a raster scan order – Zhang, paragraph 84), each of the partitions including a same number of consecutive elements (input tensor is partitioned into non-overlapping blocks; the size of the block may be determined by the memory in the computing device, for example, by the GPU memory – Zhang, paragraph 84; input tensor is partitioned into blocks of size 512 x 512 [i.e., all the same size] – id. at paragraph 106; see also Figs. 9A-B (showing that all the partitions have size H x W)).” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Bokam and Kurihara to read equally-sized partitions of the tensors in a raster scan order, as disclosed by Zhang, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would ensure that the system does not miss any entries of the tensors by reading them in a systematic fashion. See Zhang, paragraph 84.
Claim 19 is a non-transitory storage medium claim corresponding to method claim 10 and is rejected for the same reasons as given in the rejection of that claim.
Regarding claim 11, Bokam, as modified by Kurihara/Zhang, discloses that “determining the dependencies of the tasks comprises generating a dependency graph representing the dependencies of the tasks corresponding to the plurality of partitions (a selected graph representing execution of a layer by the multicore processor may be generated; the graph defines, inter alia, a set of edges representing dependencies between the set of compute operations and the set of data transfer operations – Bokam, paragraph 14).”
Claims 3 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Bokam in view of Kurihara and Zhang and further in view of Lai et al. (US 20210004208) (“Lai”).
Regarding claim 3, neither Bokum, Zhang, nor Kurihara appears to disclose explicitly the further limitations of the claim. However, Lai discloses that “the tasks are performed in a streaming manner in the neural processor such that performance of least one of the tasks corresponding to a first partition in the first tensor and performance of at least one of the tasks corresponding to a second partition in the second tensor partially overlap with each other (input to a processing element (PE) of a MAC circuit for a neural network can be part of an input stream [of tensors] that is read or accessed from a storage device; and input stream can be shared across one or more of the PEs or partitioned into overlapping data portions [MAC operation corresponding to first portion of input stream = task corresponding to first partition; MAC operation corresponding to second portion of input stream = task corresponding to second partition]; output of each PE can be routed directly out of the PE array – Lai, paragraph 45).”
Lai and the instant application both relate to hardware implementations of neural networks and are analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Bokum, Zhang, and Kurihara to divide the tasks into overlapping portions, as disclosed by Lai, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would ensure that no data point is left unconsidered by the system by creating redundancy in the tasks. See Lai, paragraph 45.
Claim 14 is a non-transitory storage medium claim corresponding to method claim 3 and is rejected for the same reasons as given in the rejection of that claim.
Claims 4 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Bokam in view of Kurihara and Zhang and further in view of Mody et al. (US 20230013998) (“Mody”).
Regarding claim 4, neither Bokam, Zhang, nor Kurihara appears to disclose explicitly the further limitations of the claim. However, Mody discloses “releasing the first portion of the memory after an end of the first time frame when the first subset of the tasks is completed (layer of ML model is run using static memory and a range of memory addresses; release request is transmitted to a shared memory to free the range of memory addresses after the layer of the ML model is run; this release may be transmitted before executing a next layer of the ML model [first subset of tasks = first layer execution; first portion of memory = range of memory addresses associated with first layer] – Mody, paragraph 72), and
releasing the second portion of the memory after an end of the second time frame when the second subset of the tasks is completed (layer of ML model is run using static memory and a range of memory addresses; release request is transmitted to a shared memory to free the range of memory addresses after the layer of the ML model is run; this release may be transmitted before executing a next layer of the ML model [second subset of tasks = second layer execution; fsecond portion of memory = range of memory addresses associated with second layer] – Mody, paragraph 72).”
Mody and the instant application both relate to memory management in machine learning and are analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Bokam, Zhang, and Kurihara to release a portion of the memory after the tasks associated therewith are completed, as disclosed by Mody, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would free up memory for other tasks, thereby reducing the system’s memory footprint relative to a system in which the memory is occupied indefinitely. See Mody, paragraph 72.
Claim 15 is a non-transitory storage medium claim corresponding to method claim 4 and is rejected for the same reasons as given in the rejection of that claim.
Claims 8-9 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Bokam in view of Kurihara and Zhang and further in view of Alfalo et al. (US 11526736) (“Alfalo”).
Regarding claim 8, neither Bokam, Zhang, nor Kurihara appears to disclose explicitly the further limitations of the claim. However, Alfalo discloses “determining a first value of a metric indicating hardware performance when the first task schedule is implemented (in response to at least one iteration of a layer map generator applying a particular combination of resources [hardware], a state definer updates state metrics of the mapping effort; state report contains actions most recently taken and corresponding results; reward determiner calculates a results metric based on measured performance metrics [e.g., a first value] and corresponding performance characteristic targets; such results metric data are used on a relative comparison basis to determine which resource assignments exhibit the relatively best performance as compared to the other resource assignments [first resource assignment = first task schedule] – Alfalo, col. 10, ll. 13-47);
determining a second value of the metric indicating hardware performance when the second task schedule is implemented (in response to at least one iteration of a layer map generator applying a particular combination of resources, a state definer updates state metrics of the mapping effort; state report contains actions most recently taken and corresponding results; reward determiner calculates a results metric based on measured performance metrics [e.g., a second value] and corresponding performance characteristic targets; such results metric data are used on a relative comparison basis to determine which resource assignments exhibit the relatively best performance as compared to the other resource assignments [second resource assignment = second task schedule] – Alfalo, col. 10, ll. 13-47);
comparing the first value and the second value to determine whether the first task schedule or the second task schedule yields a higher hardware performance (in response to at least one iteration of a layer map generator applying a particular combination of resources, a state definer updates state metrics of the mapping effort; state report contains actions most recently taken and corresponding results; reward determiner calculates a results metric based on measured performance metrics and corresponding performance characteristic targets; such results metric data are used on a relative comparison basis to determine which resource assignments exhibit the relatively best performance as compared to the other resource assignments [by comparing the performance values including the first and second values] – Alfalo, col. 10, ll. 13-47); and
choosing one of the first task schedule or the second task schedule that yields the higher hardware performance for operating the neural processor (in response to at least one iteration of a layer map generator applying a particular combination of resources, a state definer updates state metrics of the mapping effort; state report contains actions most recently taken and corresponding results; reward determiner calculates a results metric based on measured performance metrics and corresponding performance characteristic targets; such results metric data are used on a relative comparison basis to determine which resource assignments exhibit the relatively best performance as compared to the other resource assignments; reward determiner generates an iteration decision [choice of task schedule] based on the results metric – Alfalo, col. 10, ll. 13-47).”
Alfalo and the instant application both relate to resource allocation for neural networks and are analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination of Bokam, Zhang, and Kurihara to compare hardware performance values to determine which resource assignments yield the best performance, as disclosed by Alfalo, and an ordinary artisan could reasonably expect to have done so successfully. Doing so would increase the efficiency of allocation of resources by ensuring that resources are allocated in a way that maximizes performance. See Alfalo, col. 10, ll. 13-47.
Claim 18 is a non-transitory storage medium claim corresponding to method claim 8 and is rejected for the same reasons as given in the rejection of that claim.3
Regarding claim 9, Bokam, as modified by Kurihara, Zhang, and Alfalo, discloses that “the metric indicates a footprint of a portion of the memory utilized for performing the tasks by the neural processor (system can access register [portion of memory] dimensions [footprint] of the processor in order to calculate valid partition sizes for the input tensors, weight tensors, and output tensors – Bokam, paragraph 36).”
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RYAN C VAUGHN whose telephone number is (571)272-4849. The examiner can normally be reached M-R 7:00a-5:00p ET.
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/RYAN C VAUGHN/ Primary Examiner, Art Unit 2125
1 Note that, while there are certain claims in this claim set that have different dependency chains than their counterparts in the previous claim set, the underlying analysis remains the same.
2 The ground of rejection remains the same even though claim 17 is dependent on claim 16, which is equivalent to claim 6, on which claim 7 does not depend, because claims 6 and 16 were also rejected over the combination of Bokam and Kurihara. Therefore, the rejections of claims 6 and 7 apply, mutatis mutandis, to claim 17.
3 The ground of rejection remains the same notwithstanding the difference in dependency for the reasons given in footnote 2.
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