DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-3, 5-10, 21, 23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-8, 10, 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over McCarthy et al. (US2024/0179330) in view of Kadu et al. (US20230050950).
To claim 1, McCarthy teach an electronic device comprising:
an electronic display configured to display an image based at least in part on processed image data (paragraph 0164); and
image processing circuitry configured to process image data to generate the processed image data, the image processing circuitry comprising:
a circuitry configured to generate an offset for a pixel block in an image frame of the image (paragraphs 0046-0053, 0110, 0112, synthesizing film grain pattern thru generating pseudo-random values);
film grain fetch circuitry configured to receive a first film grain value corresponding to the offset (530-535 of Fig. 5A; paragraph 0112);
film grain combine circuitry configured to scale the first film grain value to produce a scaled first film grain value (540 of Fig. 5A; paragraphs 0112-0113); and to combine the scaled first film grain value with a value of the first pixel in an image frame of the image (545 of Fig. 5A; paragraph 0113).
But, McCarthy do not expressly disclose using a linear feedback shift register (LFSR) configured to generate an offset, wherein the offset corresponds to a pixel row number and a pixel column number of a first pixel; to add a film grain effect to the image displayed via the electronic display, the image being perceivable with the film grain effect.
Kadu teach using a linear feedback shift register based pseudo-random number generator to faster implementation in synthesizing film grain image (abstract, paragraphs 0088-0089), wherein said pseudo-random number generator is applied to respective pixel with column and row in input image (paragraphs 0083,0084, 0122, film grain value at a column C in row R… for each pixel in the row R, the pseudo random number module generates a new random number… seeded from a function of the row index and a random offset), to add a film grain effect to the image displayed via the electronic display, the image being perceivable with the film grain effect (paragraphs 0005, 0011-0012, 0147, 0156, synthesizing noises to reduce the effect of compression artifacts in displayed image, creating a synthesized noise image; wherein the decoder is configured to combine the synthesized noise image with the decoded clean sequence, creating a rendered image for display).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teaching of Kadu into the apparatus of McCarthy, in order to provide faster pseudo-random value generation.
To claim 21, McCarthy and Kadu teach image processing circuitry (as explained in response to claim 1 above).
To claim 2, McCarthy and Kadu teach claim 1.
McCarthy teach wherein the LFSR is configured to: generate the offset based at least in part on a pseudorandom seed for the first pixel, wherein the offset comprises coordinates of a film grain value in the first film grain template (paragraphs 0046, 0053, 0110, 0112, 0180, 0198, using pseudo-random generator to generate offsets for block inside film grain template).
To claim 3, McCarthy and Kadu teach claim 2.
McCarthy teach wherein the film grain fetch circuitry is configured to: identify the first film grain value in the first film grain template corresponding to an offset, wherein the offset is based at least in part on coordinates of the pixel in the image frame (paragraphs 0275-0307, obviously block location affects offset).
To claim 5, McCarthy and Kadu teach claim 1.
McCarthy teach wherein the image processing circuitry comprises: the film grain fetch circuitry configured to receive a second film grain value from a second film grain template; and the film grain combine circuitry configured to scale the second film grain value to produce a scaled second film grain value and add the scaled second film grain value to the value of a second pixel in the image frame (paragraph 0185, generated multiple film grain templates, which would be obvious to one of ordinary skill in the art that operation for processing a second grain template as it does to the first grain template).
To claim 6, McCarthy and Kadu teach claim 1.
McCarthy teach wherein the value comprises a luma value, a chroma value, or both (paragraphs 0054-0059, 0112).
To claim 7, McCarthy and Kadu teach claim 1.
McCarthy teach wherein the first film grain template comprises film grain values generated based at least in part on film grain parameters received from an encoder (122 of Fig. 1A; paragraphs 0023-0024).
To claim 8, McCarthy and Kadu teach claim 1.
McCarthy teach wherein the film grain combine circuitry is configured to scale the first film grain value based on using a look-up-table (LUT) to multiply the first film grain value by a scaling factor (paragraph 0113).
To claim 10, McCarthy and Kadu teach claim 1.
McCarthy teach wherein the film grain combine circuitry is configured to combine the scaled first film grain value with the value of the first pixel in the image frame of the image based on adding the first film grain value and the value of the first pixel (paragraph 0025, 0112).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over McCarthy et al. (US2024/0179330) in view of Kadu et al. (US20230050950) and Holland et al. (US2019/0073176).
To claim 9, McCarthy and Kadu teach claim 1.
But, McCarthy and Kadu do not expressly disclose wherein the image processing circuitry comprises memory-to-memory scaler and rotator (MSR) circuitry configured to perform scaling and rotation operations on the image data.
Holland teach the image processing circuitry comprises memory-to-memory scaler and rotator (MSR) circuitry configured to perform scaling and rotation operations on the image data (paragraphs 0029-0037), which would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate into the apparatus of McCarthy and Kadu for modification by design preference.
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over McCarthy et al. (US2024/0179330) in view of Kadu et al. (US20230050950), Sjoberg et al. (US2023/0016432) and Chen et al. (US2022/0051382).
To claim 23, McCarthy and Kadu teach claim 1.
But, McCarthy and Kadu do not expressly disclose wherein the image processing circuitry comprises: swizzle circuitry configured to: reorder a first configuration of one or more color channels of the image data corresponding to the first pixel to a second configuration of the one or more color channels of the image data, wherein the second configuration of the one or more color channels of the image data corresponds to the film grain combine circuitry; and provide the image data comprising the second configuration of the one or more color channels to the film grain combine circuitry; and unswizzle circuitry configured to: receive the image data comprising the second configuration of the one or more color channels from the film grain combine circuitry; and reorder the second configuration of the one or more color channels of the image data to the first configuration of the one or more color channels of the image data.
However, McCarthy does teach modelling film grain on each color component (paragraph 0026, Table 1), for all 8×8 blocks in each color component, the block average is computed and compared with intensity intervals to select the film grain component values to be used for the 8×8 block (paragraph 0050), obtain values of the scaling function, the following procedure is invoked with the color plane index cIdx and the input value pointVal as inputs (paragraph 0094)
Sjoberg teach a film grain process to generate an output picture by applying generated film grain to the current picture (abstract), wherein a linear-feedback shift register (LFSR) is applied to add a film grain effect to the image displayed via the electronic display, the image being perceivable with the film grain effect (1042 of Fig. 10; paragraphs 0117, 0183, 0203, 0239), wherein the output process may output an output picture that is modified version of the decoded picture that may have been modified in a number of different ways, such as one of the following or a combination of two or more of the following: 1. Apply film grain; 2. Apply a color transform and/or color component value scaling; 3. Apply a projection mapping or inverse projection mapping such as converting the decoded picture from a cube map projection to a spherical representation or to an equirectangular representation; 4. Perform a region-wise packing or region-wise unpacking of the picture by a set of region-wise operations such as repositioning, scaling and rotation; 5. Crop the decoded picture; 6. Convert the decoded picture to a different color format such as from Rec 709 to PQ; 7. Convert the decoded picture to a different chroma format such as from YUV 4:2:0 to YUV 4:4:4; 8. Scale or resample the picture from a decoded resolution to an output resolution; 9. Convert to a different sample aspect ratio; 10. Convert two decoded fields to an interlaced picture; 11. Apply/remove frame packing; 12. Extracting one or more subpictures (similar to cropping the decoded picture but may for instance comprise merging subpictures from different locations in the picture; 13. Apply post filtering such as deblocking filtering, anti-banding filtering, anti-aliasing filtering, sharpening filtering and blurriness filtering; and 14. Apply overlays such as timed text, logos, and sport graphics (paragraphs 0077-0091, which shows color swizzling to be obviously combined with film grain processing).
In furthering obvious combination of Sjoberg, Chen teach image processing having swizzle engine (140 of Fig. 1, 260 inside of 140 of Fig. 2; paragraphs 0112, 0123) processed output inputted into perceptual quality model (178 of Fig. 1) for possible film grain noise combination (paragraph 0042).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate teachings of Sjoberg and Chen into the apparatus of McCarthy and Kadu, in order to further preferential output effect by design preference.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHIYU LU whose telephone number is (571)272-2837. The examiner can normally be reached Weekdays: 8:30AM - 5:00PM.
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ZHIYU . LU
Primary Examiner
Art Unit 2669
/ZHIYU LU/Primary Examiner, Art Unit 2665 January 12, 2026