DETAILED ACTION
Claims 1, 3-11, 13-17, and 19-20 are pending.
The office acknowledges the following papers:
Claims and remarks filed on 1/7/2026.
Allowable Subject Matter
Claims 11, 13-17, and 19-20 are allowed.
Maintained Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Scott et al. (U.S. 2015/0301829), in view of Kranich et al. (U.S. 6,651,163), in view of Alexander et al. (U.S. 2004/0215720).
As per claim 1:
Scott and Kranich disclosed a computing device, comprising:
a processor having a first branch target buffer and a second branch target buffer (Scott: Figures 1 and 4 elements 28-30, 62, and 66, paragraphs 11-12, 15-16, and 23)(The CPU includes a first and second BTB used by multiple threads.);
wherein the processor is configured to:
store first branch prediction information in the first branch target buffer (Scott: Figure 4 elements 66-68, paragraph 23)(Thread 1 branch prediction information is stored only in BTB1 (i.e. first BTB) when both threads are enabled or when no BTB sharing is enabled while thread 0 is disabled.);
perform a first branch prediction, during execution of a set of instructions, using the first branch prediction information stored in the first branch target buffer (Scott: Figures 1 and 4-5 elements 28-30, 66-68, and 82-86, paragraphs 15, 20, 23, and 28)(Branch instruction addresses are sent to the BTBs for branch prediction purposes.);
allocate, in response to the set of instructions being executed to call to a subroutine (Kranich: Figure 3B element 334, column 10 lines 56-67 and column 12 lines 1-14, table 1)(Scott: Paragraph 18)(Kranich disclosed a single thread including fork instructions (i.e. call to subroutine) that create a new thread of execution at a target address. The combination allows for the threads of Scott to include fork instructions.), the second branch target buffer for execution of the subroutine (Kranich: Figure 3B element 334, column 10 lines 56-67 and column 12 lines 1-14, table 1)(Scott: Figure 4 element 62, paragraphs 23 and 25)(Kranich disclosed a single thread including fork instructions (i.e. call to subroutine) that creates a new thread of execution at a target address. The combination allows for the threads of Scott to include fork instructions. Enabling a second thread in Scott allocates the shared or non-used BTB to the second thread for private use.);
store second branch prediction information (Kranich: Figure 3B element 338, column 10 line 67 continued to column 11 lines 1-2 and column 12 lines 3-10)(Scott: Figures 2 and 4-5 elements 48, 52, 62-64, and 100, paragraphs 16, 18, 23, and 31)(The combination allows for the threads of Scott to include fork instructions to create new threads of execution. Execution of the new second thread in Scott allows for population of the private BTB.); and
perform a second branch prediction, during the execution of the subroutine, using the second branch prediction information stored in the second branch target buffer (Kranich: Figure 3B element 338, column 10 line 67 continued to column 11 lines 1-2 and column 12 lines 3-14)(Scott: Figures 1 and 4-5 elements 28-30, 66-68, and 82-86, paragraphs 15, 20, 23, and 28)(The combination allows for the threads of Scott to include fork instructions to create new threads of execution. Branch instruction addresses for the new second thread are sent to the second private BTB for branch prediction purposes.);
in response to execution of the set of instructions returning from execution of the subroutine, perform branch prediction during further execution of the set of instructions using the first branch prediction information stored in the first branch target buffer (Kranich: Figure 3B elements 338-346, column 10 lines 56-67 continued to column 11 lines 1-16 and column 12 lines 3-14)(Scott: Figure 4 elements 66-68, paragraph 23)(The combination allows for the threads of Scott to include fork instructions to create new threads of execution. The combination allows for created threads to include join instructions to combine the multiple threads to a single thread of execution. Thread 1 branch prediction information is stored only in BTB1 (i.e. first BTB) when both threads are enabled or when no BTB sharing is enabled while thread 0 is disabled. Thus, upon return from multithreading, branch prediction is performed using solely BTB1 (i.e. first BTB) when no BTB sharing is enabled.).
The advantage of including fork instructions in thread code is that multiple threads of code can be created to allow for parallel execution and/or the hiding of execution latency. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the fork instruction of Kranich in the processor of Scott for the advantage of increased processor performance from execution of multiple threads at once.
Scott and Kranich failed to teach wherein the processor is further configured to block the execution of the subroutine from accessing the first branch prediction information stored in the first branch target buffer.
However, Alexander combined with Scott and Kranich disclosed wherein the processor is further configured to block the execution of the subroutine from accessing the first branch prediction information stored in the first branch target buffer (Alexander: Figure 3B element 316, paragraph 36)(Scott: Figure 4 elements 62 and 66, paragraph 23)(Scott disclosed when both threads are enabled, that each BTB is a private BTB for a corresponding thread and only allocates branch entries for the corresponding thread. Scott doesn’t explicitly state that access is limited only to the corresponding thread of the private BTB. Alexander disclosed that an active thread can only access its corresponding count cache component. The combination allows for enabled threads 0/1 to only access their corresponding BTB0/1 for branch prediction.).
The advantage of only allowing threads to access their corresponding BTB components is that false positives and branch mispredictions can be reduced, as well as power consumption. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the access method of Alexander in the processor of Scott to limit access to private thread BTBs to only their corresponding thread.
As per claim 3:
Scott, Kranich, and Alexander disclosed the computing device of claim 1, wherein the processor is further configured to block the execution of the subroutine from accessing the first branch prediction information stored in the first branch target buffer (Alexander: Figure 3B element 316, paragraph 36)(Scott: Figure 4 elements 62 and 66, paragraph 23)(Scott disclosed when both threads are enabled, that each BTB is a private BTB for a corresponding thread and only allocates branch entries for the corresponding thread. Scott doesn’t explicitly state that access is limited only to the corresponding thread of the private BTB. Alexander disclosed that an active thread can only access its corresponding count cache component. The combination allows for enabled threads 0/1 to only access their corresponding BTB0/1.).
As per claim 7:
Scott, Kranich, and Alexander disclosed the computing device of claim 1, wherein the processor is further configured to prevent the execution of the subroutine from accessing a plurality of branch target buffers other than the second branch target buffer (Alexander: Figure 3B element 316, paragraph 36)(Scott: Figure 4 elements 62 and 66, paragraph 23)(Scott disclosed when both threads are enabled, that each BTB is a private BTB for a corresponding thread and only allocates branch entries for the corresponding thread. Scott doesn’t explicitly state that access is limited only to the corresponding thread of the private BTB. Alexander disclosed that an active thread can only access its corresponding count cache component. The combination allows for enabled threads 0/1 to only access their corresponding BTB0/1.).
As per claim 8:
Scott, Kranich, and Alexander disclosed the computing device of claim 1, wherein the processor is further configured to prevent the execution of the set of instructions from accessing a plurality of branch target buffers other than the first branch target buffer (Alexander: Figure 3B element 316, paragraph 36)(Scott: Figure 4 elements 62 and 66, paragraph 23)(Scott disclosed when both threads are enabled, that each BTB is a private BTB for a corresponding thread and only allocates branch entries for the corresponding thread. Scott doesn’t explicitly state that access is limited only to the corresponding thread of the private BTB. Alexander disclosed that an active thread can only access its corresponding count cache component. The combination allows for enabled threads 0/1 to only access their corresponding BTB0/1.).
Claims 4-6 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Scott et al. (U.S. 2015/0301829), in view of Kranich et al. (U.S. 6,651,163), in view of Alexander et al. (U.S. 2004/0215720), further in view of Official Notice.
As per claim 4:
Scott, Kranich, and Alexander disclosed the computing device of claim 1, wherein the processor is further configured to clear the second branch target buffer before the execution of the subroutine (Kranich: Figure 3B element 334, column 10 lines 56-67 and column 12 lines 1-14, table 1)(Scott: Figure 4 elements 62 and 66, paragraph 23)(Kranich disclosed a single thread including fork instructions (i.e. call to subroutine) that create a new thread of execution at a target address. The combination allows for the threads of Scott to include fork instructions. Official notice is given that thread switching can clear processor buffers for the advantage of ensuring old thread processor state isn’t incorrectly used by the new thread. Thus, it would have been obvious to one of ordinary skill in the art to implement clearing the BTB upon calling a new thread or returning from a current thread.).
As per claim 5:
Scott, Kranich, and Alexander disclosed the computing device of claim 1, wherein the processor is further configured to clear the second branch target buffer after returning from the subroutine and before the second branch target buffer is used for execution of a third subroutine called from the set of instructions (Kranich: Figure 3B element 334, column 10 lines 56-67 and column 12 lines 1-14, table 1)(Scott: Figure 4 elements 62 and 66, paragraph 23)(Kranich disclosed a single thread including fork instructions (i.e. call to subroutine) that create a new thread of execution at a target address. The combination allows for the threads of Scott to include fork instructions. Official notice is given that thread switching can clear processor buffers for the advantage of ensuring old thread processor state isn’t incorrectly used by the new thread. Thus, it would have been obvious to one of ordinary skill in the art to implement clearing the BTB upon calling a new thread or returning from a current thread.).
As per claim 6:
Scott, Kranich, and Alexander disclosed the computing device of claim 5, wherein the set of instructions is one of:
a subroutine; and
a main routine of a program (Kranich: Figure 3B element 330, column 10 lines 56-67)(Scott: Paragraph 18)(Kranich disclosed a single thread (i.e. main routine) including fork instructions that create a new thread of execution at a target address. The combination allows for the threads of Scott to include fork instructions.).
As per claim 9:
Scott, Kranich, and Alexander disclosed the computing device of claim 1, wherein the processor is further configured to clear the second branch target after or upon returning from the subroutine to the set of instructions (Kranich: Figure 3B element 334, column 10 lines 56-67 and column 12 lines 1-14, table 1)(Scott: Figure 4 elements 62 and 66, paragraph 23)(Kranich disclosed a single thread including fork instructions (i.e. call to subroutine) that create a new thread of execution at a target address. The combination allows for the threads of Scott to include fork instructions. Official notice is given that thread switching can clear processor buffers for the advantage of ensuring old thread processor state isn’t incorrectly used by the new thread. Thus, it would have been obvious to one of ordinary skill in the art to implement clearing the BTB upon calling a new thread or returning from a current thread.).
As per claim 10:
Scott, Kranich, and Alexander disclosed the computing device of claim 1, wherein when the second branch target buffer is in use at a time of the subroutine being called by the execution of the set of instructions, the processor is further configured to select and clear the second branch target buffer for allocation to the execution of the subroutine (Kranich: Figure 3B element 334, column 10 lines 56-67 and column 12 lines 1-14, table 1)(Scott: Figure 4 elements 62 and 66, paragraph 23)(Kranich disclosed a single thread including fork instructions (i.e. call to subroutine) that create a new thread of execution at a target address. The combination allows for the threads of Scott to include fork instructions. Official notice is given that thread switching can clear processor buffers for the advantage of ensuring old thread processor state isn’t incorrectly used by the new thread. Thus, it would have been obvious to one of ordinary skill in the art to implement clearing the BTB upon calling a new thread or returning from a current thread.).
Response to Arguments
The arguments presented by Applicant in the response, received on 1/7/2026 are not considered persuasive.
Applicant argues for claim 1:
“Scott discloses the allocation of different branch target buffers (BTB) to different threads. Although two threads may be generated from a single thread via a fork instruction (e.g., as in Kranich), such a fork instruction is seen an instruction to duplicate the current thread and thus not an instruction to call another routine. At the time of a fork instruction, the single thread is duplicated; and the duplicated threads are configured to execute the same instruction. Subsequently, different conditions to be evaluated by the duplicated threads separately can lead to different paths of executions. To execute a routine, a call instruction would be used in a thread. Thus, a fork instruction is not a call instruction. It is possible to use a fork instruction to generate two duplicated threads to perform the same computations, at least for the execution of a number of instructions, without calling a routine. Further, Scott and Kranich do not disclose and/or suggest how such forking is to be handled in the allocation and use of branch target buffers (BTB). Thus, no combination of Scott and Kranich would lead to the feature of “wherein the processor is further configured to block the execution of the subroutine from accessing the first branch prediction information stored in the first branch target buffer” as amened in claim 1. No combination of Scott and Kranich would lead to the feature of “in response to returning from the respective routine to a calling routine that calls the respective routine, de-allocating the respective branch target buffer” as amended in claim 11. And, no combination of Scott and Kranich would lead to the feature of “wherein the processor is further configured to clear the second branch target buffer upon completing execution of the second routine” as amended in claim 17.
Alexander is insufficient to cure the deficiencies of Scott and Kranich. Thus, the pending claims are seen patentable.”
This argument is found to be persuasive for the following reason. The examiner agrees that Scott and Kranich failed to teach the previous newly claimed limitation. The previously rejected limitation instead relied upon a combination of Scott, Kranich, and Alexander to reject the limitation. Alexander disclosed that an active thread can only access its corresponding count cache component. The combination allows for enabled threads 0/1 to only access their corresponding BTB0/1 for branch prediction. Thus, reading upon the claimed limitation.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB PETRANEK/Primary Examiner, Art Unit 2183