DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1 – 8, 10 – 18, 20, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Tsirkin (US Publication Number 2024/0086219) in view of Serebrin et al. (US Patent Number 9,594,704, hereinafter “Serebrin”).
4. As per claims 1, 11, and 20, Tsirkin teaches method, apparatus, and medium comprising: a memory (504, figure 5) to store an instrumented program (instrumented program being the guest software 112 in the virtual machine 106 running on the processor, figures 1 and 5, paragraph 21) having an interrupt instruction (memory location associated with a destination processor to handle the instrumented program reference via a pointer, paragraph 20); and a processor (source processing unit, 102, figures 1 and 5), the processor to execute the interrupt instruction (102 will handle the interrupt 122, figure 2, paragraphs 22 and 35), the interrupt instruction having an interrupt number (the interrupt number 204a, figure 2, which list interrupts 1…4); search for the interrupt number (processor searches for the interrupt in the interrupt tables 114, figures 2 and 5); and in response to the interrupt number being found (each entry correlated to an interrupt in the table, paragraph 19), save an address of a next instruction of the instrumented program after the interrupt instruction as a return address (next instruction for CPU processing, columns 204b and 204c), determine an address (the interrupt table maps interrupts triggered by 112 to destinations assigned to handle interrupt, paragraph 18), in an interrupt destination (interrupt destination table 120, figure 3, paragraph 23), of a beginning of an instrumentation handler program (interrupt handle program is 118a…n which is associated with Handler0…3, 304b, figure 3) associated with the interrupt number (the interrupt entry maps interrupt to the handler and pointer associated therein, paragraph 23) and transfer control of the instrumented program to the instrumentation handler program at the address (upon mapping to the handler the control is transferred from the source to the destination processing unit, paragraph 24, interrupt is seen from 106 to 116, figure 5, paragraphs 33 – 35).
Tsirkin does not appear to explicitly disclose search for the interrupt number in an interrupt register; and in response to the interrupt number being found in the interrupt register, determine an address, in an interrupt destination register.
However, Serebrin discloses search for the interrupt number in an interrupt register; and in response to the interrupt number being found in the interrupt register, determine an address, in an interrupt destination register (interrupt register 108/208, figures 1 and 2, column 2 – line 43 to column 3, line 20).
Tsirkin and Serebrin are analogous art because they are from the same field of endeavor of interrupt handling.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Tsirkin and Serebrin before him or her, to modify the interrupt mechanism of Tsirkin to include the interrupt handling of Serebrin because it would enhance multi-source interrupt detection.
One of ordinary skill would be motivated to make such modification in order to enhance interrupt processing (column 1, lines 26 – 41). Therefore, it would have been obvious to combine Serebrin with Tsirkin to obtain the invention as specified in the instant claims.
5. Tsirkin modified by the teachings of Serebrin as seen in claim 1 above, as per claims 2 and 12, Tsirkin teaches a method and apparatus, wherein the instrumentation handler program has a same privilege level as the instrumented program (privilege levels for interrupt handling may be the same for the processing elements, paragraph 24).
6. Tsirkin modified by the teachings of Serebrin as seen in claim 1 above, as per claims 3 and 13, Tsirkin teaches a method and apparatus, wherein the same privilege level is user mode (user space privilege for the interrupt which would be same as guest software, paragraph 17).
7. Tsirkin modified by the teachings of Serebrin as seen in claim 1 above, as per claims 4 and 14, Tsirkin teaches a method and apparatus, wherein the processor transfers control of the instrumented program to the instrumentation handler program without trapping into supervisor mode of an operating system (the supervisory program element is present however not required to handle the interrupt in the operating system, paragraphs 17 and 24, flow seen in figure 6 is without triggering and exit).
8. Tsirkin modified by the teachings of Serebrin as seen in claim 1 above, as per claims 5 and 15, Tsirkin teaches a method and apparatus, comprising storing the interrupt register in a runtime call interrupts register (register 110a…n, figure 1) in the processor (memory locations associated in the processor for storing the interrupt register, paragraph 17), the interrupt register to store a plurality of interrupt numbers (Serebrin: interrupt register 108/208, figures 1 and 2, column 2 – line 43 to column 3, line 20).
9. Tsirkin modified by the teachings of Serebrin as seen in claim 1 above, as per claims 6 and 16, Tsirkin teaches a method and apparatus, comprising storing the interrupt destination register in a runtime call register (registers 124 for each 118a…n, figure 1) in the processor, the interrupt destination register to store a plurality of addresses (interrupt table figure 3, destination address, paragraph 23, Serebrin: interrupt register 108/208, figures 1 and 2, column 2 – line 43 to column 3, line 20).
10. Tsirkin modified by the teachings of Serebrin as seen in claim 1 above, as per claims 7 and 17, Tsirkin teaches a method and apparatus, wherein an interrupt number in the interrupt register is associated with one destination address in the interrupt destination register (each interrupt 204a in figure 2 is associated with one address 204b in the table).
11. Tsirkin modified by the teachings of Serebrin as seen in claim 1 above, as per claims 8 and 18, Tsirkin teaches a method and apparatus, comprising storing the return address in a runtime call return destination register in the processor (registers 124 for each 118a…n, figure 1).
12. Tsirkin modified by the teachings of Serebrin as seen in claim 1 above, as per claims 10 and 22, Tsirkin teaches a method and medium, wherein the interrupt instruction comprises one of one byte and two bytes (single entries in the interrupt table, paragraph 39).
Allowable Subject Matter
13. Claims 9, 19, and 21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
14. Applicant’s arguments with respect to claims 1 – 22 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument in light of Serebrin.
Conclusion
15. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Goe/Hammer/Murty has teachings of interrupt register handling.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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AH
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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