Prosecution Insights
Last updated: May 29, 2026
Application No. 17/949,857

IC PACKAGE WITH LEDS

Non-Final OA §103
Filed
Sep 21, 2022
Examiner
YEUNG LOPEZ, FEIFEI
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
81%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
78%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
865 granted / 1067 resolved
+13.1% vs TC avg
Minimal -3% lift
Without
With
+-2.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
31 currently pending
Career history
1111
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
85.0%
+45.0% vs TC avg
§102
8.4%
-31.6% vs TC avg
§112
4.4%
-35.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1067 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on December 17, 2025. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wei et al (PG Pub 2021/00256893 A1) and Zhong et al (PG Pub 2023/0163115 A1). Regarding claim 1, Wei teaches an integrated circuit (IC) package, comprising: a substrate (430, fig. 4C); a micro light emitting diode (LED) (470, paragraph [0031]) positioned over the substrate; a semiconductor die (440); one or more through vias (TGVs) (432), wherein the one or more TGVs are integrated into the substrate and the one or more TGVs connect the micro LED to the semiconductor die (fig. 4C); a package substrate (410), wherein the semiconductor die is connected to the package substrate (fig. 4C). Wei does not teach the substrate to be glass but teaches it to be sapphire (paragraph [0056]). In the same field of endeavor, Zhong teaches using a glass substrate instead of sapphire reduces cost (paragraph [0022]). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make the substrate glass for the benefit of reducing cost. Regarding claim 5, Wei teaches the IC package of claim 1, wherein the semiconductor die includes processing logic (paragraph [0011]). Claim(s) 2 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wei et al (PG Pub 2021/00256893 A1) and Zhong et al (PG Pub 2023/0163115 A1) as applied to claim 1 above, and further in view of Shibata et al (PG Pub 2013/0221385 A1). Regarding claim 2, the previous combination remains as applied in claim 1. The previous combination does not teach the micro LED comprises: a plurality of nanowire cores. In the same field of endeavor, Shibata teaches an LED (2300, fig. 35A) comprises a plurality of nanowire cores (2202) positioned over the substrate (2201); one or more gallium nitride (GaN) shells (2203/2205, paragraph [0327]) positioned over the plurality of nanowire cores, for the benefit of providing an LED with increasing light emitting area (paragraph [0003]). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to make the micro LED to comprise: a plurality of nanowire cores positioned over the glass substrate; one or more gallium nitride (GaN) shells positioned over the plurality of nanowire cores, for the benefit of providing an LED with increasing light emitting area. Regarding claim 4, Shibata teaches the IC package of claim 2, wherein the LED further comprises a transparent metal electrode (ITO 2206, paragraph [0333]) over the one or more GaN shells. Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wei et al (PG Pub 2021/00256893 A1) and Zhong et al (PG Pub 2023/0163115 A1) as applied to claim 1 above, and further in view of Chang (PG Pub 2023/0230966 A1). Regarding claim 8, the previous combination remains as applied in claim 1. The previous combination does not an insulator formed over the package substrate, wherein the glass substrate is at least partially encased in the insulator. In the same field of endeavor, Chang teaches an insulator (16, paragraph [0060]) formed over the package substrate (15), wherein the substrate (10) is at least partially encased in the insulator, for the benefit of protecting the elements within the insulator (paragraph [0064]). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to include an insulator formed over the package substrate, wherein the glass substrate was at least partially encased in the insulator for the benefit of protecting the elements within the insulator. Claim(s) 9 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wei et al (PG Pub 2021/00256893 A1) and Zhong et al (PG Pub 2023/0163115 A1) as applied to claim 1 above, and further in view of Tao et al (PG Pub 2019/0088633 A1). Regarding claim 9, the previous combination remains as applied in claim 1. The previous combination does not teach a copper plate. In the same field of endeavor, Tao teaches a copper plate (copper pad at interface 306, fig. 3, paragraph [0026]), and an LED (below 306, fig. 3) is directly on the copper plate (figs. 3-6), for the benefit of providing strong bondage (paragraphs [0026][0046]). Wei in view of Tao teaches “the one or more TGVs and the micro LED are directly on” (the bottom of) “the copper plate and the one or more TGVs directly connect to the copper plate” (to connect LED to driver 302, fig. 3 of Tao; driver 440, fig. 4C of Wei). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to include a copper plate, wherein the one or more TGVs and the micro LED were directly on the copper plate and the one or more TGVs directly connected to the copper plate for the benefit of providing strong bondage. Regarding claim 10, Tao teaches the IC package of claim 9, wherein the copper plate is at least partially integrated into the substrate (fig. 3-6). Allowable Subject Matter Claims 3,6,7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Prior art does not teach “the plurality of nanocores comprise a silicon oxide in a glass solid state” (claim 3); “the semiconductor die includes components configured to convert light signals from the LED to electric signals for the processing logic” (claim 6); “the micro LED is a first micro LED and wherein the IC package comprises a second micro LED positioned over the glass substrate, wherein: the second micro LED is connected by the one or more TGVs to the semiconductor die; … and the second micro LED operates as a detector LED” (claim 7). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FEIFEI YEUNG LOPEZ whose telephone number is (571)270-1882. The examiner can normally be reached M-F: 8am to 4pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571 270 7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FEIFEI YEUNG LOPEZ/Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Sep 21, 2022
Application Filed
Jun 01, 2023
Response after Non-Final Action
Mar 04, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12635292
LIGHT EMITTING DEVICE AND PRODUCT INCLUDING SAME
3y 4m to grant Granted May 19, 2026
Patent 12635322
OPTOELECTRONIC SEMICONDUCTOR COMPONENT AND PRODUCTION METHOD
3y 3m to grant Granted May 19, 2026
Patent 12628378
SEMICONDUCTOR MANUFACTURING
2y 10m to grant Granted May 12, 2026
Patent 12628536
DISPLAY APPARATUS AND NEAR-EYE DISPLAY DEVICE
2y 6m to grant Granted May 12, 2026
Patent 12628481
DIODE ARRANGEMENT
2y 5m to grant Granted May 12, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
81%
Grant Probability
78%
With Interview (-2.9%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1067 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month