DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 03/30/2026 has been entered. As directed, claims 1-2, 4-5, 10, 12-13, 15-20,
and 22 have been amended, no claim is added or canceled. Thus claims 1-2, 4-13, 15-22 remain pending in the application. The applicant’s amendments to the claims have overcome each and every objection and rejection under 35 U.S.C 112(b) set forth in the Non-final Office Action mailed 12/29/2025. However, new rejection under 35 U.S.C 112(b) has been made in the current office action based on the amendment.
Response to Arguments
With respect to the Applicant’s argued 35 U.S.C. 103 in “Applicant Arguments/Remarks Made in an Amendment,”
Applicant argues:
…
The cited references do not teach or suggest "generating a layout shell structure by preprocessing a full-chip layout based on a two-dimensional polygon mesh representing the full- chip layout and assigning a virtual height to the two-dimensional polygon mesh .. .wherein the layout shell structure [has] a dimension which is greater than two dimensions and less than three dimensions" as recited in claim 1.
The office action rejects claim 1 over Ramoa, alleging that paragraph [0022] (reproduced below) discloses a "layout shell structure." Applicant submits that Ramoa does not teach or suggest a "layout shell structure" with dimensions greater than two and less than three based on an assigned virtual height.
[0022] The algorithm is prepared to write out finite element meshes based on the following FE types: (i) full 3D finite elements, using 3D tri- linear 8-node hexahedra elements to model both FR4 and copper layers; (ii) hybrid 30+2D finite elements, using 3D tri-linear 8-node hexahedra elements to model the FR4 layers and 2D bi-linear 4-node quadrilateral membrane elements to model the copper layers; (iii) thick-shell 2.5D finite elements, i.e. using only one layer of finite elements through- thickness to describe, in a single finite element (3D tri-linear 8-node hexahedron) all layers of both FR4 and copper; and (iV) 2D shell finite elements, using 2D bi-linear 4-node quadrilateral shell elements to model with a single shell element all layers of both FR4 and copper.
(Emphasis added)
Claim 1 requires "assigning a virtual height" to a "two-dimensional polygon mesh" representing "the full-chip layout." Ramoa is entirely devoid of any teaching or suggestion of assigning a "virtual height" to a polygon mesh.
While Ramoa mentions "thick-shell 2.5D finite elements," this label refers to a method of using a single layer of finite elements to represent multiple physical layers of a PCB. There is no discussion in Ramoa regarding the assignment of a "virtual height" to a mesh to derive its structure. Instead, Ramoa merely describes a single layer of elements that collapses the physical thickness of FR4 and copper into a single element. Consequently, Ramoa fails to teach the specific functional step of "assigning a virtual height" as required by claim 1.
Furthermore, Ramoa does not disclose a mesh with a dimensionality that is "greater than two dimensions and less than three dimensions based on the assigned virtual height." Ramoa's "2.5D" elements are described as representing "a single layer" of finite elements. This characterizes a model that effectively reduces a 3D physical structure to a 2D computational representation. In Ramoa, the "2.5D" elements are either standard 3D hexahedrons (which have three dimensions) or a simplified 2D representation of 3D layers. Neither of these configurations constitutes a dimensionality that is mathematically "greater than two dimensions and less than three dimensions" as a function of an "assigned virtual height." Because Ramoa merely collapses 3D data into a 2D or single-layer 3D representation, it does not meet the specific dimensionality limitations of the "layout shell structure" defined in claim 1.
During the Examiner Interview, the Examiner suggested that paragraphs [0026]-[0028] of Ramoa might teach the features of claim 1. These paragraphs are reproduced below:
[0026] It is disclosed a method for converting a printed circuit board, PCB, image description to a finite element model, said PCB comprising one or more conductive layers and one or more dielectric layers for insulation and support of the conductive layers, comprising the steps of:
generating in-plane with the PCB a 2D mesh of cells;
generating a stack of one or more finite elements from each 2D mesh cell, each said finite element corresponding to one or more PCB layers;
calculating the geometric and material features of each finite element of each said stack from the PCB image description of the PCB layers delimited by the outline of the respective 2D mesh cell;
outputting a finite element model comprising the nodes and connections of the calculated finite elements;
characterized in that
the 2D mesh of cells is delimited by the PCB shape from the PCB image description;
wherein said PCB shape comprises the border of the PCB and the hole or holes of the PCB, if present;
such that all finite element nodes are within the PCB shape.
[0027] A PCB hole can be a full hole (e.g. drilled) or a partial hole (e.g. a slot).
[0028] In an embodiment, each finite element is calculated having an inertia tensor defined by the largest conductive independent area of each corresponding conductive layer or layers delimited by the outline of the respective 2D mesh cell.
(Emphasis added)
These sections describe generating a standard 3D model through "stacks of finite elements." Each element in the stack corresponds to one or more physical PCB layers. This teaching is directed to a conventional 3D volumetric representation where multiple elements are stacked to account for thickness.
Nothing in these paragraphs suggests that the 2D mesh of cells is assigned a "virtual height" to create a structure with a dimensionality between two and three. In contrast to the claimed feature, Ramoa's model is a discrete 3D representation formed by stacking elements.
Ramoa's reliance on "stacks" to represent thickness confirms that it does not utilize the "virtual height" mechanism to achieve the specific "layout shell structure" dimensionality required by claim 1.
Thus, Ramoa does not teach or suggest at last one feature of claim 1.
Further, Ramoa does not teach or suggest "wherein the virtual height is determined based on the two-dimensional polygon mesh."
The "thick-shell 2.5D" discussed in Ramoa merely represents a modeling option aimed at improving computational efficiency by using three-dimensional hexahedral elements while reducing the number of elements in the thickness direction. In Ramoa, the thickness of the PCB is a physically given value, and there is no disclosure or suggestion that the thickness or height is determined based on the mesh structure.
Thus, Ramoa does not teach or suggest at least one additional feature of claim 1.
Other cited references, whether considered separately or in combination, also do not
teach or suggest the abovementioned features of claim 1. Therefore, claim 1 is patentable over the cited references. Dependent claims are patentable at least by virtue of their dependence from the patentable independent claim 1.
Accordingly, Applicant requests reconsideration and withdrawal of these rejections.
(see Response filed 03/30/2026 [pages 9-12]).
Applicant argues that the cited references do not teach or suggest the amended limitation of claim 1, including “generating a layout shell structure by preprocessing a full-chip layout based on a two-dimensional polygon mesh representing the full-chip layout and assigning a virtual height to the two-dimensional polygon mesh,” and further argues that Ramoa does not teach a “layout shell structure” having a dimension greater than two dimensions and less than three dimensions based on an assigned virtual height. Applicant’s argument is not persuasive because as set forth in the current rejection, Dadkhah teaches preprocessing full-chip IC layout data and generating a finite element mesh/model from the IC layout data. Ramoa teaches processing layout/image data to generate finite element meshes, including generating an in-plane 2D mesh of cells, generating one or more finite elements from each 2D mesh cell, and generating shell finite element models including thick-shell 2.5D finite elements and 2D shell finite elements. Ramoa further teaches that the mesh cells may be square, rectangular, quadrilateral, or triangular, which are polygonal cells. Thus, Dadkhah and Ramoa teach or suggest generating a layout shell structure from full-chip layout data based on a two-dimensional polygonal mesh representing the full-chip layout.
Applicant also argues that Ramoa merely describes “a single layer” of finite elements that collapses physical PCB thickness and therefore does not teach assigning a “virtual height” to a mesh. This argument is not persuasive because the claim broadly recites “assigning a virtual height” and does not require that using the exact term “virtual height,” be non-physical, be manually assigned, or be calculated by a particular formula. Ramoa teaches generating finite elements from each 2D mesh cell and using shell finite element modeling, including thick-shell 2.5D finite elements and 2D shell finite elements, to represent multiple layers using a shell/thick-shell representation. Accordingly, Ramoa teaches or suggests assigning an out of plane through thickness dimensional extent to the mesh based shell representation, which reasonably corresponds to the broadly recited “virtual height.”
Applicant further argues that Ramoa does not disclose a mesh with a dimensionality greater than two dimensions and less than three dimensions based on the assigned virtual height. This argument is not persuasive because Ramoa expressly teaches thick-shell 2.5D finite elements and 2D shell finite elements. A shell finite element representation with through thickness dimensional information is greater than a purely two-dimensional mesh and less than a full volumetric three-dimensional model. Therefore, Ramoa teaches or suggests the recited layout shell structure having a dimension greater than two dimensions and less than three dimensions based on the assigned virtual height.
Regarding Applicant’s arguments based on paragraphs [0026]-[0028] of Ramoa, Applicant argues that these paragraphs merely describe generating a standard 3D model through “stacks of finite elements” and do not suggest assigning a virtual height to create a structure having dimensionality between two and three. This argument is not persuasive for the same reasons discussed above. Ramoa teaches generating finite elements from each 2D mesh cell, calculating geometric and material features for the finite elements, and using shell/thick-shell finite element modeling. Thus, Ramoa’s disclosure is not limited to a conventional full 3D volumetric representation, but also teaches shell finite element modeling with through thickness dimensional representation.
Applicant also argues that Ramoa does not teach “wherein the virtual height is determined based on the two-dimensional polygon mesh.” To the extent Applicant argues that Ramoa alone does not expressly teach this newly added limitation, the argument is acknowledged. However, the current rejection further relies on newly applied reference, Ferreira (“Estimating Local Part Thickness in Midplane Meshes for Finite Element Analysis,” published in 2011), for this feature. Ferreira teaches a midplane two-dimensional mesh, teaches that midplane meshes are meshes of polygons, and teaches automatic estimation of thickness on a per-element basis using the CAD geometry model and the midplane mesh itself. Ferreira further teaches tagging each mesh element with its associated local thickness. Thus, Ferreira teaches determining an out of plane dimensional extent, reasonably corresponding to the claimed virtual height, based on the two-dimensional polygon mesh
Therefore, for the reasons discussed above, the combination of Dadkhah US20070239419A1 in view of Ramoa (WO2017001890A1) and Yu (US20080221845A1) and Suresh (US20080183524A1) and Ferreira (“Estimating Local Part Thickness in Midplane Meshes for Finite Element Analysis,” published in 2011) teach or suggest the amended claim 1, and the rejection under 35 U.S.C. §103 is maintained.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being
indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation "… has a virtual height corresponding to the three-dimensional simulation model," which renders the claim indefinite because it is unclear if the “a virtual height” refers to assigned virtual height recited in claim 1 or different/new virtual height corresponding to the three-dimensional simulation model. For the purpose of substantive examination, the examiner presumes that “a virtual height” is interpreted as “the assigned virtual height”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and
103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set
forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2 and 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over
Dadkhah US20070239419A1 in view of Ramoa WO2017001890A1 and Yu US20080221845A1 and Suresh US20080183524A1 and Ferreira (“Estimating Local Part Thickness in Midplane
Meshes for Finite Element Analysis,” published in 2011).
Claim 1, Dadkhah teaches (Original) A layout check method comprising:
generating a layout ([0018], “Initially, method 8 begins when IC layout data of an IC device is read and parsed in step 10 by a parsing portion of a conversion program … Further, in step 16, the conversion program instructs the FEA program to generate a finite element mesh of the IC device 9. The finite element mesh defines a three dimensional model of the IC device 9 with identical driver placement and notch area placement.” [0020], “The layout tool generates IC layout data from the IC device 9 for use by the integrated thermal analysis system. The IC layout data is then formatted into three distinct sections by the IC layout tool.” [0021], “The finite element analysis program creates a two-dimensional representation of the surface of the relevant IC device 9 so that each driver and its location can be individually identified.” [0022], “The finite element analysis program is also instructed to generate a three-dimensional finite element mesh 37 (shown in FIG. 3) by extruding the chip surface area 32 already entered.” [0025], “Next, a three-dimensional representation 64 is extruded from the surface of the IC device 9 based on the two-dimensional representation.”. Examiner note: the reference teaches preprocessing IC layout data and generating a finite element structure from the processed full-chip IC layout, and generating a three-dimensional representation by extrusion from a two-dimensional representation of the IC device surface.);
extracting a ([0018], “… in step 20, the conversion program instructs the FEA program to perform the thermal analysis based on the information collected from the user. The FEA program is executed in step 22 to generate thermal analysis data. A thermal analysis report containing the thermal analysis data is produced that provides the relevant thermal characteristics of the IC device 9 in step 24 based upon the operating conditions supplied by the user.”)
However, Dadkhah fails to teach generating a layout shell structure by preprocessing layout based on a two-dimensional polygon mesh representing the layout and assigning a virtual height to the two-dimensional polygon mesh; extracting a stress simulation value of the layout shell structure by performing a stress simulation based on the layout shell structure, and layout shell structure have a dimension which is greater than two dimensions and less than three dimensions based on the assigned virtual height.
Ramoa teaches generating a layout shell structure by preprocessing layout based on a two-dimensional polygon mesh representing the layout and assigning a virtual height to the two-dimensional polygon mesh ([0016], “Processing: at this stage, the methods of the disclosure will access the information enclosed in the gerber files and, after that, it will convert the gerber commands contained in those files into graphic binary structures (bitmaps). Through these bitmaps it will be generated a finite element mesh enhanced with the geometric properties of each finite element of copper such as: area fraction of copper, inertia tensor and centre of mass.” [0022], “The algorithm is prepared to write out finite element meshes based on the following FE types: … (iii) thick-shell 2.5D finite elements, i.e. using only one layer of finite elements through-thickness to describe, in a single finite element … all layers of both FR4 and copper; and (iV) 2D shell finite elements, using 2D bi-linear 4-node quadrilateral shell elements to model with a single shell element all layers of both FR4 and copper.” [0026], “generating in-plane with the PCB a 2D mesh of cells; generating a stack of one or more finite elements from each 2D mesh cell, each said finite element corresponding to one or more PCB layers.” [0029], “… the generated in-plane 2D mesh of cells is a node grid of squares or rectangles, which have been deformed or cut until the 2D mesh of cells is delimited by the PCB shape, such that all finite element nodes will be within the PCB shape.” See also [0030]. Examiner note: the reference teaches processing layout/image data to generate a finite element mesh, generating an in-plane 2D mesh of cells, generating one or more finite elements from each 2D mesh cell, and further teaches shell modeling, including thick-shell 2.5D finite elements and 2D shell finite elements. The disclosed square, rectangular, quadrilateral, and triangular cells are polygonal cells. Thus, the reference teaches generating a layout shell structure by processing layout data based on a two-dimensional polygonal mesh, generating one or more finite elements from each 2D mesh cell corresponding to one or more PCB layers, and representing the layers using shell and thick-shell finite element structures, wherein the through thickness representation of the shell finite elements reasonably corresponds to assigning a virtual height to the two-dimensional polygonal mesh); extracting a ([0017], “Information output: From the previous processing step all the necessary information for the numerical simulation will be provided in the form of: a finite element mesh (nodes, and connectivity), material properties, boundary conditions, element properties and simulation conditions … Starting from these data, the CAE tools will be able to determine the displacement fields of PCB under analysis, and thus estimate the amount of warpage associated with the prescribed thermo-mechanical loadings.” Examiner note: the reference teaches exporting a shell finite element mesh derived from layout data to a CAE solver and performing a numerical simulation on the shell structure to produce numerical simulation output values (e.g., displacement and warpage), which constitute simulation values obtained by performing a simulation based on the layout shell structure); the layout shell structure have a dimension which is greater than two dimensions and less than three dimensions based on the assigned virtual height (see [0022], “… (iii) thick-shell 2.5D finite elements … (iV) 2D shell finite elements …” Examiner note: the reference teaches thick-shell 2.5D finite elements and 2D shell finite elements generated from two-dimensional mesh cells, wherein one shell element represent multiple PCB layers through thickness, which reasonably corresponds to a layout shell structure having a dimensional representation greater than two dimensions and less than three dimensions based on the assigned virtual height).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Dadkhah to incorporate the teachings of Ramoa, and apply processing of layout data using a two-dimensional mesh of cells and shell finite element modeling in order to generate shell based finite element structures from the full chip IC layout and represent multiple layout layers through shell and thick-shell finite element structures corresponding to assigning a virtual height to the two-dimensional polygon mesh for simulation process to reduce computational complexity relative to volumetric three-dimensional finite element modeling while maintain simulation efficient and thickness modeling capability for large scale IC layouts.
However, Ramoa and Dadkhah fail to teach generating a process condition model by preprocessing at least one process condition; extracting a stress simulation value by performing a stress simulation based on process condition model; the process condition model have a dimension which is greater than two dimensions and less than three dimensions.
Yu teaches generating a process condition model by preprocessing at least one process condition ([0145], “The governing equations include mass, momentum, and energy balances, and they are solved (concurrently) in the respective portions of the solution domain, subject to process inputs 640 that describe the process being modeled, initial conditions, and boundary conditions.” Examiner note: the reference teaches that process inputs, initial conditions, and boundary conditions are provided prior to solving the governing equations and describe “the process being modeled.” These inputs together define a process condition model, as they parameterize the modeled process before execution of the solver); extracting a stress simulation value by performing a stress simulation based on the process condition model ([0145], “The equation solver 642 in the system 600 of FIG. 6 solves for the distribution of one or more process variables (such as pressure, temperature, flow velocity, stress, viscosity, and fluid flow front) in the first and second portions of the solution domain as functions of time.” Examiner note: the reference teaches that an equation solver computes stress as a process variable by solving the governing equations subject to the previously defined process inputs, initial condition, and boundary condition); the process condition model have a dimension which is greater than two dimensions and less than three dimensions based on the assigned virtual height ([0144], “The 2.5D-analysis portion is made up of regions 1702, 1704, 1706 (light colored) that are discretized with wedge elements.” See also [0131], [0133]-[0134], [0145] and [0146]. Examiner note: the reference teaches a 2.5D-analysis portion of the solution domain is generated by assigning thickness to subsurface/elements and discretizing the 2.5D portion using wedge elements, with the governing equations solved through a thickness direction defined by h. Thus, Yu teaches a process condition model having a 2.5D dimensional representation based on an assigned thickness, which reasonably corresponds to the claimed process condition model having a dimension greater than two dimensions and less than three dimensions based on the assigned virtual height.).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Dadkhah and Ramoa to incorporate the teachings of Yu, and apply Yu’s process condition modeling with assigned virtual height and stress computation to the shell element layout analysis in order to enable stress simulation that account for defined process conditions while retaining the computational efficiency for large scale structural analysis. Dadkhah and Ramoa teach generating a shell element mesh derived from layout data for use in mechanical analysis of layout structure. Yu teaches preprocessing process conditions, including governing equations, initial conditions, and boundary conditions, to generate a numerical process condition model, and solving that model to obtain stress values by using a 2.5D simulation domain. The combination of teaching would provide benefit of improving simulation efficiency while maintaining accurate mechanical stress evaluation for large scale layout structures.
However, Ramoa and Dadkhah and Yu fail to teach extracting statistics data based on the stress simulation value.
Suresh teaches extracting statistics data based on the stress simulation value ([0004], “Once the mesh is complete, finite element analysis may be performed to assess the behavior of the model. More particularly, the analysis process may measure various performance metrics, such as stress, displacement, thermal transfer, and the like.” [0005], “A particularly challenging implication of such an iterative design process is that the designer must compute various quantities of interest, e.g., such as average stress within a region, maximum deflection, etc., as features and/or parameters are modified.” [0029], “The data of the table may be statistically evaluated to provide statistical values, such as mean values, to assist the designer in identifying the hole location that is optimal.”).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Dadkhah and Ramoa and Yu to incorporate the teachings of Suresh, and apply Suresh’s extraction of statistical metrics derived from finite element stress simulation results in order to obtain quantitative statistical data from the stress simulation values generated for the layout shell structure. The combination of teaching would provide benefit of enabling systematic evaluation and comparison of mechanical stress behavior across a layout while improving analysis efficiency with high stress simulation accuracy.
However, Dadkhah and Ramoa and Yu and Suresh fail to teach the virtual height is determined based on the two-dimensional polygon mesh.
Ferreira teaches the virtual height is determined based on the two-dimensional polygon mesh (Page.69, right column, last paragraph, “the entire geometric domain (whether a midplane two-dimensional mesh, or a full three-dimensional surface or solid mesh), is discretized and modelled by a mesh mesh), comprised of a large set of finite elements … Elements are then assigned properties, which can be physical (e.g. thickness …).” Page.70, right column, “These representations are meshes of polygons that, ideally, run in the middle of the closed surface – they are thus referred to as midplane meshes (see figure 1) … Midplane meshes are generated from the CAD geometry model, … The problem addressed throughout this paper is automatic estimation of thickness on a per-element basis, using as inputs the CAD geometry model and the midplane mesh itself … The proposed thickness estimation techniques … allow tagging each mesh element with its associated local thickness …”. II. THICKNESS ESTIMATION ALGORITHMS, “Ideally, the midplane mesh runs inside the closed surface and parallel to it (see figure 2). Intuitively, in such cases the thickness at the centroid of each midplane mesh element is the sum of the distances between this centroid and some surface point on each side of the element. Examiner note: the reference teaches a midplane two-dimensional mesh and the midplane meshes are meshes of polygons, and further teaches automatically estimating thickness on a per-element basis using the CAD geometry model and the midplane mesh itself, and tagging each mesh element with its associated local thickness. The assigned local thickness provides an out of plane dimensional extent for the corresponding mesh elements and is used to supplement the two dimensional polygon mesh for simulation, which reasonably corresponds to determining a virtual height based on the two dimensional polygon mesh).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Dadkhah and Ramoa and Yu and Suresh to incorporate the teachings of Ferreira, and apply automatic estimation of local thickness values for mesh elements based on a midplane two dimensional polygon mesh in order to improve the accuracy of shell based simulation models by providing element specific thickness information without requiring full volumetric three dimensional modeling. The combination of teaching would predictably provide benefit of improve the simulation accuracy and efficiency while reducing computational complexity.
Claim 2, Dadkhah fail to teach, but Ramoa teaches (Original) The layout check method of claim 1, wherein the generating of the layout shell structure comprises:
generating a tile layout by disassembling the full-chip layout into a plurality of tiles ([0019], “The first one (1st step) is reading and processing the information of the gerber files. These information is discretized and temporarily stored in high-resolution bitmaps, i.e. bitmaps are generated based on the information defining the geometric features on each layer of copper existent on the PCB.” [0026], “generating in-plane with the PCB a 2D mesh of cells.” Examiner note: A POSITA would understand that the “2D mesh of cells” is interpreted as a subdivision of the full-chip PCB layout into multiple discrete layout regions. Each cell corresponds to a portion of the overall layout that can be independently represented and processed);
extracting a polygon based on parsing performed on each of the plurality of tiles ([0015], “Gerber files are lines of code that follows preferably the RS- 274X standard containing the coordinates describing the geometry of all the elements of a PCB.” [0016], “the methods of the disclosure will access the information enclosed in the gerber files and, after that, it will convert the gerber commands contained in those files into graphic binary structures (bitmaps).” Examiner note: A POSITA would understand parsing to be performed on subdivided regions of the layout when the layout is processed in cells (tiles));
generating a polygon mesh corresponding to each of the plurality of tiles by generating a mesh based on the polygon ([0020], “The second step is the finite element mesh generation, which will be a 3D representation of the real macroscopic geometry of the PCB … the finite element mesh created by this method consists of the Cartesian nodal coordinates of all nodes defining the PCB geometry, the connectivity between these nodes …” [0026], “… generating a stack of one or more finite elements from each 2D mesh cell …” See also [0029]-[0030]); and
generating the layout shell structure by assigning the virtual height to the polygon mesh ([0022], “… (iii) thick-shell 2.5D finite elements, i.e. using only one layer of finite elements through-thickness to describe, in a single finite element (3D tri-linear 8-node hexahedron) all layers …” Examiner note: the reference teaches generating a finite element mesh from layout geometry and defining a thick shell 2.5D by using one layer of finite elements through the thickness, which assigns a through thickness dimension to the mesh. A POSITA would understand that through thickness dimension corresponds to a virtual height assigned to the polygon mesh to form a layout shell structure).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Dadkhah to incorporate the teachings of Ramoa, and apply Ramos’s converting layout data into a two dimensional mesh of cells and generating finite element meshes with assigned thickness (2.5D) in order to enable efficient mechanical analysis of full-chip layout geometry while reducing computational complexity relative to full three dimensional modeling, thereby allowing the layout geometry as a layout shell structure that maintained simulation accuracy and improving scalability for large layout analysis.
Claim 7, Dadkhah and Ramoa and Yu fail to teach, but Suresh teaches (Original) The layout check method of claim 1, wherein the extracting of the statistics data comprises generating statistics data of the full-chip layout by performing statistics analysis based on the stress simulation value ([0004], “a computerized model will include multiple individual finite design features or elements that are independently developed and then combined or meshed into a single composite model … Once the mesh is complete, finite element analysis may be performed to assess the behavior of the model. More particularly, the analysis process may measure various performance metrics, such as stress, displacement, thermal transfer, and the like.” [0005], “… the designer must compute various quantities of interest, e.g., such as average stress within a region, maximum deflection, etc., as features and/or parameters are modified.” [0029], “The data of the table may be statistically evaluated to provide statistical values, such as mean values, to assist the designer in identifying the hole location that is optimal.”).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Dadkhah and Ramoa and Yu to incorporate the teachings of Suresh, and apply Suresh’s extraction of statistical metrics derived from finite element stress simulation results in order to enable quantitative evaluation and comparison of stress simulation results produced during full-chip mechanical analysis. The combination of teaching would provide benefit of enabling systematic evaluation and comparison of mechanical stress behavior across a layout while improving analysis efficiency with high stress simulation accuracy.
Claim 8, Dadkhah and Ramoa and Yu fail to teach, but Suresh teaches (Original) The layout check method of claim 7, wherein the extracting of the statistics data comprises:
selectively converting the stress simulation value into a layout viewer format ([0020], “The results of the finite element analysis are output in a conventional manner, e.g., on a computer display, at block 16.” [0026], “Conversely, as reflected in the process 30 set forth in the flow chart of FIG. 2, the computer could receive an input from the designer at block 32 indicative of a desired quantity of interest.” [0029], “The data of the table may be statistically evaluated to provide statistical values, such as mean values, to assist the designer in identifying the hole location that is optimal.” Examiner note: A POSITA would understand that displaying finite element stress results associated with spatial regions of a modeled structure that constitutes stress values in a layout correlated viewer format, since the stress values are mapped to corresponding locations of the modeled layout); and
generating additional data, where the statistics data extracted from each of a plurality of different full-chip layouts is converted into a relative score, by selectively and additionally analyzing the statistics data ([0026], “… the computer could iteratively cycle through various design alternatives, find the quantity of interest for each alternative, and then determine which of the alternatives provides a best fit given the desired quantity of interest.” [0029], “The data of the table may be statistically evaluated to provide statistical values, such as mean values, to assist the designer in identifying the hole location that is optimal.” Examiner note: A POSITA would understand that statistically evaluating simulation results across multiple design alternatives to determine which alternative provides a best fit converts the evaluated statistics into a relative score or ranking among the alternatives).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Dadkhah and Ramoa and Yu to incorporate the teachings of Suresh, and apply Suresh’s generation of statistical metrics derived from finite element stress simulation results in order to compute statistical measures, such as average stress and other statistical values for evaluating and comparing modeled structures. The combination of teaching would provide benefit of enabling systematic evaluation and comparison of mechanical stress behavior across a layout while improving analysis efficiency with high stress simulation accuracy.
Claim 9, Dadkhah and Ramoa and Yu fail to teach, but Suresh teaches (Original) The layout check method of claim 1, wherein the extracting of the statistics data comprises:
performing pattern analysis based on the stress simulation value ([0004], “Once the mesh is complete, finite element analysis may be performed to assess the behavior of the model. More particularly, the analysis process may measure various performance metrics, such as stress, displacement, thermal transfer, and the like.” [0005], “A particularly challenging implication of such an iterative design process is that the designer must compute various quantities of interest, e.g., such as average stress within a region, maximum deflection, etc., as features and/or parameters are modified.” [0029], “The data of the table may be statistically evaluated to provide statistical values, such as mean values, to assist the designer in identifying the hole location that is optimal.” Examiner note: A POSITA would understand that analyzing stress distributions produced by finite element analysis would involves identifying spatially recurring stress distribution pattern across different regions of the layout as stress results are evaluated over multiple locations of the modeled structure); and
generating statistics data for each pattern by performing statistics analysis based on a result obtained by performing the pattern analysis ([0005], “… the designer must compute various quantities of interest, e.g., such as average stress within a region, maximum deflection, etc., as features and/or parameters are modified.” [0029], “The data of the table may be statistically evaluated to provide statistical values, such as mean values, to assist the designer in identifying the hole location that is optimal.” Examiner note: A POSITA would understand that generating statistics data for each identified stress pattern or region based on results obtained from stress analysis).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Dadkhah and Ramoa and Yu to incorporate the teachings of Suresh, and apply Suresh’s analysis of stress simulation results in order to evaluate stress behavior across different layout regions and generate statistical data corresponding to identified stress behavior patterns, thereby enabling quantitative comparison and assessment of mechanical stress characteristics while improving analysis efficiency using stress statistical analysis.
Claim 10, Dadkhah and Ramoa and Yu fail to teach, but Suresh teaches (Original) The layout check method of claim 9, wherein the performing of the pattern analysis comprises:
extracting a plurality of local layout patterns based on the stress simulation value ([0004], “… a computerized model will include multiple individual finite design features or elements that are independently developed and then combined or meshed into a single composite model.” Examiner note: A POSITA would understand that individual finite design features or elements analyzed by stress simulation corresponds to localized regions of the layout from which recurring stress behavior being identified); and
categorizing the plurality of local layout patterns for each local layout pattern having a same pattern ([0005], “the designer must compute various quantities of interest, e.g., such as average stress within a region, maximum deflection, etc., as features and/or parameters are modified.” Examiner note: A POSITA would understand that regions exhibiting similar stress metrics would be categorized together for comparison as having the same stress behavior).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Dadkhah and Ramoa and Yu to incorporate the teachings of Suresh, and apply Suresh’s analyzing finite elements stress results to identify stress behavior across different regions in order to identify and group localized layout regions exhibiting similar stress behavior within the shell element of full chip layout structure, thereby facilitating comparison and evaluation of recurring stress patterns across the layout based on stress simulation values.
Claim(s) 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Dadkhah and Ramoa
and Yu and Suresh and Ferreira as applied to claim 1 above, and further in view of Tsuchiya US20050233601A1.
Claim 4, Dadkhah and Ramoa fail to teach, but Yu further teaches (Original) The layout check method of claim 1, wherein the generating of the process condition model comprises:
generating the process condition model which is configured to output a same value as the simulation value and has a virtual height corresponding to the three-dimensional simulation model ([0144], “The 2.5D-analysis portion is made up of regions 1702, 1704, 1706 (light colored) that are discretized with wedge elements.” [0145], “The equation solver 642 in the system 600 of FIG. 6 solves for the distribution of one or more process variables (such as pressure, temperature, flow velocity, stress, viscosity, and fluid flow front) in the first and second portions of the solution domain as functions of time. The governing equations include mass, momentum, and energy balances, and they are solved (concurrently) in the respective portions of the solution domain, subject to process inputs 640 that describe the process being modeled, initial conditions, and boundary conditions.” Examiner note: the reference teaches generating a numerical process condition model governed by process inputs and solved equations, and the model outputs stress values, which are the same type of simulation value extracted from a three dimensional simulation, and 2.5D analysis portion discretized with wedge elements. A POSITA would understand that a reduced dimension model having a virtual height corresponding to a three dimensional simulation model).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Dadkhah and Ramoa to incorporate the teachings of Yu, and apply Yu’s process condition modeling and stress computation to the shell element layout analysis in order to enable stress simulation that account for defined process conditions while retaining the computational efficiency for large scale structural analysis. Dadkhah and Ramoa teach generating a shell element mesh derived from layout data for use in mechanical analysis of layout structure. Yu teaches preprocessing process conditions, including governing equations, initial conditions, and boundary conditions, to generate a numerical process condition model, and solving that model to obtain stress values by using a 2.5D simulation domain. The combination of teaching would provide benefit of improving simulation efficiency while maintaining accurate mechanical stress evaluation for large scale layout structures.
However, Dadkhah and Ramoa and Yu and Suresh and Ferreira fail to teach extracting a simulation value by applying the at least one process condition to a three-dimensional simulation model.
Tsuchiya teaches extracting a simulation value by applying the at least one process condition to a three-dimensional simulation model ([0070], “In Step S104, based on process conditions of the target process and the structure of the semiconductor substrate 50 processed by the target process, the stress analysis module 10 performs a three-dimensional stress simulation to predict a stress field by calculating stresses at a plurality of nodes provided in the structure of the semiconductor substrate 50.”).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Dadkhah and Ramoa and Yu and Suresh and Ferreira to incorporate the teachings of Tsuchiya, and apply Tsuchiya’s using process conditions to a three dimensional simulation model to extract a stress simulation value in order to obtain simulation results derived from three-dimensional modeling under specified process conditions, thereby proving more accurate simulation outputs while preserving the computational efficiency and scalability of the reduced dimension layout.
Claim 6, Dadkhah and Ramoa and Yu and Suresh and Ferreira fail to teach, but Tsuchiya teaches (Original) The layout check method of claim 1, wherein the extracting of the stress simulation value comprises extracting information about at least one of coordinates, a stress value, strain, and displacement each corresponding to a position at which stress occurs ([0008], “an origin setting module configured to provide a plurality of origins at positions where a stress concentration having a stress value not less than a reference value is predicted.”).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Dadkhah and Ramoa and Yu and Suresh and Ferreira to incorporate the teachings of Tsuchiya, and apply Tsuchiya’s teaching of identifying stress values at specific positions where stress concentrations occur in order to extract positional stress information from simulation results produced by the stress analysis, thereby causing report stress information that is spatially correlated with locations at which stress occurs.
Claim(s) 5 is rejected under 35 U.S.C. 103 as being unpatentable over Dadkhah and Ramoa and Yu
and Suresh and Ferreira as applied to claim 1 above, and further in view of Hisada (“Study of Warpage and Mechanical Stress of 2.5D Package Interposers during Chip and Interposer Mount Process,” published on 2012).
Claim 5, Dadkhah and Ramoa and Yu and Suresh and Ferreira fail to teach, but Hisada teaches (Original) The layout check method of claim 1, wherein the extracting of the stress simulation value comprises:
generating a target shell structure by applying the process condition model to the layout shell structure (abstract, “We analyzed warpage behavior and mechanical stress using finite element method (FEM) modeling technique with a set of combinations of coefficient of thermal expansion (CTE) and elastic modulus of the interposers.” Page.969, FEM Modeling and Analysis, “We modeled three different sequences of mount process described in the previous section. The models of sequence -α and - β consist of two reflow steps … These models were created in half of the assembled form.” Examiner note: the reference teaches generating finite-element shell structural model of semiconductor packages and modifying models by applying process conditions such as mount process sequency, material properties, and reflow steps. A POSITA would understand that applying process conditions to an existing layout shell model necessarily produces a modified (target) shell structure corresponding to the applied process conditions); and
extracting the stress simulation value by performing the stress simulation on the basis of the target shell structure (Abstract, “We show the analysis results of interposer warpage, first principal stress at low-k dielectric layer under C4 pad and von Mises stress at solder interconnections of chip joining and interposer joining.” Examiner note: the abstract shows performing a finite element method (FEM) modeling technique to analyze mechanical stress, and the FEM analysis produces stress results (e.g., first principal stress and von mises stress). Therefore, the NPL teaches extracting a stress simulation value (stress values/results) by performing a stress simulation (FEM mechanical analysis ) on a modeled package structure (interposer, solder interconnections, chip joining and interposer joining).).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Dadkhah and Ramoa and Yu and Suresh and Ferreira to incorporate the teachings of Hisada, and apply Hisada’s modeled process conditions to the layout structural prior to stress analysis in order to generate a conditioned structural model that reflects process induce effects before stress simulation, thereby allowing stress simulation values to be extracted from a target shell structure that incorporates applied process conditions.
Allowable Subject Matter
Claims 11-13 and 15-17 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 11 and 18, the closest prior arts found, Dadkhah (US20070239419A1), discloses a method for performing a thermal analysis, including the steps of determining size and placement of each of a plurality of drivers on an integrated circuit device. The determined size and placement of each driver is stored as layout data and the layout data is converted into input for a finite element analysis program. Ramoa (WO2017001890A1), discloses a method to convert a Printed Circuit Board, PCB, image description, in particular a PCB vector image file (e.g. Gerber file), to a finite element model (e.g. a computer-aided engineering, CAE, file), in particular a finite element model of thermo-mechanical loading. Yu (US20080221845A1), discloses methods of process simulation and analysis. More particularly, the invention relates to the simulation of injection molding using a multidimensional model. Suresh (US20080183524A1), discloses finite element analysis may be performed to assess the behavior of the model. More particularly, the analysis process may measure various performance metrics, such as stress, displacement, thermal transfer, and the like. A particularly challenging implication of such an iterative design process is that the designer must compute various quantities of interest, e.g., such as average stress within a region, maximum deflection, etc., as features and/or parameters are modified. Moroz (US20100042958A1), discloses dividing the search region into a rectangular grid and calculating the stress caused by each grid rectangle in which there is a source of stress. (New reference) Sriraman (US20210157228A1), discloses using design layout segments, such as clips or gauges, and computational resist and etch models to predict developed resist profiles and etched feature profiles, and using process conditions and generating two-dimensional contours or three-dimensional representations of features (e.g., [0004] and [0006]-[0008]). (New reference) Jandhyala (US20070245275A1), discloses reading geometry/layout data, preprocessing a two-dimensional circuit layout, creating a two-dimensional mesh of polygons for each layer, and extruding the mesh to form a three-dimensional mesh for electromagnetic simulation (e.g., [0008]-[0009]).
However, In light of record taken as a whole, applicant's method claim 11 is considered to be patentable distinct over the prior art. In particular, the prior art does not disclose, teach or suggest in combination of limitations “generating a process condition model by using at least one process condition and a three-dimensional simulation model, the process condition model having the virtual height; generating a plurality of target shell structures by applying the process condition model to the layout shell structure; and extracting stress simulation values respectively corresponding to the plurality of target shell structures by performing a stress simulation on each of the plurality of target shell structures,” as disclosed in claim 11. Claims 12-13 and 15-17 are allowed as being dependent from allowed claim 11.
Claims 18-22 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 18, the closest prior arts found, Dadkhah (US20070239419A1), discloses a method for performing a thermal analysis, including the steps of determining size and placement of each of a plurality of drivers on an integrated circuit device. The determined size and placement of each driver is stored as layout data and the layout data is converted into input for a finite element analysis program. Ramoa (WO2017001890A1), discloses a method to convert a Printed Circuit Board, PCB, image description, in particular a PCB vector image file (e.g. Gerber file), to a finite element model (e.g. a computer-aided engineering, CAE, file), in particular a finite element model of thermo-mechanical loading. Yu (US20080221845A1), discloses methods of process simulation and analysis. More particularly, the invention relates to the simulation of injection molding using a multidimensional model. Suresh (US20080183524A1), discloses finite element analysis may be performed to assess the behavior of the model. More particularly, the analysis process may measure various performance metrics, such as stress, displacement, thermal transfer, and the like. A particularly challenging implication of such an iterative design process is that the designer must compute various quantities of interest, e.g., such as average stress within a region, maximum deflection, etc., as features and/or parameters are modified. Moroz (US20100042958A1), discloses dividing the search region into a rectangular grid and calculating the stress caused by each grid rectangle in which there is a source of stress. (New reference) Sriraman (US20210157228A1), discloses using design layout segments, such as clips or gauges, and computational resist and etch models to predict developed resist profiles and etched feature profiles, and using process conditions and generating two-dimensional contours or three-dimensional representations of features (e.g., [0004] and [0006]-[0008]). (New reference) Jandhyala (US20070245275A1), discloses reading geometry/layout data, preprocessing a two-dimensional circuit layout, creating a two-dimensional mesh of polygons for each layer, and extruding the mesh to form a three-dimensional mesh for electromagnetic simulation (e.g., [0008]-[0009]).
However, In light of record taken as a whole, applicant's method claim 18 is considered to be patentable distinct over the prior art. In particular, the prior art does not disclose, teach or suggest in combination of limitations “… to generate a process condition model having a virtual height based on at least one of the process conditions and the three-dimensional simulation model, and to perform the stress simulation by using a target shell structure generated by applying the process condition model to the layout shell structure,” as disclosed in claim 18. Claims 19-22 are allowed as being dependent from allowed claim 18.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Onodera US20150254392, discloses method of verifying a layout of a semiconductor integrated
circuit. The method includes executing a timing analysis of the semiconductor integrated circuit based on first layout information acquired after execution of a layout process; executing layout correction with respect to the first layout information; comparing the first layout information acquired before the execution of the layout correction and second layout information acquired after the execution of the layout correction to acquire information indicating an RC difference in wires; and adding, by a computer, an effect due to an increase in delay in the wires resulting from the RC difference to timing information obtained by the timing analysis.
H. Cheng et al., "Theoretical and Experimental Investigation of Warpage Evolution of Flip Chip Package on Packaging during Fabrication," published on 25 August 2021, discloses investigate the warpage behavior of a flip chip package-on-package (FCPoP) assembly during fabrication process. A process simulation framework that integrates thermal and mechanical finite element analysis (FEA), effective modeling and ANSYS element death-birth technique is introduced for effectively predicting the process-induced warpage.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/YI . HAO/
Examiner, Art Unit 2187
/EMERSON C PUENTE/Supervisory Patent Examiner, Art Unit 2187
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