DETAILED ACTION
This action is in response to application 17/950773, filed on 9/22/2022. Claims 1-25 are pending. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 13, and 18 recite “a processor,” “a protected system memory,” and “a just in time (JIT) compiler executable by the processor” (a) to receive “a JIT file comprising instructions” and (b) to “JIT compile the JIT file into machine code, wherein the machine code includes a translation for the instructions in the JIT file, plus an opcode for a JIT instruction.” The claims also recite (c) “use code stored in the protected system memory to execute the opcode for the JIT instruction while executing the machine code.” It is unclear whether the “processor” or the “just in time (JIT) compiler” is executing “the opcode for the JIT instruction while executing the machine code” in limitation (c). In other words, the claims appear to require the JIT compiler to “use code stored in the protected system memory to execute the opcode for the JIT instruction.” How would the “JIT compiler” itself “execute the opcode for the JIT instruction” and would it also be required to execute said opcode “while executing the machine code”? Does the execution of the JIT compiler by the processor cause execution of the opcode? Does the JIT compiler access “code stored in the protected system memory”? Does the “machine code” in limitation (b) include the “code stored in the protected system memory” used “to execute the opcode” in limitation (c)? Because of the foregoing ambiguities, the claims are not decipherable and cannot be examined in their present form. The dependent claims not specifically mentioned inherit the deficiencies of claims 1, 14, and 18 and are rejected accordingly.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 18-25 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claims do not fall within at least one of the four categories of patent eligible subject matter because the claimed “machine readable storage media” does not exclude transitory media. To overcome the instant rejection, Applicant may amend claim 18 to recite “One or more non-transitory machine readable storage media” or similar. The dependent claims not specifically mentioned inherit the deficiencies of claim 18 and are rejected accordingly.
Conclusion
The prior art made of record is considered pertinent to applicant's disclosure. USPGPUB 2018/0159830 (“Gibbons”) discloses manipulating opcode locations in bytecode generated for a browser. USPGPUB 2021/0182040 (“Tiwary”) discloses delegating JIT bytecode compilation to a Web Assembly (WASM) runtime for purposes of access protection and performance optimization. The cited ARM document describes a trusted execution environment, or “Confidential Compute Architecture,” comprising memory access controls and instructions similar to the claimed “XuCode Mode.” The Kucuk reference describes using XuCode and Intel’s SGX to allow code to be executed in protected memory regions.
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/Ryan D. Coyer/Primary Examiner, Art Unit 2191