Prosecution Insights
Last updated: May 29, 2026
Application No. 17/950,826

REDUCING LATENCY OF HARDWARE TRUSTED EXECUTION ENVIRONMENTS

Final Rejection §103§112
Filed
Sep 22, 2022
Priority
Dec 22, 2020 — continuation of 17/131,716
Examiner
LIPMAN, JACOB
Art Unit
2434
Tech Center
2400 — Computer Networks
Assignee
Intel Corporation
OA Round
10 (Final)
83%
Grant Probability
Favorable
11-12
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
659 granted / 790 resolved
+25.4% vs TC avg
Moderate +14% lift
Without
With
+13.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
21 currently pending
Career history
818
Total Applications
across all art units

Statute-Specific Performance

§101
1.3%
-38.7% vs TC avg
§103
66.8%
+26.8% vs TC avg
§102
20.0%
-20.0% vs TC avg
§112
2.3%
-37.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 790 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement The information disclosure statements (IDS) submitted on 8 January 2026 and 12 March 2026 have been considered by the examiner. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 2, 26, and 30 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 2 recites the limitation " the processing circuitry comprises at least one graphics processing unit (GPU)". It is unclear if this is the same GPU of the patent claim, or a new GPU, and if it is the same, what limitation exactly is being added to the parent claim, that already includes a GPU. This renders the claim unclear and indefinite. This issue is repeated in claims 26 and 30. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1, 2, 25, 26, 29, and 30, as best understood, are rejected under 35 U.S.C. 103 as being unpatentable over YU, CN 107870788 A, outlined using previously supplied translation (supplied 27 January 2023), in view of Herbert et al., USPN 2017/0177417, in further view of Cheng, KR 20200130164 A, outlined using previously supplied translation (supplied 27 January 2023). With regard to claims 1, 2, 25, 26, 29, and 30, Yu discloses an apparatus (page 3 paragraph starting “in order”), including memory circuitry and processing circuitry (page 3 paragraph starting “in order”, page 5 paragraph starting “in specific”) coupled to the memory circuitry (page 3 paragraph starting “in order”), the processing circuitry configured to allocate resources of the processing circuitry to create a plurality of TEEs (page 2 paragraph starting “in order”, page 4 paragraph starting “further”), initialize respective TEEs of the plurality of TEEs by allocating an isolated memory space to the respective TEEs in memory circuitry (page 5 paragraph starting “in specific”), and enabling the respective TEEs to execute workloads on the processing circuitry (page 8 paragraph starting “in order”), wherein the respective TEEs of the plurality of TEEs are initialized to support independent scheduling and execution of a plurality of different types of workloads (page 8 paragraph starting “in order”), after the respective TEEs of the plurality of TEEs are initialized, receive a request to execute a workload (starting code), and enable the TEE to execute the one or more workloads (page 9 paragraph starting “in the configuration”), in response to the request, wherein the TEE is isolated from one or more TEEs of the plurality of TEEs that are capable of executing one or more workloads distinct from the workload (pages 5 and 6 paragraph starting “in particular”). Yu discloses the initialization of the multiple TEEs, as outlined above, but does not disclose, in detail, the respective TEEs of the plurality of TEEs are initialized to support independent scheduling and execution of a plurality of different types of workloads or encryption techniques or that the TEE which is to execute the workload is isolated to a particular user of the plurality of users, and wherein, during executing of the workload, other TEEs of the plurality of TEEs are available to perform other workloads for other users of the plurality of users, or that the TEEs can are isolated in a single GPU. Herbert discloses an apparatus including memory circuitry, and processing circuitry (0019-0021), configured to allocate resources of the processing circuitry to create a plurality of trusted execution environments (TEEs) (0107, 0063), initialize respective TEEs of the plurality of TEEs by allocating an isolated memory space to the respective TEEs (0063, 0103) and enabling the respective TEEs of the plurality of TEEs to execute workloads on the processing circuitry (0063), wherein the respective TEEs of the plurality of TEES are initialized to support independent scheduling and execution (0087) of a plurality of different types of workloads (0105), after the respective TEEs of the plurality of TEEs are initialized, receive a request to execute a workload (0087), and cause a TEE of the initialized plurality of TEEs to execute the workload in response to the request (0063), wherein the TEE which is to execute the workload is isolated to a particular user of the plurality of users (0024-0029, 0078, 0081), and wherein, during executing of the workload, other TEEs of the plurality of TEEs are available to perform other workloads for other users of the plurality of users (0024-0029, 0078, 0081). And further discloses the processing circuitry includes one or more graphics processing circuitry or application processing circuitry (0021), wherein, the TEE is configured to be isolated (Fig. 4, 0041, 0093, 0106) and execute the one or more workloads using a portion of the graphics processing circuitry (0022, 0041). It would have been obvious for one of ordinary skill in the art, prior to the instant effective filing date, to implement the GPU isolated workload and user specific TEE tasking of Herbert in the apparatus of Yu for the stated motivation of Herbert, ensuring that there is no cross-contamination between workloads, or security breaches between workloads (0081). Yu in view of Herbert does go into detail on key assignment, although Herbert mentions cryptographic security (0048, 0086). Cheng discloses a system using multiple TEEs (page 3 paragraphs starting “the data processing”) similar to that of Yu in view of Herbert, and further discloses the processing circuitry is further configured to assign an encryption key to the TEE which is to execute the workload, and encrypt the memory space allocated to the TEE which is to execute the workload using the encryption key (page 4 second paragraph starting “in one embodiment) and that the processing circuitry includes a graphics processor (page 8), wherein, the TEE is isolated (Fig. 1, pages 3-4) and configured to execute the workload using a portion of the processor (pages 7-8). It would have been obvious for one of ordinary skill in the art, prior to the instant effective filing date, to implement the TEE initialization of Yu in view of Herbert in the apparatus of Cheng for the motivation of ensuring the TEEs of Herbert and Cheng be secure. Response to Arguments Applicant’s arguments, filed 9 March 2026, have been fully considered and are not persuasive. The examiner does not agree that Herbert is irrelevant, old, or archaic. Herbert was filed in December of 2015, published in 2017 and patented in 2020, which is also the year of the instant effective filing date. Herbert does discuss TEEs and having different types of workloads assigned to different enclaves (0105), which are defined as including TEEs (0063). The fact that Herbert is directed toward monitoring TEE activity does not mean he does not also disclose assigning workloads to TEEs. The examiner continues to recommend that applicant not argue over the age of a reference. The instant arguments copy the entire independent claim and state that the references do no teach it. Applicant is requested to argue specific detailed differences between the claims and the cited references. The examiner recommends identifying the core part of the invention that is novel over the cited references, pointing it out, and arguing why it would not be obvious to add such a feature to the prior art. The rest of applicant’s arguments consist of copying claim 1, several times, each time with almost all the limitations either underlined or in bold, and stating that the references do not teach them. These arguments are not persuasive, and are not really arguments. Applicant is encouraged to point to one or two specific limitations that are seen as either not taught or not obvious over the prior art, and a writing actual convincing arguments over them. Applicant does not specifically state why the limitation added, in the amendments filed 9 March 2026, distinguishes the instant invention from the cited prior art. References Cited Zeng et al., USPN 2018/0129828, discloses a system using a GPU to isolate trusted execution environments (0001). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB LIPMAN whose telephone number is (571)272-3837. The examiner can normally be reached 5:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ali Shayanfar can be reached at 571-270-1050. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JACOB LIPMAN/Primary Examiner, Art Unit 2434
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Prosecution Timeline

Show 26 earlier events
Jun 02, 2025
Response Filed
Jun 11, 2025
Final Rejection mailed — §103, §112
Aug 08, 2025
Response after Non-Final Action
Oct 30, 2025
Request for Continued Examination
Nov 13, 2025
Response after Non-Final Action
Dec 08, 2025
Non-Final Rejection mailed — §103, §112
Mar 09, 2026
Response Filed
Apr 29, 2026
Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

11-12
Expected OA Rounds
83%
Grant Probability
97%
With Interview (+13.6%)
2y 10m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 790 resolved cases by this examiner. Grant probability derived from career allowance rate.

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