CTFR 17/951,024 CTFR 81278 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1 – 25 are pending. Response to Arguments 07-37 AIA Applicant's arguments filed 04 March 2026 have been fully considered but they are not persuasive. Applicant argues that the relied upon references, specifically US Patent No. 7,617,377 (hereinafter Moertl), does not teach "guest software issuing a command directly to the ATC to modify information stored in the ATC" (Applicant's remarks filed 04 March 2026; Page 2). However, the Examiner respectfully submits that the claim in question, claim 12, does not require the limitation above. The claim, as currently written, does not require a command issued directly to an ATC. Rather, the claim only requires receiving a command to modify information stored in an ATC of an accelerator from guest software executing on a host processor. There is no limitation on what device receives the command, only that the command come from the guest software and be a command to modify information stored in an ATC of an accelerator. Moertl teaches a guest software (Moertl; Figure 4 Item 450, Figure 7 Item 710 – 740, Figure 31A Item 1365 – Figure 13B Item 1385) executing on a host processor (Moertl; Figure 1 Item 110) that sends an invalidation request (Moertl; Col 9 Lines 3 – 10) to a device driver service (Moertl; Figure 4 Item 470). The invalidation request triggers the device driver service and the root complex to modify information stored in the ATC (Moertl; Col 9 Lines 7 – 10). Therefore, the Examiner maintains that the cited prior art teaches the limitation of the claimed invention. Applicant also argues that the Examiner has not provided a reasoned analysis as to why it would be obvious to incorporate the completion record of Tian within the context of the ATS invalidation performed by a root complex of Moertl. However, the Examiner respectfully asserts that the teachings of Tian described a driver utilizing the completion record address of an invalidation command in order to determine successful completion of the invalidation operation. The driver and invalidation command described by Tian are similar to the device driver and invalidation request described in Moertl. Tian explicitly states that utilizing the completion record address in the invalidation command provides the benefit of providing the driver with the status related to the invalidation (Tian; Paragraph [0067]). Therefore, the Examiner maintains that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined the teachings of Moertl and Tian . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1 – 9 and 12 – 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Patent No. 7,617,377 (hereinafter Moertl) in view of US Patent Application Publication No. 2021/0064525 (hereinafter Tian) . As per claim 1, Moertl teaches an apparatus comprising: a processor (Moertl; Figure 1 Item 140, Figure 4 Item 490, Figure 9 Item 990) comprising an address translation cache (ATC) (Moertl; Figure 1 Items 160 – 164, Figure 4 Item 494, Figure 9 Item 992); a port (Moertl; Figure 1 “PCIe PORT”) to couple to a host processor (Moertl; Figure 1 Item 110) and a memory management unit (Moertl; Figure 1 Item 130, Figure 4 Item 482, Figure 9 Item 962, Figure 10 Item 1090, Figure 13A Item 1335) over a Peripheral Component Interconnect Express (PCIe)-based link (Moertl; Figure 1 Item 135, Figure 4 Item 485, Figure 9 Item 985, Col 10 Lines 5 – 7); and circuitry to: receive address translation information from a memory management unit (Moertl; Figure 1 Item 130, Figure 4 Item 482, Figure 9 Item 962, Figure 10 Item 1090, Figure 13A Item 1335), the address translation information comprising virtual memory address to physical memory address translations (Moertl; Col 2 Lines 34 – 40, Col 14 Lines 31 – 35); store the address translation information in the ATC (Moertl; Col 2 Lines 34 – 40, Figure 10 Item 1095, Figure 13A Item 1340); receive a command from the host processor to modify information stored in the ATC (Moertl; Figure 7 Item 710 – 740, Figure 13A Item 1365 – Figure 31B Item 1385, Col 2 Lines 54 – 64, Col 11 Lines 33 – 51); modify the information in the ATC based on the command (Moertl; Figure 7 Item 750, Figure 13B Item 1390, Col 2 Lines 54 – 64, Col 11 Lines 33 – 51). Moertl does not teach a shared work queue (SWQ) associated with the ATC and storing completion information in a memory location indicated by the command. However, Tian teaches a shared work queue (SWQ) associated with an ATC (Tian; Figure 1 Item 169) and storing completion information in a memory location indicated by the command (Tian; Figure 5A “Completion Record Address,” Paragraph [0067]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Moertl to include the SWQ and storing the completion information because doing so allows queuing work of any devices transparent to the type of device to which the command is targeted (Tian; Paragraph [0042]) and providing the status related to the invalidation (Tian; Paragraph [0067]) (See “Response to Arguments” presented above). As per claims 2 and 13, Moertl also teaches wherein the command is an invalidation command indicating an invalidation of address translation information stored in the ATC (Moertl; Col 2 Lines 54 – 64, Col 11 Lines 33 – 51). As per claims 3, 14, and 20, Tian also teaches wherein the command is formatted as an EnqCmdS instruction (Tian; Paragraphs [0057] – [0058]). As per claims 4, 15, and 21, Tian also teaches wherein the command includes an identifier of a process to which the completion is directed (Tian; Figure 5A “Guest PASID”). As per claims 5, 16, and 22, Tian also teaches wherein the command includes an identifier of a process that is associated with invalidation of the address translation information (Tian; Figure 5A “Guest BDF”). As per claims 6, 17, and 23, Tian also teaches wherein the command includes an identifier of a virtual machine associated with the address translation information (Tian; Figure 5A “Host PASID”). As per claims 7, 18, and 24, Tian also teaches wherein the command includes a command type identifier (Tian; Figure 5A “COMMAND”). As per claims 8 and 25, Tian also teaches wherein the processor further comprises a capability register to advertise the SWQ to the host processor (Tian; Paragraph [0048]). As per claim 9, Tian also teaches wherein the capability register comprises fields to indicate one or more of: a number of SWQs of the apparatus, a total number of SWQ entries of the apparatus, one or more SWQ memory locations for guest software of the host to write commands to (Tian; Paragraph [0048]), and a stride between SWQ memory locations. As per claim 12, Moertl teaches a method comprising: receiving, from guest software (Moertl; Figure 4 Item 450, Figure 7 Item 710 – 740, Figure 13A Item 1365 – Figure 31B Item 1385) executing on a host processor (Moertl; Figure 1 Item 110), a command (Moertl; Col 11 Lines 23 – 51) to modify information stored in an address translation cache (ATC) (Moertl; Figure 1 Items 160 – 164, Figure 4 Item 494, Figure 7 Item 710 – 740, Figure 9 Item 992, Figure 13A Item 1365 – Figure 31B Item 1385, Col 2 Lines 54 – 64, Col 11 Lines 33 – 51) (See “Response to Arguments” presented above); modifying the information stored in the ATC based on the command (Moertl; Figure 7 Item 750, Figure 13B Item 1390, Col 2 Lines 54 – 64, Col 11 Lines 33 – 51). Moertl does not teach an accelerator and storing completion information in a memory location indicated by the command. However, Tian teaches an accelerator (Tian; Figure 1 Item 160) and storing completion information in a memory location indicated by the command (Tian; Figure 5A “Completion Record Address,” Paragraph [0067]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Moertl to include storing the completion information because doing so allows relaying status information related to completion of the invalidation (Tian; Paragraph [0067]) (See “Response to Arguments” presented above). As per claim 19, Moertl teaches a system comprising: a memory (Moertl; Figure 1 Item 110); a host processor (Moertl; Figure 1 Item 110); an input/output memory management unit (IOMMU) ((Moertl; Figure 1 Item 130, Figure 4 Item 482, Figure 9 Item 962, Col 1 Lines 20 – 24); a processing device (Moertl; Figure 1 Item 140, Figure 4 Item 490, Figure 9 Item 990) coupled to the host processor and memory via a Peripheral Component Interconnect Express (PCIe)-based link (Moertl; Figure 1 Item 135, Figure 4 Item 485, Figure 9 Item 985, Col 10 Lines 5 – 7), the processing device comprising an address translation cache (ATC) (Moertl; Figure 1 Items 160 – 164, Figure 4 Item 494, Figure 9 Item 992), and a shared work queue (SWQ) corresponding to the ATC (Moertl; Figure 4 Item 498, Col 10 Line 64 – Col 11 Line 13); wherein the processing device is to: receive address translation information from the IOMMU (Moertl; Figure 10 Item 1090, Figure 13A Item 1335, Col 1 Lines 20 – 24) the address translation information comprising virtual memory address to physical memory address translations (Moertl; Col 2 Lines 34 – 40, Col 14 Lines 31 – 35) used by the host processor; store the address translation information in the ATC (Moertl; Col 2 Lines 34 – 40, Figure 10 Item 1095, Figure 13A Item 1340); receive an invalidation command from guest software (Moertl; Figure 4 Item 450, Figure 7 Item 710 – 740, Figure 13A Item 1365 – Figure 31B Item 1385) executing on the host processor (Moertl; Col 2 Lines 54 – 64, Col 11 Lines 33 – 51); modify address translation information stored in the ATC based on the invalidation command (Moertl; Figure 7 Item 750, Figure 13B Item 1390, Col 2 Lines 54 – 64, Col 11 Lines 33 – 51). Moertl does not teach an accelerator and storing completion information in a memory location indicated by the invalidation command. However, Tian teaches an accelerator (Tian; Figure 1 Item 160) and storing completion information in a memory location indicated by the invalidation command (Tian; Figure 5A “Completion Record Address,” Paragraph [0067]). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Moertl to include storing the completion information because doing so allows relaying status information related to completion of the invalidation (Tian; Paragraph [0067]) (See “Response to Arguments” presented above) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 10 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims . 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: Claim 10 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record fails to teach or suggest alone or in combination wherein the capability register comprises, for each SWQ of the apparatus, a field to indicate a set of commands that are supported by the SWQ and a number of entries in the SWQ , as required by dependent claim 10, in combination with the other claimed limitations (emphasis added). The prior art of record teaches a configuration register for the SWQ, but does not teach the specific fields of the configuration register required by dependent claim 10. Claim 11 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record fails to teach or suggest alone or in combination wherein the SWQ is a first SWQ to store commands from one or more guest software applications running on the host processor, and the apparatus further comprises a second SWQ associated with the ATC to store commands from a host software application running on the host processor , as required by dependent claim 11, in combination with the other claimed limitations (emphasis added). The prior art of record teaches a SWQ to store commands from one or more guest software applications running on the host processor, but does not teach a second SWQ associated with the ATC to store commands from a host software application running on the host processor, as required by dependent claim 11 . Conclusion 07-39 AIA THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to RICHARD B FRANKLIN whose telephone number is (571)272-0669. The examiner can normally be reached M-F 8:30am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Idriss Alrobaye can be reached at (571) 270-1023. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RICHARD B FRANKLIN/ Examiner, Art Unit 2181 /IDRISS N ALROBAYE/ Supervisory Patent Examiner, Art Unit 2181 Application/Control Number: 17/951,024 Page 2 Art Unit: 2181 Application/Control Number: 17/951,024 Page 3 Art Unit: 2181 Application/Control Number: 17/951,024 Page 4 Art Unit: 2181 Application/Control Number: 17/951,024 Page 5 Art Unit: 2181 Application/Control Number: 17/951,024 Page 6 Art Unit: 2181 Application/Control Number: 17/951,024 Page 7 Art Unit: 2181 Application/Control Number: 17/951,024 Page 8 Art Unit: 2181 Application/Control Number: 17/951,024 Page 9 Art Unit: 2181 Application/Control Number: 17/951,024 Page 10 Art Unit: 2181
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