DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
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Status of claim(s) to be treated in this office action:
Independent: 1, 15 and 20.
Pending: 1-20.
Information Disclosure Statement
Applicant’s IDS(s) submitted on 3/10/2026 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 7, 8, and 12-14 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sanuki US patent 11839082 B2.
Re: Independent Claim 1, Sanuki discloses a peripheral logic structure (15-19, fig. 1) including a peripheral logic substrate (15-17, fig. 1) and a peripheral logic insulating film (18, fig. 1) on the peripheral logic substrate (15-17, fig. 1); a cell array structure (SL, SGS, WL, SGD, fig. 1) including a cell substrate (SGS, fig. 1) and a source structure (SL, fig. 1) that are sequentially stacked on the peripheral logic structure (15-19, fig. 1); and a first bypass via (most left via 28, fig. 1) directly contacting the cell substrate (SGS, fig. 1) and the peripheral logic substrate (15-17, fig. 1), wherein the first bypass via (most left via 28, fig. 1) has a bar shape, and wherein the first bypass via (most left via 28, fig. 1) has a structure with a single-piece via.
Re: Claim 2, Sanuki disclose(s) all the limitations of claim 1 on which this claim depends. Sanuki further discloses: wherein an upper surface (top tiny flat surface of layer 28) of the first bypass via (most left via 28, fig. 1) extends in a direction parallel to a side surface of the cell substrate (SGS, fig. 1).
Re: Claim 3, Sanuki disclose(s) all the limitations of claim 1 on which this claim depends. Sanuki further discloses: a second bypass via (most right via 28, fig. 1), wherein each of an upper surface (top tiny flat surface of layer 28) of the first bypass via (most left via 28, fig. 1) and an upper surface of the second bypass via (most right via 28, fig. 1) extends in a first direction (X direction, fig. 1), and the first bypass via (most left via 28, fig. 1) and the second bypass via (most right via 28, fig. 1) are spaced apart from each other in a second direction (Z direction, fig. 1).
Re: Claim 4, Sanuki disclose(s) all the limitations of claim 3 on which this claim depends. Sanuki further discloses: wherein a width of the upper surface (top tiny flat surface of layer 28) of the first bypass via (most left via 28, fig. 1) in the second direction (Z direction, fig. 1) is different from a width of the upper surface of the second bypass via (most right via 28, fig. 1) in the second direction (Z direction, fig. 1).
Re: Claim 5, Sanuki disclose(s) all the limitations of claim 1 on which this claim depends. Sanuki further discloses: wherein a width in a first direction (X direction, fig. 1) of an upper surface (top tiny flat surface of layer 28) of the first bypass via (most left via 28, fig. 1) differs from a length in a second direction (Z direction, fig. 1) of the upper surface (top tiny flat surface of layer 28) of the first bypass via (most left via 28, fig. 1).
Re: Claim 7, Sanuki disclose(s) all the limitations of claim 3 on which this claim depends. Sanuki further discloses: wherein the cell array structure (SL, SGS, WL, SGD, fig. 1) includes a stack structure (WL, fig. 1) that includes a plurality of gate electrodes stacked on the cell substrate (SGS, fig. 1); the first bypass via (most left via 28, fig. 1) is disposed on a first side of the stack structure (WL, fig. 1); and the second bypass via (most right via 28, fig. 1) is disposed on a second side of the stack structure (WL, fig. 1), the second side being opposite to the first side.
Re: Claim 8, Sanuki disclose(s) all the limitations of claim 7 on which this claim depends. Sanuki further discloses: wherein the first bypass via (most left via 28, fig. 1) includes a plurality of bypass vias (42 and 36 vias below the most left via 28, fig. 1), which extend in the second direction (Z direction, fig. 1) and are spaced apart from one another in the first direction (X direction, fig. 1); and the second bypass via (most right via 28, fig. 1) includes a plurality of bypass vias (42 and 36 vias below the most left via 28, fig. 1), which extend in the second direction (Z direction, fig. 1) and are spaced apart from one another in the first direction (X direction, fig. 1).
Re: Claim 12, Sanuki disclose(s) all the limitations of claim 1 on which this claim depends. Sanuki further discloses: a third bypass via (middle via 28, fig. 1) disposed on the first side of the stack structure (WL, fig. 1).
Re: Claim 12, Sanuki disclose(s) all the limitations of claim 1 on which this claim depends. Sanuki further discloses: a second bypass via (most right via 28, fig. 1), wherein an upper surface (top tiny flat surface of layer 28) of the first bypass via (most left via 28, fig. 1) and an upper surface of the second bypass via (most right via 28, fig. 1) extend in a first direction (X direction, fig. 1) and spaced apart from each other in the first direction (X direction, fig. 1).
Re: Claim 13, Sanuki disclose(s) all the limitations of claim 12 on which this claim depends. Sanuki further discloses: wherein a length (length of most left 28 has a longer length) in the first direction (X direction, fig. 1) of the upper surface (top tiny flat surface of layer 28) of the first bypass via (most left via 28, fig. 1) differs from a length (length of most right via 28 has a shorter length) in the first direction (X direction, fig. 1) of the upper surface of the second bypass via (most right via 28, fig. 1).
Re: Claim 14, Sanuki disclose(s) all the limitations of claim 1 on which this claim depends. Sanuki further discloses: wherein the first bypass via (most left via 28, fig. 1) is in direct contact with the cell substrate (SGS, fig. 1).
Allowable Subject Matter
Claims 15-19 are allowed.
Re: Independent Claim 15 (and its dependent claim(s) 16-19), the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: a first stack structure (WL, fig. 1) including a plurality of first gate electrodes that are stacked on the source structure; and a first stack structure (WL, fig. 1) including a plurality of first gate electrodes that are stacked on the source structure; and a first bypass via and a second bypass via directly contacting the cell substrate and the peripheral logic substrate, each of the first bypass via and the second bypass via being bar-shaped, wherein a width in a first direction of an upper surface of the first bypass via differs from a width in the first direction of an upper surface of the second bypass via, and wherein each of the first bypass via and the second bypass via has a structure with a single-piece via.
Claim(s) 6, 10 and 11 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re: Claim 6, the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: wherein a length in the first direction of the upper surface of the first bypass via differs from a length in the first direction of the upper surface of the second bypass via.
Re: Claim 10, the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: a fourth bypass via disposed on the second side of the stack structure and spaced apart from the third bypass via.
Re: Claim 11, the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: wherein a sum of an area of the upper surface of the first bypass via and an area of the upper surface of the second bypass via is greater than an area of an upper surface of the third bypass via.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5, 7-9, 12-14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898