Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status
This instant application No. 17/951580 has Claims 1-20 pending.
Priority /Filing Date
Applicant claimed Foreign Priority from Korean Application No. KR10-2021-0162790. The priority filing date of this application is November 23, 2021.
Information Disclosure Statement
As required by M.P.E.P. 609(C), the Applicant’s submissions of the Information Disclosure Statements dated September 23, 2022 is acknowledged by the Examiner and the cited references have been considered in the examination of the claims now pending. As required by M.P.E.P. 609 C(2), a copy of each of the PTOL-1449s initialed and dated by the Examiner is attached to the instant Office action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1-20 are rejected under 35 U.S.C. 103 as being obvious over Hua-Yu LIU, hereafter Liu (Pub. No.: US 2013/0311958 A1), in view of Xu et al. hereafter Xu (Pub. No.: US 2008/0066023 A1).
Regarding Claim 1, Liu disclose a manufacturing method comprising:
designing a full-chip layout (Liu: Figure 2, Figure 3, [0045], [0047]: Full chip SMO; Note that the design layout module 26, which defines the target design; Also note that a target design 300 (typically comprising a layout in a standard digital format such as OASIS, GDSII, etc.));
extracting a representative pattern from the full-chip layout (Liu: Figure 3, [0047]: From this design, a full set of clips 302 is extracted, which represents all the complicated patterns in the design 300 (typically about 50 to 1000 clips).);
verifying (Liu: [0054], [0055], [0056]: full pattern simulation based manufacturability verification is performed with the optimized source 314 and the full set of clips 316 as corrected in 318);
(Liu: [0011], [0012], [0044]: In a typical high-end design almost every feature edge requires some modification in order to achieve printed patterns that come sufficiently close to the target design. These modifications may include shifting or biasing of edge positions or line widths as well as application of 'assist' features that are not intended to print themselves, but will affect the properties of an associated primary feature); and
forming at least one of a mask and a semiconductor chip in response to analysis of the modified full-chip layout (Liu: Figure 3, [0018], [0045], [0051], [0055]: The optimized source is then used to optimize the mask ( e.g. using OPC and LMC) for the full chip; If the verification in 310 is satisfactory, as determined in 312, then processing advances to full chip optimization in 314; Qualified source for full chip(328)).
Liu do not explicitly disclose:
detecting a stress weak point in the representative pattern by performing a simulation.
Xu disclose:
detecting a stress weak point in the representative pattern by performing a simulation (Xu: [0040]- [0044]: a 2-dimensional stress analysis considers only the tensor stress components acting in-plane, on a 2-dimensional (planar) region; region of high 2-dimensional stress);
Liu and Xu are analogous art because they are from the same field of endeavor. They both relate to semiconductor manufacturing.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the above lithographic application, as taught by Liu, and incorporating the use of high stress identification technique, as taught by Xu.
One of ordinary skill in the art would have been motivated to do this modification in order to provide fast techniques for identifying high-stress regions., as suggested by Xu (Xu: [0001]).
Regarding Claims 11 and 16, the claims recite the same substantive limitations as Claim 1 and are rejected using the same teachings.
Regarding Claim 2, the combinations of Liu and Xu further disclose the manufacturing method of claim 1, wherein the extracting of the representative pattern comprises: extracting the representative pattern by identifying a pattern in the full-chip layout that is repeated in the full-chip layout as the representative pattern (Liu: Figure 3, [0045]-[0047]: the invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in SMO. SMO is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask ( e.g. using OPC and LMC) for the full chip).
Regarding Claim 3, the combinations of Liu and Xu further disclose the manufacturing method of claim 1, wherein the extracting of the representative pattern comprises: receiving an input of the full-chip layout (Liu: [0047]: A target design 300 (typically comprising a layout in a standard digital format such as OASIS, GDSII, etc.)); and extracting a unique pattern as the representative pattern and storing the unique pattern using a hash code, wherein the unique pattern is a pattern of the full-chip layout that has not been previously identified (Liu: Figure 3, [0045]-[0047]: the invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in SMO. SMO is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask ( e.g. using OPC and LMC) for the full chip).
Regarding Claim 12, the claim recites the same substantive limitations as Claim 3 and is rejected using the same teachings.
Regarding Claim 4, the combinations of Liu and Xu further disclose the manufacturing method of claim 1, wherein the extracting of the representative pattern uses a pattern matching method of comparing a previously identified pattern to the full-chip layout and extracting a corresponding pattern as the representative pattern (Liu: Figure 3, [0045]-[0047]: the invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in SMO. SMO is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask ( e.g. using OPC and LMC) for the full chip, and the results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result.).
Regarding Claim 17, the claim recites the same substantive limitations as Claim 4 and is rejected using the same teachings.
Regarding Claim 5, the combinations of Liu and Xu further disclose the manufacturing method of claim 1, wherein the detecting of the stress weak point comprises detecting the stress weak point based on a stress simulation using a finite element method (FEM) (Xu: [0042], [0050], [0078]: performing a finite element analysis to determine the three 2-dimensional stress components in each polygon defined by the mesh polygons).
Motivation to combine Liu and Xu are same here as Claim 1.
Regarding Claim 6, the combinations of Liu and Xu further disclose the manufacturing method of claim 5, wherein the detecting of the stress weak point further comprises:
converting a two-dimensional representation of the representative pattern into a three-dimensional representation of the representative pattern (Xu: Figure 3, [0072], [0078]-[0080]: the portion of the layout layer information that bears on the current volume is converted into a 3-dimensional description of structures within the current volume. This conversion takes into account the 2-dimensional shapes and sizes of elements in each of the layout layers that affect the structures that will ultimately be formed in the current volume…);
setting a physical property and a process condition with respect to the three- dimensional representation of the representative pattern (Xu: Figure 3, Figure 10, [0078]-[0082]: 3-dimensional polyhedron mesh is imposed on the current volume. Preferably the mesh has variable density, with the mesh increasing in polyhedron density near corners and walls of the 3-dimensional structure);
generating a mesh for FEM analysis that divides the three-dimensional representation of the representative pattern into cells (Xu: Figure 3, Figure 10, [0078]-[0082]: for analyzing the 3-dimensional stress in the current volumetric region, can be performed using any conventional or yet-to-be-developed method. Since the regions are small and their number has been limited by the 2-dimensional filtering above, a full fledged finite element analysis can be used; 3-dimensional polyhedron mesh is imposed on the current volume. Preferably the mesh has variable density, with the mesh increasing in polyhedron density near corners and walls of the 3-dimensional structure); and
performing the stress simulation using the FEM (Xu: Figure 3, Figure 10, [0078]-[0082]: The 3-dimensional description developed in step 1010 is set up for numerical solution for this system of equations with proper boundary conditions, again taking into account the stress propagation characteristics of the particular materials to be used. The system of equations is then solved numerically, yielding values for the six 3-dimensional stress components, σxx, σxy, σxz, σyy, σyz, and σzz for each polyhedron in the mesh).
Motivation to combine Liu and Xu are same here as Claim 1.
Regarding Claims 13 and 18, the claims recite the same substantive limitations as Claim 6 and is rejected using the same teachings.
Regarding Claim 7, the combinations of Liu and Xu further disclose the manufacturing method of claim 1, wherein the changing of the design rule with respect to the full-chip layout comprises changing the design rule with respect to the full-chip layout by performing optimization of a shape or a topology of the full-chip layout by using a shape optimization method (Xu: Figure 3, [0045], [0051], Figure 9, [0074]: If the averaging of the stress determined for nearby polygons in step 314 considered polygons within a circle of radius r centered at the center of the subject polygon, then the lateral size and shape of the volumetric region identified in step 320 for that subject polygon might be a circle of radius of 5 r centered at the center of the subject polygon).
Motivation to combine Liu and Xu are same here as Claim 1.
Regarding Claim 19, the claim recites the same substantive limitations as Claim 7 and is rejected using the same teachings.
Regarding Claim 8, the combinations of Liu and Xu further disclose the manufacturing method of claim 7, wherein the shape optimization method changes the shape or the topology of the full-chip layout so that stress of the stress weak point is reduced to be less than or equal to a set reference stress value (Xu: Figure 3, [0045], [0051], Figure 9, [0074]: The heavy black line 918 thus indicates the shape of the region where stress is actually averaged in this example, and while it is not square, its area should be roughly equal to the area of the square 912).
Motivation to combine Liu and Xu are same here as Claim 1.
Regarding Claim 14, the claim recites the same substantive limitations as Claim 8 and is rejected using the same teachings.
Regarding Claim 9, the combinations of Liu and Xu further disclose the manufacturing method of claim 1, wherein the verifying the stress weak point by forming the pattern on the wafer comprises:
generating an initial mask based on the full-chip layout (Liu: Figure 2, [0042]: Referring to FIG. 2, the functional modules include the design layout module 26, which defines the target design; the mask layout module 28, which defines the mask to be utilized in the imaging process; the mask model module 30, which defines the model of the mask layout to be utilized during the simulation process);
forming the pattern on the wafer by using the initial mask (Liu: Figure 3, [0045]-[0047]: the invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in SMO. SMO is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask ( e.g. using OPC and LMC) for the full chip); and
detecting the pattern on the wafer with a scanning electron microscope (SEM) (Liu: [0003]: In an alternative apparatus, commonly referred to as a step-and-scan apparatus, each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the "scanning" direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction; Examiner’s Remark(ER): scanning electron microscope is the obvious choice in this case; Also see [0006] and [0007]).
Regarding Claims 15 and 20, the claims recite the same substantive limitations as Claim 9 and are rejected using the same teachings.
Regarding Claim 10, the combinations of Liu and Xu further disclose the manufacturing method of claim 1, further comprising analyzing the modified full-chip layout including extracting a representative pattern from the modified full-chip layout and performing a simulation to evaluate the existence of a stress weak point in the representative pattern of the modified full-chip (Liu: Figure 3, [0045]-[0047]: the invention enables full chip pattern coverage while lowering the computation cost by intelligently selecting a small set of critical design patterns from the full set of clips to be used in SMO. SMO is performed only on these selected patterns to obtain an optimized source. The optimized source is then used to optimize the mask ( e.g. using OPC and LMC) for the full chip, and the results are compared. If the results are comparable to conventional full-chip SMO, the process ends, otherwise various methods are provided for iteratively converging on the successful result).
Conclusion
6. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Victor MOROZ (Pub. No.: US 2020/0184136 A1) teaches technology for placing cells in a circuit design layout to thereby improve the operation of place-and route equipment used for fabrication of an integrated circuit.
Wangxiao et al. (Pub. No.: US 2008/0216041 A1) teaches an integrated circuit (IC) simulation method which can predict the operation and performance of an IC considering stress effects that affect the characteristics of unit devices included in the IC.
Hu et al. (Pub. No.: US 20200097621 A1) conceptually presents a system, that comprises a processor that is provided to decompose a layout of a semiconductor chip into multiple intended circuit layout patterns.
Mallik et al. (Simulation of Process-Stress Induced Warpage of Silicon Wafers Using ANSYS® Finite Element Analysis, 2010, IMAPS, pp 364-371) defines the notion of thermal network associated to an electric circuit where the definition of the temperatures of the elements of the electric circuit and of the power densities they dissipate are deduced.
7. Examiner’s Remarks: Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Correspondence Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IFTEKHAR A KHAN whose telephone number is (571)272-5699. The examiner can normally be reached on M-F from 9:00AM-6:00PM (CST). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Emerson Puente can be reached on (571)272-3652. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/IFTEKHAR A KHAN/Primary Examiner, Art Unit 2187