DETAILED ACTION
This office action is in response to the application filed on 09/23/2022.
Claims 1-20 are pending in the application and have been examined.
Claim Objections
Claim 1 is objected to because of the following informalities: claim 1 recites “sequences of instructions” in line 4 and should recite “one or more instruction sequences” to be consistent with the language in lines 5-6. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 7-12, and 16-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsumura (Design and Evaluation of an Auto-Memoization Processor).
Regarding claims 1, 10, and 17, Tsumura discloses an apparatus comprising: one or more processor cores configured to execute instructions [section 1]; and hardware-based logic to, detect loops in sequences of instructions [section 1; the system detects loop iterations]; memoize one or more loops that are repeated during execution of the one or more instruction sequences [section 2.1; the system memoizes loops]; predict an instance of a loop in an instruction sequence is a memoized loop [sections 2.1, 2.3; the system detects a match between executing code and a memoized loop; the system does this first my using an address to predict a possible match, and then confirming the match by comparing other data related to the loop]; and for the predicted instance of the memoized loop, remove instructions in the predicted instance of the memoized loop from the instruction sequence [section 2.1; in response to detecting a matching memoized loop, the system omits the execution of those instructions]; determine input data loaded into input registers at a start of the loop are the same as in previous instances of the memoized loop [section 2.1; the system compares inputs of the executing instructions to the inputs of the memoized loop]; and when the input data are the same, continue execution of instructions in the instruction sequence [section 2.1; when the input matches, the loop instructions are omitted and execution continues].
Regarding claims 2, 11, and 18, Tsumura discloses the apparatus of claim 1, wherein the hardware-based logic is further configured to: store an output context for the memoized loop comprising output register values upon completion of the loop and memory loads and/or stores and their order performed via execution of the memoized loop [section 2; the system stores an output context associated with the memoized loop]; and reproduce the output context of the memoized loop as if the instructions in the memoized loop had been executed [section 2; the system outputs the stored output context instead of executing the loop].
Regarding claims 3, 12, and 19, Tsumura discloses the apparatus of claim 1, wherein the apparatus further comprises: a loop memoization table configured to store a plurality of entries, each entry containing information pertaining to a respective memoized loop [section 2; the system uses a table to store data pertaining to memoized loops] including, a loop start program counter (PC) [section 2; Figure 4; the table includes a PC that represents the start address of the memoizable region]; an input register signature comprising a set of input register values when the loop begins [section 2; Figure 4; the table includes a set of input register values]; and an output register signature comprising a set of output register values when the loop is completed [section 2, Figure 4; the table includes a set of output register values associated with a set of input values].
Regarding claims 7 and 16, Tsumura discloses the apparatus of claim 1, further comprising a post-retirement Uop buffer [section 2, Figure 2; the system includes a buffer and a table for storing loop instructions after they have been executed], wherein the hardware-based logic is further configured to: write retired Uops to the post-retirement Uop buffer [section 2, Figure 2; the buffer and table store values of instructions that have been executed]; inspect retired Uops in the post-retirement Uop buffer to identify loops that are repeated [section 2; the system detects loops of instructions]; and identify repeated loops that are candidates for memoization [section 2; the loops are memoized].
Regarding claim 8, Tsumura discloses the apparatus of claim 7, wherein the loops are identified as being repeated, at least in part, by tracking back branch program counters [section 2.1; a system detects a loop by detecting a back branch instruction and its branch target].
Regarding claim 9, Tsumura discloses the apparatus of claim 1, further comprising a memoize context buffer that is used to track input and output values through registers and loads/stores and an order in which they occur when a memoized loop is executed [section 2; the inputs and outputs of a loop are tracked, including their order].
Allowable Subject Matter
Claims 4-6, 13-15, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Corey Faherty whose telephone number is (571)270-1319. The examiner can normally be reached weekdays between 7:30 and 4:00 ET, with every other Friday off.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached at (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/COREY S FAHERTY/Primary Examiner, Art Unit 2183