DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Specification. The objection to the specification is withdrawn based on amendment to the specification.
Claim Objections. The objections to the claims are withdrawn based on amendment to claims.
35 USC 112(b). The rejections to claims 1-31 are withdrawn based on amendment to claims. However, see new rejections of claims 18-31 necessitated by amendment.
35 USC 103.
Applicant asserts that the Song reference cannot be prior art to the claimed invention under 35 USC 102(a)(2) because the effective filing date of the claimed invention, January 7, 2020 or January 17, 2020, the filing dates of US 62958223 and KR 1020200006902 predate the earliest publication dates of the Song reference, July 8, 2021.
Examiner respectfully disagrees. The claim of benefit is based on a continuation in part, and limitations in claim 1, and claim 18, at least wherein the first MAC operator is configured to perform an element-wise multiplication (EWM) operation and to generate multiplication result data and transmitting the multiplication result data to a third memory bank of the plurality of memory banks having not been disclosed in the above referenced earlier references to which benefit is being claimed. As Applicant has not refuted finding, the statement as to priority and the rejection stands.
Applicant further asserts that under 35 USC 102(a)(2), the Song reference cannot be prior art because the Song reference and the present application are owned by the applicant and have been owned by the applicant before, at the time of, and after the effective filing data of the present application.
Examiner respectfully disagrees. The Song reference was published on July 8, 2021. The present application was filed on 26 September, 2022. Under 35 USC 102(a)(1) no patent may be granted on a claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Furthermore the Song reference is beyond the one year grace period of the present application under 35 USC 102(b).
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. With respect to claims 13-18, Applicant has not complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C. 120 as follows:
The later-filed application must be an application for a patent for an invention which is also disclosed in the prior application (the parent or original nonprovisional application or provisional application). The disclosure of the invention in the parent application and in the later-filed application must be sufficient to comply with the requirements of 35 U.S.C. 112(a) or the first paragraph of pre-AIA 35 U.S.C. 112, except for the best mode requirement. See Transco Products, Inc. v. Performance Contracting, Inc., 38 F.3d 551, 32 USPQ2d 1077 (Fed. Cir. 1994).
The disclosure of the prior-filed application, Application No. 17090462, fails to provide adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this application. The prior-filed application does not disclose, is silent with respect to, at least wherein the first MAC operator is configured to perform an element-wise multiplication (EWM) operation and to generate multiplication result data and transmitting the multiplication result data to a third memory bank of the plurality of memory banks, and as in claims 1-31. Furthermore the prior-filed application does not disclose, is silent with respect to at least a write global data input/output (GIO) line capable of providing a data transmission path from the data input/output (I/O) circuit to the plurality of memory banks and the plurality of MAC operators; and a read GIO line capable of providing a data transmission path from the data input/output (I/O) circuit to the plurality of memory banks and the plurality of MAC operators as in claims 18-31.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 18-31 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 line 6 recites “a global data input/output (GIO) line”. It is not clear whether “input/output” refers to input or output, or input and output. For purposes of examination, Examiner interprets as input and output. Claims 19-31 inherit the same deficiency as claim 18 based on dependence.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over US 20210208884 A1 Song (hereinafter “Song”) in view of D. Kwon et al., A 1 ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application, IEEE Journal of Solid-State Circuits, Vol. 58, No. 1, 2023 (date of publication 9 Sept 2022) (hereinafter “Kwon”) in view of US 20200026498 A1 Sumbul et al., (hereinafter “Sumbul”).
Regarding claim 1, Song teaches the following:
a memory and arithmetic region including a plurality of memory banks and a plurality of multiplication-and-accumulation (MAC) operators, the plurality of MAC operators including a first MAC operator (fig 2 120, fig 4, MAC operator);
a peripheral region including a data input/output (I/O) circuit (fig 1-131); and
a global data input and output (GIO) line capable of providing a data transmission path between the peripheral region and the memory/arithmetic region ([0106] GIO, [0082-0083] the GIO is in a transmission path with I/F, DQ for peripheral region, as such is capable of providing a transmission path between the peripheral region and the memory/arithmetic region)
wherein the first MAC operator is configured to perform an element-wise multiplication (EWM) operation by performing a multiplication operation on first input data and second input data that are transmitted from first and second memory banks of the plurality of memory banks, respectively, to generate multiplication result data ([0110], fig 5 for EWM, fig 2 [0083], fig 7, fig 8, [0106-0107] for performing a multiplication operation on first input data and second input data that are transmitted from first and second memory banks of the plurality of memory banks respectively, [0093], [0111-0113] for generate multiplication result data).
Song discloses a MAC unit comprising a first memory bank and a second memory bank, and further discloses the PIM device may include a plurality of MAC units ([0083]). Song also further discloses a latch for controlling data into and results from the arithmetic circuit ([0081], [0092-0093]). Song does not, however, explicitly disclose transmitting the multiplication result data to a third memory bank of the plurality of memory bands or wherein, while the EWM operation is being performed, data transmission through the GIO line between the peripheral region and the memory and arithmetic region is blocked.
However, in the same field of endeavor, Kwon discloses an apparatus similar to Song comprising processing in memory including bank-parallel memory and arithmetic processing units performing MAC operations including elementwise multiplication (Introduction, fig 1, fig 2(c)). Kwon further discloses transmitting the multiplication result data to a third memory bank of the plurality of memory banks (fig 2(c)). It would have been obvious to one of ordinary skill in the art before the effective filing date use the existing structure of Song comprising adjacent memory banks among Song’s plurality of MAC unit to transmit the multiplication data to a third memory bank among the plurality of memory banks as in Kwon. It would have been obvious to achieve the performance improvement of bank-level parallelism (Kwon Section V.D). Therefore Song in view of Kwon teaches transmitting the multiplication result data to a third memory bank of the plurality of memory banks.
Song in view of Kwon does not explicitly disclose wherein, while the EWM operation is being performed, data transmission through the GIO line between the peripheral region and the memory and arithmetic region is blocked. However, in the same field of endeavor, Sumbul discloses an apparatus similar to Song comprising a compute in memory circuit (CIM) including a number of MAC circuits (abstract). Sumbul further discloses an enable signal that controls multiplexers controlling input data and addressing data to arithmetic and memory region of the CIM device (fig 2 216 to 214, 222, [0056-0065] sending only one element per cycle). It would have been obvious to one of ordinary skill in the art before the effective filing date to include the enable control circuit and multiplexers as in Sumbul in the GIO line of Song, to block data transmission through the GIO line between the peripheral region and the memory/arithmetic region while the EWM is being performed to achieve the benefit of avoiding data collision while the EWM operation is being performed (Sumbul [0064]). Therefore, Song in view of Kwon in view of Sumbul teaches wherein, while the EWM operation is being performed, data transmission through the GIO line between the peripheral region and the memory and arithmetic region is blocked.
Regarding claim 18, Song teaches the following:
a memory and arithmetic region including a plurality of memory banks and a plurality of multiplication-and-accumulation (MAC) operators, the plurality of MAC operators including a first MAC operator (fig 2 120, fig 4, MAC operator);
a peripheral region including a data input and output (I/O) circuit (fig 1-131); and
a global data input/output (GIO) line, the GIO line including:
a data (GIO) line capable of providing a data transmission path from the data input and output (I/O) circuit to the plurality of memory banks and the plurality of MAC operators ([0106] GIO, [0082-0083] the GIO is in a transmission path with I/F, DQ for data input/output circuit, as such is capable of providing a transmission path between the data input/output (I/O) circuit and plurality of memory banks and the plurality of MAC operators)
wherein the first MAC operator is configured to perform an element-wise multiplication (EWM) operation by performing a multiplication operation on first input data and second input data that are transmitted from first and second memory banks of the plurality of memory banks, respectively, to generate multiplication result data ([0110], fig 5 for EWM, fig 2 [0083], fig 7, fig 8, [0106-0107] for performing a multiplication operation on first input data and second input data that are transmitted from first and second memory banks of the plurality of memory banks respectively, [0093], [0111-0113] for generate multiplication result data).
Song discloses a MAC unit comprising a first memory bank and a second memory bank, and further discloses the PIM device may include a plurality of MAC units ([0083]). Song also further discloses a latch for controlling data into and results from the arithmetic circuit ([0081], [0092-0093]). Song also further discloses a GIO line capable of providing a data transmission path from the data input and output (I/O) circuit to the plurality of memory banks and the plurality of MAC operators. Song does not, however, explicitly disclose transmitting the multiplication result data to a third memory bank of the plurality of memory bands or wherein, while the EWM operation is being performed, data transmission through the GIO line between the peripheral region and the memory/arithmetic region is blocked, or wherein the GIO line comprises separate write and read global lines capable of providing a data transmission path from the data input and output (I/O) circuit to the plurality of memory banks and the plurality of MAC operators.
However, in the same field of endeavor, Kwon discloses an apparatus similar to Song comprising processing in memory including bank-parallel memory and arithmetic processing units performing MAC operations including elementwise multiplication (Introduction, fig 1, fig 2(c)). Kwon further discloses transmitting the multiplication result data to a third memory bank of the plurality of memory banks (fig 2(c)). It would have been obvious to one of ordinary skill in the art before the effective filing date use the existing structure of Song comprising adjacent memory banks among Song’s plurality of MAC unit to transmit the multiplication data to a third memory bank among the plurality of memory banks as in Kwon. It would have been obvious to achieve the performance improvement of bank-level parallelism (Kwon Section V.D). Furthermore, Kwon further discloses a write global data input/output (GIO) line capable of providing a data transmission path from the data input/output (I/O) circuit to the plurality of memory banks and the plurality of MAC operators; and a read GIO line capable of providing a data transmission path from the data input/output (I/O) circuit to the plurality of memory banks and the plurality of MAC operators (fig 2(d), 2(e)). It would have been obvious to one of ordinary skill in the art before the effective filing data for Song to implement the GIO using separate read and write GIO to achieve the benefit of efficient read and write wherein the bandwidths of each operation is different (Section III.C. last paragraph). Therefore Song in view of Kwon teaches transmitting the multiplication result data to a third memory bank of the plurality of memory banks, and a write global data input/output (GIO) line capable of providing a data transmission path from the data input and output (I/O) circuit to the plurality of memory banks and the plurality of MAC operators; and a read GIO line capable of providing a data transmission path from the data input/output (I/O) circuit to the plurality of memory banks and the plurality of MAC operators.
Song in view of Kwon does not explicitly disclose wherein, while the EWM operation is being performed, data transmission through the GIO line between the peripheral region and the memory/arithmetic region is blocked. However, in the same field of endeavor, Sumbul discloses an apparatus similar to Song comprising a compute in memory circuit (CIM) including a number of MAC circuits (abstract). Sumbul further discloses an enable signal that controls multiplexers controlling input data and addressing data to arithmetic and memory region of the CIM device (fig 2 216 to 214, 222, [0056-0065] sending only one element per cycle). It would have been obvious to one of ordinary skill in the art before the effective filing date to include the enable control circuit and multiplexers as in Sumbul in the GIO line of Song, to block data transmission through the GIO line between the peripheral region and the memory/arithmetic region while the EWM is being performed to achieve the benefit of avoiding data collision while the EWM operation is being performed (Sumbul [0064]). Therefore, Song in view of Kwon in view of Sumbul teaches wherein, while the EWM operation is being performed, data transmission through the GIO line between the peripheral region and the memory and arithmetic region is blocked.
Allowable Subject Matter
For the reasons set forth in the office action dated 02/06/26, claims 2-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 19-31 would be allowable if rewritten in in independent form including all of the limitations of the base claim and any intervening claims, and further rewritten to overcome the rejections under 35 USC 112(b).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EMILY E LAROCQUE whose telephone number is (469)295-9289. The examiner can normally be reached on 10:00am - 1200pm, 2:00pm - 8pm ET M-F.
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/EMILY E LAROCQUE/Examiner, Art Unit 2182
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