DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. With respect to claims 13-18, Applicant has not complied with one or more conditions for receiving the benefit of an earlier filing date under 35 U.S.C. 120 as follows:
The later-filed application must be an application for a patent for an invention which is also disclosed in the prior application (the parent or original nonprovisional application or provisional application). The disclosure of the invention in the parent application and in the later-filed application must be sufficient to comply with the requirements of 35 U.S.C. 112(a) or the first paragraph of pre-AIA 35 U.S.C. 112, except for the best mode requirement. See Transco Products, Inc. v. Performance Contracting, Inc., 38 F.3d 551, 32 USPQ2d 1077 (Fed. Cir. 1994).
The disclosure of the prior-filed application, Application No. 17090462, fails to provide adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this application: claim 13 - claim 18. The prior-filed application does not disclose, is silent with respect to, at least wherein the first MAC operator is configured to perform an element-wise multiplication (EWM) operation and to generate multiplication result data and transmitting the multiplication result data to a third memory bank of the plurality of memory banks, and as in claims 1-31. Furthermore the prior-filed application does not disclose, is silent with respect to at least a write global data input/output (GIO) line capable of providing a data transmission path from the data input/output (I/O) circuit to the plurality of memory banks and the plurality of MAC operators; and a read GIO line capable of providing a data transmission path from the data input/output (I/O) circuit to the plurality of memory banks and the plurality of MAC operators as in claims 18-31.
Specification
The disclosure is objected to because of the following informalities. Pages 80-81 of the specification uses reference designator 630 to refer to both the “memory/arithmetic regions 610 and 630” and “a GIO line 630”.
Appropriate correction is required.
Claim Objections
Claims 26-31 are objected to because of the following informalities.
Claim 26 line 7 recites “a second write GIO lines”. This appears to include a typographical error and should possible recite “a second write GIO line”. Claims 27-31 inherit the same deficiency as claim 26 based on dependence.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-31 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18, line 2, last line recite “a memory/arithmetic region”, “the memory/arithmetic region”. It is not clear whether “memory/arithmetic region” refers to a memory region or an arithmetic region or a memory region and an arithmetic region. For purposes of examination, Examiner interprets as a memory region and an arithmetic region. Claims 19-31 inherit the same deficiency as claim 18 based on dependence. Claims 26, 27 also recite “the memory/arithmetic region” and are rejected for the same reason. Claims 27-31 inherit the same deficiency as claim 26 based on dependence. Claims 28-31 inherit the same deficiency as claim 27 based on dependence.
Claim 1, line 5 recites “a data input/output (I/O) circuit”. It is not clear whether “input/output” refers to input or output or input and output. For purposes of examination, Examiner interprets as input and output. Claims 2-17 inherit the same deficiency as claim 1 based on dependence. Claim 14 also recites “the data I/O circuit” and is rejected for the same reason. Claim 15 inherits the same deficiency as claim 14 based on dependence.
Claim 18, line 5, and line 11 recite “a data input/output (I/O) circuit”, “the data input/output (I/O) circuit”. It is not clear whether “input/output” refers to input or output or input and output. For purposes of examination, Examiner interprets as input and output. Claims 19-31 inherit the same deficiency as claim 18 based on dependence. Claim 26, claim 27 also recite “the data I/O circuit” and is rejected for the same reason. Claims 27-31 inherit the same deficiency as claim 26 based on dependence. Claims 28-31 inherit the same deficiency as claim 27 based on dependence.
Claim 18, line 6, and line 20, claim 26 line 1, line 3, line 7, line 11, line 12, claim 28 line 3, line 7 recite “a write global data input/output (GIO) line”, “the write GIO line”, “a first write GIO line”, “a second write GIO lines” “a third write GIO line”. It is not clear whether “input/output” refers to input or output or input and output. For purposes of examination, Examiner interprets as input and output. Claims 19-31 inherit the same deficiency as claim 18 based on dependence. Claims 21-22 inherit the same deficiency as claim 20 based on dependence. Claim 26, claim 27 also recite “the data I/O circuit” and is rejected for the same reason. Claims 27-31 inherit the same deficiency as claim 26 based on dependence. Claims 29-31 inherit the same deficiency as claim 28 based on dependence.
Claim 18, line 9. and line 20, claim 27 line 1, line 3, line 7, line 11, line 12, claim 28 line 4, line 8 recite “a read GIO line”, “the read GIO line”, “a first read GIO line”, “a second read GIO line” “a third read GIO line”. It is not clear whether “input/output” refers to input or output or input and output. For purposes of examination, Examiner interprets as input and output. Claims 19-31 inherit the same deficiency as claim 18 based on dependence. Claims 21-22 inherit the same deficiency as claim 20 based on dependence. Claim 26, claim 27 also recite “the data I/O circuit” and is rejected for the same reason. Claims 27-31 inherit the same deficiency as claim 26 based on dependence. Claims 29-31 inherit the same deficiency as claim 28 based on dependence.
Claim 21 last line recites “the GIO line”. This limitation lacks antecedent basis. It is unclear whether the GIO line refers to the read GIO line, the write GIO line or both the read and write GIO line. For purposes of examination, Examiner interprets as the write GIO line. Claim 22 inherits the same deficiency as claim 21 based on dependence.
Claim 11 lines 1-2, claim 12 lines 1-2, claim 13 lines 1-2, claim 14 lines 1-2, claim 15 lines 1-2, claim 16 lines 1-2, recite “a command/address decoder”, “the command/address decoder”. It is not clear whether “command/address” refers to command or address or command and address. For purposes of examination, Examiner interprets as command and address. Claims 12-17 inherit the same deficiency as claim 1 based on dependence. Claim 15 inherits the same deficiency as claim 14 based on dependence. Claim 17 inherits the same deficiency as claim 16 based on dependence.
Claim 29 lines 1-2, line 5, claim 29 lines 1-2 recite “a command/address decoder”, “the command/address decoder”. It is not clear whether “command/address” refers to command or address or command and address. For purposes of examination, Examiner interprets as command and address. Claims 30-31 inherit the same deficiency as claim 29 based on dependence.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, and 13-18 are rejected under 35 U.S.C. 103 as being unpatentable over US 20210208884 A1 Song (hereinafter “Song”) in view of D. Kwon et al., A 1 ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application, IEEE Journal of Solid-State Circuits, Vol. 58, No. 1, 2023 (date of publication 9 Sept 2022) (hereinafter “Kwon”) in view of US 20200026498 A1 Sumbul et al., (hereinafter “Sumbul”).
Regarding claim 1, Song teaches the following:
a memory/arithmetic region including a plurality of memory banks and a plurality of multiplication-and-accumulation (MAC) operators, the plurality of MAC operators including a first MAC operator (fig 2 120, fig 4, MAC operator);
a peripheral region including a data input/output (I/O) circuit (fig 1-131); and
a global data input/output (GIO) line capable of providing a data transmission path between the peripheral region and the memory/arithmetic region ([0106] GIO, [0082-0083] the GIO is in a transmission path with I/F, DQ for peripheral region, as such is capable of providing a transmission path between the peripheral region and the memory/arithmetic region)
wherein the first MAC operator is configured to perform an element-wise multiplication (EWM) operation by performing a multiplication operation on first input data and second input data that are transmitted from first and second memory banks of the plurality of memory banks, respectively, to generate multiplication result data ([0110], fig 5 for EWM, fig 2 [0083], fig 7, fig 8, [0106-0107] for performing a multiplication operation on first input data and second input data that are transmitted from first and second memory banks of the plurality of memory banks respectively, [0093], [0111-0113] for generate multiplication result data).
Song discloses a MAC unit comprising a first memory bank and a second memory bank, and further discloses the PIM device may include a plurality of MAC units ([0083]). Song also further discloses a latch for controlling data into and results from the arithmetic circuit ([0081], [0092-0093]). Song does not, however, explicitly disclose transmitting the multiplication result data to a third memory bank of the plurality of memory bands or wherein, while the EWM operation is being performed, data transmission through the GIO line between the peripheral region and the memory/arithmetic region is blocked.
However, in the same field of endeavor, Kwon discloses an apparatus similar to Song comprising processing in memory including bank-parallel memory and arithmetic processing units performing MAC operations including elementwise multiplication (Introduction, fig 1, fig 2(c)). Kwon further discloses transmitting the multiplication result data to a third memory bank of the plurality of memory banks (fig 2(c)). It would have been obvious to one of ordinary skill in the art before the effective filing date use the existing structure of Song comprising adjacent memory banks among Song’s plurality of MAC unit to transmit the multiplication data to a third memory bank among the plurality of memory banks as in Kwon. It would have been obvious to achieve the performance improvement of bank-level parallelism (Kwon Section V.D). Therefore Song in view of Kwon teaches transmitting the multiplication result data to a third memory bank of the plurality of memory banks.
Song in view of Kwon does not explicitly disclose wherein, while the EWM operation is being performed, data transmission through the GIO line between the peripheral region and the memory/arithmetic region is blocked. However, in the same field of endeavor, Sumbul discloses an apparatus similar to Song comprising a compute in memory circuit (CIM) including a number of MAC circuits (abstract). Sumbul further discloses an enable signal that controls multiplexers controlling input data and addressing data to arithmetic and memory region of the CIM device (fig 2 216 to 214, 222, [0056-0065] sending only one element per cycle). It would have been obvious to one of ordinary skill in the art before the effective filing date to include the enable control circuit and multiplexers as in Sumbul in the GIO line of Song, to block data transmission through the GIO line between the peripheral region and the memory/arithmetic region while the EWM is being performed to achieve the benefit of avoiding data collision while the EWM operation is being performed (Sumbul [0064]). Therefore, Song in view of Kwon in view of Sumbul teaches wherein, while the EWM operation is being performed, data transmission through the GIO line between the peripheral region and the memory/arithmetic region is blocked.
Regarding claim 18, Song teaches the following:
a memory/arithmetic region including a plurality of memory banks and a plurality of multiplication-and-accumulation (MAC) operators, the plurality of MAC operators including a first MAC operator (fig 2 120, fig 4, MAC operator);
a peripheral region including a data input/output (I/O) circuit (fig 1-131); and
a data input/output (GIO) line capable of providing a data transmission path from the data input/output (I/O) circuit to the plurality of memory banks and the plurality of MAC operators ([0106] GIO, [0082-0083] the GIO is in a transmission path with I/F, DQ for data input/output circuit, as such is capable of providing a transmission path between the data input/output (I/O) circuit and plurality of memory banks and the plurality of MAC operators)
wherein the first MAC operator is configured to perform an element-wise multiplication (EWM) operation by performing a multiplication operation on first input data and second input data that are transmitted from first and second memory banks of the plurality of memory banks, respectively, to generate multiplication result data ([0110], fig 5 for EWM, fig 2 [0083], fig 7, fig 8, [0106-0107] for performing a multiplication operation on first input data and second input data that are transmitted from first and second memory banks of the plurality of memory banks respectively, [0093], [0111-0113] for generate multiplication result data).
Song discloses a MAC unit comprising a first memory bank and a second memory bank, and further discloses the PIM device may include a plurality of MAC units ([0083]). Song also further discloses a latch for controlling data into and results from the arithmetic circuit ([0081], [0092-0093]). Song also further discloses a GIO line capable of providing a data transmission path from the data input/output (I/O) circuit to the plurality of memory banks and the plurality of MAC operators. Song does not, however, explicitly disclose transmitting the multiplication result data to a third memory bank of the plurality of memory bands or wherein, while the EWM operation is being performed, data transmission through the GIO line between the peripheral region and the memory/arithmetic region is blocked, or wherein the GIO line comprises separate write and read global lines capable of providing a data transmission path from the data input/output (I/O) circuit to the plurality of memory banks and the plurality of MAC operators.
However, in the same field of endeavor, Kwon discloses an apparatus similar to Song comprising processing in memory including bank-parallel memory and arithmetic processing units performing MAC operations including elementwise multiplication (Introduction, fig 1, fig 2(c)). Kwon further discloses transmitting the multiplication result data to a third memory bank of the plurality of memory banks (fig 2(c)). It would have been obvious to one of ordinary skill in the art before the effective filing date use the existing structure of Song comprising adjacent memory banks among Song’s plurality of MAC unit to transmit the multiplication data to a third memory bank among the plurality of memory banks as in Kwon. It would have been obvious to achieve the performance improvement of bank-level parallelism (Kwon Section V.D). Furthermore, Kwon further discloses a write global data input/output (GIO) line capable of providing a data transmission path from the data input/output (I/O) circuit to the plurality of memory banks and the plurality of MAC operators; and a read GIO line capable of providing a data transmission path from the data input/output (I/O) circuit to the plurality of memory banks and the plurality of MAC operators (fig 2(d), 2(e)). It would have been obvious to one of ordinary skill in the art before the effective filing data for Song to implement the GIO using separate read and write GIO to achieve the benefit of efficient read and write wherein the bandwidths of each operation is different (Section III.C. last paragraph). Therefore Song in view of Kwon teaches transmitting the multiplication result data to a third memory bank of the plurality of memory banks, and a write global data input/output (GIO) line capable of providing a data transmission path from the data input/output (I/O) circuit to the plurality of memory banks and the plurality of MAC operators; and a read GIO line capable of providing a data transmission path from the data input/output (I/O) circuit to the plurality of memory banks and the plurality of MAC operators.
Song in view of Kwon does not explicitly disclose wherein, while the EWM operation is being performed, data transmission through the GIO line between the peripheral region and the memory/arithmetic region is blocked. However, in the same field of endeavor, Sumbul discloses an apparatus similar to Song comprising a compute in memory circuit (CIM) including a number of MAC circuits (abstract). Sumbul further discloses an enable signal that controls multiplexers controlling input data and addressing data to arithmetic and memory region of the CIM device (fig 2 216 to 214, 222, [0056-0065] sending only one element per cycle). It would have been obvious to one of ordinary skill in the art before the effective filing date to include the enable control circuit and multiplexers as in Sumbul in the GIO line of Song, to block data transmission through the GIO line between the peripheral region and the memory/arithmetic region while the EWM is being performed to achieve the benefit of avoiding data collision while the EWM operation is being performed (Sumbul [0064]). Therefore, Song in view of Kwon in view of Sumbul teaches wherein, while the EWM operation is being performed, data transmission through the GIO line between the peripheral region and the memory/arithmetic region is blocked.
Allowable Subject Matter
Claims 2-17 and 19-31 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and rewritten to overcome the rejections under 35 USC 112(b) and the relevant claim objections.
The following is a statement of reasons for the indication of allowable subject matter.
Applicant claims processing-in-memory devices wherein the device as in claim 1 comprises:
a memory/arithmetic region including a plurality of memory banks and a plurality of multiplication-and-accumulation (MAC) operators, the plurality of MAC operators including a first MAC operator;
a peripheral region including a data input/output (I/O) circuit; and
a global data input/output (GIO) line capable of providing a data transmission path between the peripheral region and the memory/arithmetic region,
wherein the first MAC operator is configured to perform an element-wise multiplication (EWM) operation by performing a multiplication operation on first input data and second input data that are transmitted from first and second memory banks of the plurality of memory banks, respectively, to generate multiplication result data and transmitting the multiplication result data to a third memory bank of the plurality of memory banks, and
wherein, while the EWM operation is being performed, data transmission through the GIO line between the peripheral region and the memory/arithmetic region is blocked.
Wherein claim 2 comprising the device PIM device of claim 1, wherein the first MAC operator includes:
a multiplication circuit including a plurality of multipliers that are disposed to be parallel with each other;
a data output selection circuit configured to output multiplication data that has been output from the multiplication circuit through output lines, selected among first output lines and second output lines;
an adder tree including a plurality of adders that are arranged in a tree structure; and
an accumulator configured to perform an accumulative addition operation on data that is output from the adder tree.
Applicant further claims processing-in-memory devices wherein the device as in claim 18 comprises:
a memory/arithmetic region including a plurality of memory banks and a plurality of multiplication-and-accumulation (MAC) operators, the plurality of MAC operators including a first MAC operator;
a peripheral region including a data input/output (I/O) circuit;
a write global data input/output (GIO) line capable of providing a data transmission path from the data input/output (I/0) circuit to the plurality of memory banks and the plurality of MAC operators; and
a read GIO line capable of providing a data transmission path from the plurality of memory banks and the plurality of MAC operators to the data input/output (I/0) circuit,
wherein the first MAC operator is configured to perform an element-wise multiplication (EWM) operation by performing a multiplication operation on first input data and second input data that are transmitted from first and second memory banks of the plurality of memory banks, respectively, to generate multiplication result data, and transmitting the multiplication result data to a third memory bank of the plurality of memory banks, and
wherein while the EWM operation is being performed, data transmission through the read and write GIO lines between the peripheral region and the memory/arithmetic region is blocked.
Wherein claim 19 comprising the device PIM device of claim 18 wherein the first MAC operator includes:
a multiplication circuit including a plurality of multipliers that are disposed to be parallel with each other;
a data output selection circuit configured to output multiplication data that has been output from the multiplication circuit to output lines, selected among first output lines and second output lines;
an adder tree including a plurality of adders that are arranged in a tree structure; and
an accumulator configured to perform an accumulative addition operation on data that is output from the adder tree.
The primary reasons for indication of allowable subject matter are the above highlighted limitations in combination with the remaining limitations. None of Song, Kwon, or Sumbul teach or suggest a data output selection circuit configured to output multiplication data that has been output from the multiplication circuit to output lines, selected among first output lines and second output lines.
Conclusion
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/EMILY E LAROCQUE/Examiner, Art Unit 2182