Prosecution Insights
Last updated: April 19, 2026
Application No. 17/953,206

ELECTROLYTIC SURFACE FINISH ARCHITECTURE

Non-Final OA §102§103
Filed
Sep 26, 2022
Examiner
ROBINSON, KRYSTAL
Art Unit
2848
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2y 0m
To Grant
80%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
652 granted / 756 resolved
+18.2% vs TC avg
Minimal -6% lift
Without
With
+-5.7%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
27 currently pending
Career history
783
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
47.8%
+7.8% vs TC avg
§102
33.6%
-6.4% vs TC avg
§112
10.4%
-29.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 756 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Claims 12-18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method of forming a package substrate, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on December 30, 2025. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 8-11 and 19 and is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hando et al. (US 8,143,534). In regards to claim 1, Hando et al. teaches a package substrate (see figure 12), comprising: a core (11); a pad (22) over the core (11), wherein the pad has a first width (see the width of the pad in figure 12); a surface finish over the pad (the pad consist of metal plating layers, column 10 lines 4, Ni-P plating layer and Au plating layer), wherein the surface finish has a second width that is substantially equal to the first width (the width of the entire pad (22) in figure 12); and a solder resist (30) over the pad (22), wherein the solder resist (22) comprises an opening (see the opening in layer (30) in figure 12) that exposes a portion of the surface finish (see figure 12), wherein the opening has a third width that is smaller than the second width (see figure 12, the solder resist layer opening is smaller than the width of the pad (22). In regards to claim 8, Hando et al. teaches the package substrate of claim 1, wherein the pad (22) is a solder resist defined pad (22)( PCB copper pads where the solder mask overlaps the edges, with the mask opening defining the final soldering area). In regards to claim 9, Hando et al. teaches the package substrate of claim 1, wherein the pad (22) is a metal defined pad (the pad consist of metal plating layers, column 10 lines 4, Ni-P plating layer and Au plating layer). In regards to claim 10, Hando et al. teaches the package substrate of claim 1, wherein the core (11) comprises a borosilicate glass (glass fiber, column 2, lines 53-65). In regards to claim 11, Hando et al. teaches The package substrate of claim 1, wherein the surface finish comprises gold (column 10 lines 4, Ni-P plating layer and Au plating layer). In regards to claim 19, Hando et al. teaches an electronic system, comprising: a board (12); package substrate (substrate (11), figure 12) coupled to the board (12), wherein the package substrate (11) comprises: a core (11); a pad (22) over the core (11); and a surface finish over the pad (the pad consist of metal plating layers, column 10 lines 4, Ni-P plating layer and Au plating layer), wherein the surface finish (the pad consist of metal plating layers, column 10 lines 4, Ni-P plating layer and Au plating layer) is capable of being deposited with an electrolytic process (electrolytic is capable of being used as a process to plate the Ni-P or Au material, the method of making the plating layers is not germane to the product claim); and a die (IC chip (45)) coupled to the package substrate (see figure 11). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hando et al. (US 8,143,534) in view of Park et al. (US 2014/0182904). In regards to claim 5, Hando et al. teaches the package substrate of claim 1. Hando et al. does not teach an adhesion promoting layer over portions of the surface finish. Park et al. teaches an adhesion (115) promoting layer over portions of the surface finish (an adhesive promoter (115) interposed between an insulating layer (110) and a circuit layer on a substrate in order to improve adhesion between the insulating layer and the circuit layer; paragraph [0034]). IT would have been obvious to one of ordinary skilled in the art at the time of the invention to have included in the teaching of Hando et al. the adhesion promoting layer over portions of the surface finish as taught by Park et al. (in order to improve adhesion between the insulating layer and the circuit layer; paragraph [0034]). In regards to claim 6, Hando et al. in combination with Park et al. teaches the package substrate of claim 5, wherein the adhesion promoting layer (115) is absent from the surface finish under the opening in the solder resist (the second polymer and the organic compound are mixed so as to be adhered to the insulating layer 110 or the solder resist, paragraph [0044]). In regards to claim 7, Hando et al. in combination with Park et al. teaches the package substrate of claim 5. Hando et al. in combination with Park et al. does not teach wherein the adhesion promoting layer comprises silicon and nitrogen. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have made wherein the adhesion promoting layer comprises silicon and nitrogen, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Allowable Subject Matter Claims 2-4 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please see the attachment of the USPTO-892 form. Communication Any inquiry concerning this communication or earlier communications from the examiner should be directed to KRYSTAL ROBINSON whose telephone number is (571)272-9258. The examiner can normally be reached on 9-5 M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached on (571)-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KRYSTAL ROBINSON/Examiner, Art Unit 2848
Read full office action

Prosecution Timeline

Sep 26, 2022
Application Filed
May 25, 2023
Response after Non-Final Action
Jan 24, 2026
Non-Final Rejection — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
80%
With Interview (-5.7%)
2y 0m
Median Time to Grant
Low
PTA Risk
Based on 756 resolved cases by this examiner. Grant probability derived from career allow rate.

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