DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
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Status of claim(s) to be treated in this office action:
Independent: 1, 15 and 16.
Pending: 1-20.
Withdrawn: 6, 16-20.
Election/Restrictions
Applicant’s election without traverse of Species I in the reply filed on 10/2/2025 is acknowledged.
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: SEMICONDUCTOR DEVICE WITH DUAL-LAYER BORON-DOPED SILICON NITRIDE SPACER.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 7-8 and 15 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Taniguchi et al., US PG pub. 20020163080 A1.
Re: Independent Claim 1, Taniguchi discloses a substrate (11, fig. 6) having a cell area (area where 13e, 19a and 26a formed in, fig. 6) and a peripheral area (area where 13c 13d and 25 formed in fig. 6);
transistors (transistors formed on in the right side of the device, fig. 6) in the peripheral area (area where 13c 13d and 25 formed in fig. 6) over the substrate (11, fig. 6);
a lower interlayer insulating layer (26, fig. 9) between the transistors (transistors formed on in the right side of the device, fig. 6);
interconnections (25, fig. 8) and a first spacer layer (28 and 29, fig. 7) over the transistors (transistors formed on in the right side of the device, fig. 6) and the lower interlayer insulating layer (26, fig. 9), wherein the first spacer layer (28 and 29, fig. 7) is disposed between the interconnections (25, fig. 8); and
an upper interlayer insulating layer (34, fig. 8) over the interconnections (25, fig. 8) and the first spacer layer (28 and 29, fig. 7),
wherein the first spacer layer (28 and 29, fig. 7) includes a first lower spacer layer (28, fig. 8) and a first upper spacer layer (29, fig. 8) over the first lower spacer layer (28, fig. 8),
wherein the first lower spacer layer (28, fig. 8) and the first upper spacer layer (29, fig. 8) include elements of silicon, boron, and nitrogen (¶0223).
Taniguchi is silent regarding: wherein a boron concentration of the first lower spacer layer is different than first upper spacer layer.
Taniguchi does teach that wherein a boron concentration of the first lower spacer layer (28, fig. 8) is different (¶0223; since a diffusion region by heat treatment and exit of boron from a gate electrode of a p-channel transistor the silicon nitride layer 28 would have a low concentration of boron and since layer 29 is a material such as BPSG which include boron in its layer would have a higher concentration) from a boron concentration of the first upper spacer layer (29, fig. 8). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to shown there is a difference boron concentration between the lower spacer layer and upper spacer layer.
Re: Claim 2, Taniguchi discloses all the limitations of claim 1 on which this claim depends. Taniguchi is silent regarding: wherein the boron concentration of the first lower spacer layer (28, fig. 8) is higher than the boron concentration of the first upper spacer layer (29, fig. 8). Taniguchi does teach that wherein a boron concentration of the first lower spacer layer (28, fig. 8) is different (¶0223; since a diffusion region by heat treatment and exit of boron from a gate electrode of a p-channel transistor the silicon nitride layer 28 would have a low concentration of boron and since layer 29 is a material such as BPSG which include boron in its layer would have a higher concentration) from a boron concentration of the first upper spacer layer (29, fig. 8). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to shown there is a upper spacer a BPSG would have a higher boron concentration than the lower spacer layer.
Re: Claim 3, Taniguchi discloses all the limitations of claim 1 on which this claim depends. Taniguchi further discloses: wherein the first lower spacer layer (28, fig. 8) surrounds a bottom surface and side surfaces of the first upper spacer layer (29, fig. 8) in a U-shape (as shown in figure 8 a the spacer 28 and 29 shaped like a U upside down).
Re: Claim 7, Taniguchi discloses all the limitations of claim 1 on which this claim depends. Taniguchi further discloses: an etch stop layer (32, fig. 8; ¶0016) over the first spacer layer (28 and 29, fig. 7), and wherein the etch stop layer (32, fig. 8; ¶0016) includes silicon nitride to have an etch selectivity with respect to the first spacer layer (28 and 29, fig. 7).
Re: Claim 8, Taniguchi discloses all the limitations of claim 1 on which this claim depends. Taniguchi further discloses: hard mask patterns (26 above the STI 12, fig. 8) including silicon nitride over the interconnections (25, fig. 8), and
wherein the first spacer layer (28 and 29, fig. 7) extends onto the hard mask patterns (26 above the STI 12, fig. 8).
Re: Independent Claim 15, Taniguchi discloses a substrate (11, fig. 6);
transistors (transistors formed on in the right side of the device, fig. 6) over the substrate (11, fig. 6);
a lower interlayer insulating layer (26, fig. 9) between the transistors (transistors formed on in the right side of the device, fig. 6);
interconnections (25, fig. 8) and a first spacer layer (28 and 29, fig. 7) over the transistors (transistors formed on in the right side of the device, fig. 6) and the lower interlayer insulating layer (26, fig. 9)s, wherein the first spacer layer (28 and 29, fig. 7) is disposed between the interconnections (25, fig. 8); and
an upper interlayer insulating layer (34, fig. 8) over the interconnections (25, fig. 8) and the first spacer layer (28 and 29, fig. 7),
wherein the first spacer layer (28 and 29, fig. 7) includes elements of silicon, boron, and nitrogen (¶0223).
Taniguchi is silent regarding: wherein the first spacer layer (28 and 29, fig. 7) has a concentration gradient between a first region (29, fig. 8) having a higher boron concentration and a second region (28, fig. 8) having a lower boron concentration.
Taniguchi does teach that wherein a boron concentration of the first region (28, fig. 8) is different (¶0223; since a diffusion region by heat treatment and exit of boron from a gate electrode of a p-channel transistor the silicon nitride layer 28 would have a low concentration of boron and since layer 29 is a material such as BPSG which include boron in its layer would have a higher concentration) from a boron concentration of the second region (29, fig. 8). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to shown there is a upper spacer a BPSG would have a higher boron concentration than the lower spacer layer.
Claim(s) 4-5 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Taniguchi et al., US PG pub. 20020163080 A1; in view of Baars et al., US PG pub. 20070281417 A1.
Re: Claim 4, Taniguchi discloses all the limitations of claim 1 on which this claim depends. Taniguchi is silent regarding: wherein the first upper spacer layer (29, fig. 8; layer 29 is a BPSG layer) further includes carbon.
Baars discloses spacer layer (N5 fig. 1I) a first protective layer made of carbon or made of a carbon containing material over said memory cell region and peripheral device region ¶0007.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include carbon material in the protective or spacer layer since carbon can protect the cell device and peripheral device and it has an excellent process window and can be combined with stress liner concepts to process electronic devices in a memory cell region and electronic devices in a peripheral device region very effectively ¶0009.
Re: Claim 5, Taniguchi discloses all the limitations of claim 4 on which this claim depends. Taniguchi is silent regarding: wherein the first lower spacer layer (28, fig. 8) further includes carbon, and wherein a carbon concentration of the first upper spacer layer (29, fig. 8) is higher than a carbon concentration of the first lower spacer layer (28, fig. 8).
Baars discloses spacer layer (N5 fig. 1I) a first protective layer made of carbon or made of a carbon containing material over said memory cell region and peripheral device region ¶0007.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include carbon material in the protective or spacer layer since carbon can protect the cell device and peripheral device and it has an excellent process window and can be combined with stress liner concepts to process electronic devices in a memory cell region and electronic devices in a peripheral device region very effectively ¶0009.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Lee et al., US PG pub. 20150171163 A1”) Discloses a semiconductor device and a method of fabricating the same. The semiconductor device includes a first bit line structure extending in a first direction, a second bit line structure extending in the first direction and spaced apart from the first bit line structure, a storage contact plug located between the first bit line structure and the second bit line structure, and extending in a second direction perpendicular to the first direction, a first plug insulator located between the first bit line structure and the second bit line structure, and configured to contact a side surface extending in the second direction of the storage contact plug, and a plug isolation pattern located between the first bit line structure and the first plug insulator.
* (“Ishikawa et al., US PG pub. 20030235962 A1”) discloses a semiconductor integrated circuit device comprising forming a silicon oxide film as thin as 5 nm or less on the surfaces of p type wells and n type wells by wet oxidizing a substrate, heating the substrate in an atmosphere containing about 5% of an NO gas to introduce nitrogen into the silicon oxide film so as to form a silicon oxynitride film, exposing the substrate to a nitrogen plasma atmosphere to further introduce nitrogen into the silicon oxynitride film in order to form a silicon oxynitride gate insulating film having a first peak concentration near the interface with the substrate and a second peak concentration near the surface thereof. Thereby, the concentration of nitrogen in the gate insulating film is increased without raising the concentration of nitrogen near the interface between the substrate and the gate insulating film to a higher level than required.
* (“Lee et al., US Patent 11737256 B2”) discloses a semiconductor device and a method of manufacturing a semiconductor device, the device including a substrate; a lower structure including pad patterns on the substrate, upper surfaces of the pad patterns being at an outer side of the lower structure; a plurality of lower electrodes contacting the upper surfaces of the pad patterns; a dielectric layer and an upper electrode sequentially stacked on a surface of each of the lower electrodes; and a hydrogen supply layer including hydrogen, the hydrogen supply layer being between the lower electrodes and closer to the substrate than the dielectric layer is to the substrate.
Allowable Subject Matter
Claim(s) 9-14 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re: Claim 9, (and its dependent claim(s) 10-14), the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: landing pads over the storage contacts; a second spacer layer between the landing pads; and storage structures over the landing pads, wherein the second spacer layer includes a second lower spacer layer and a second upper spacer layer over the second lower spacer layer, wherein the second lower spacer layer and the second upper spacer layer include the elements of silicon, boron, and nitrogen, and wherein a boron concentration of the second lower spacer layer is different from a boron concentration of the second upper spacer layer.
Conclusion
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898