DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
In view of amendments made and Applicant’s arguments (see Remarks submitted on 05/18/2026), the restriction requirement has been withdrawn. Accordingly, claims 1-20 and 22-26 will be examined.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/18/2023, 01/18/2024 and 07/07/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: 700 mentioned in paragraph [0054].
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 10-20 are objected to under 37 C.F.R. 1.71(a) which requires “full, clear, concise, and exact terms” as to enable any person skilled in the art or science to which the invention or discovery appertains, or with which it is most nearly connected, to make and use the same. The following should be corrected.
A. In claim 10 line 5, “analog instructions” should read “the analog instructions” instead because analog instructions is already recited in line 4. Claims 11-20 inherit the same deficiency as claim 10 by reason of dependence.
B. In claim 11 line 4, “analog instructions” should read “the analog instructions” instead because analog instructions is already recited in line 4.
C. In claim 15 line 2, “analog instructions” should read “the analog instructions” instead because analog instructions is already recited in line 2. Claim 16 inherit the same deficiency as claim 15 by reason of dependence.
D. In claim 18 line 6, “analog instructions” should read “the analog instructions” instead because analog instructions is already recited in line 5.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4, 6-10, 14-15, 19-20 and 22-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhang et al. (NPL – “Exploiting Different Levels of Parallelism in the Quantum Control Microarchitecture for Superconducting Qubits”), hereinafter Zhang.
Regarding claim 1, Zhang teaches an apparatus comprising:
a processor comprising a processor core, the processor core comprising (Zhang Fig. 8 processor/ processor core – processor):
instruction management circuitry, digital instruction execution circuitry and analog instruction execution circuitry, the instruction management circuitry to (Zhang Fig. 8 instruction management circuitry – instruction fetch and pre-decoder; digital instruction execution circuitry – classical pipeline; analog instruction execution circuitry – quantum pipeline):
receive a plurality of instructions (Zhang Fig. 8 and section 5.3.1 “The pre-decoder buffers the fetched instructions and distinguishes whether they are classical or quantum instructions, and then determines the dispatch of the instructions”);
determine whether individual instructions of the plurality of instructions are digital instructions or analog instructions (Zhang Fig. 8 and section 5.3.1 “The pre-decoder buffers the fetched instructions and distinguishes whether they are classical or quantum instructions, and then determines the dispatch of the instructions”; digital instructions – classical instructions; analog instructions – quantum instructions);
transmit individual digital instructions of the plurality of instructions to the digital instruction execution circuitry in response to a determination that the corresponding individual instructions are digital instructions (Zhang Fig. 8 and section 5.3.1 “The pre-decoder buffers the fetched instructions and distinguishes whether they are classical or quantum instructions, and then determines the dispatch of the instructions”; section 5.3.1 (2) “Classical instructions in the fetched instructions: … a branch instruction can be sent into the classical execution unit”; section 5.3.2 “Each processor has one classical pipeline … which decode and execute classical … instructions”); and
transmit individual analog instructions of the plurality of instructions to the analog instruction execution circuitry in response to a determination that the corresponding individual instructions are analog instructions (Zhang Fig. 8 and section 5.3.1 “The pre-decoder buffers the fetched instructions and distinguishes whether they are classical or quantum instructions, and then determines the dispatch of the instructions”; section 5.3.2 “Each processor has … multiple quantum pipelines, which decode and execute … quantum instructions”),
the analog instruction execution circuitry to execute analog instructions received from the instruction management circuitry, wherein to execute analog instructions comprises to generate or measure an analog signal at an input/output of the processor (Zhang Figs. 1-2, 5 and 8-9; section 2.4 “The QCP executes the measurement instruction and starts to wait for the result to return. The measurement operation is performed on the QPU … Repeat-Until-Success (RUS) [28] is a special case of dynamic quantum circuits, which repeatedly execute certain quantum operations and perform a measurement until a success measurement outcome occurs”; program 1 and program 2; section 5.4 “This example indicates that the operation to be performed on qubit 1 should be determined based on the measurement result of qubit 0 … (1) The valid measurement result is returned”; section 6.1).
Regarding claim 4, Zhang teaches all the limitations of claim 1 as stated above. Further, Zhang teaches wherein the analog instruction execution circuitry is to execute an instruction to generate an analog pulse and measure a reflection of the generated analog pulse (Zhang Figs. 1-2, 9; section 2.3 “The measurement operation usually requires a pulse”; section 5.2.4 (4); section 6.2 “The QCP sends codeword to AWGs to trigger the waveform generation, and receives measurement results from DAQs”).
Regarding claim 6, Zhang teaches all the limitations of claim 1 as stated above. Further, Zhang teaches wherein the analog instruction execution circuitry comprises a plurality of digital signal processors, wherein the plurality of digital signal processors are to execute a plurality of analog instructions in parallel (Zhang Figs. 8-9; section 5.3; section 5.3.1 “we further employ quantum superscalar to exploit the parallelism of quantum instructions. Figure 8 shows an example of a 4-way quantum superscalar structure. In this architecture, four instructions are fetched into the pre-decoder in one cycle and then dispatched to different pipelines for execution”; plurality of digital signal processors – quantum decoders and/or quantum execution units x4).
Regarding claim 7, Zhang teaches all the limitations of claim 1 as stated above. Further, Zhang teaches further comprising a plurality of qubits, wherein individual digital signal processors of the plurality of digital signal processors are to control two or more qubits of the plurality of qubits (Zhang Fig. 1 and section 2.4 plurality of qubits - the Superconducting Qubits (SQ); Figs. 5 and 8-9; section 5.2.4 (4) “The last stage of the execution unit is to convert the operation for each qubit into a codeword sent to the low-level control electronics”; section 7; section 8 “ The QuAPE processor implemented for the experiment targets a 10-qubit one-dimension superconducting chip, which requires 38 analog channels for control and readout in our experimental setup”).
Regarding claim 8, Zhang teaches all the limitations of claim 1 as stated above. Further, Zhang teaches wherein the instruction management circuitry is to receive the plurality of instructions in a single clock cycle (Zhang section 5.3 “four instructions are fetched into the pre-decoder in one cycle and then dispatched to different pipelines for execution”).
Regarding claim 9, Zhang teaches all the limitations of claim 1 as stated above. Further, Zhang teaches wherein a latency of transmission of individual analog instructions of the plurality of instructions to the analog instruction execution circuitry is less than one nanosecond (This limitation is reciting a manner of operating the apparatus and does not differentiate the apparatus claim from the prior art. See MPEP 2114 II for more information).
Regarding claim 26, Zhang teaches all the limitations of claim 1 as stated above. Further, Zhang teaches further comprising:
a second processor (Zhang Figs. 5, 9 second processor – control unit/scheduler);
a plurality of qubits (Zhang Fig. 1 and section 2.3; plurality of qubits - Superconducting Qubits (SQ); page 907 left col last paragraph); and
one or more computer-readable media comprising instructions that, when executed by the second processor, cause the second processor to (Zhang section 5.2.3 “the instructions in the program block will be fetched from the centralized main memory to the private instruction cache of each processor”; one or more computer-readable media – main memory; section 5.2.4 “The previously described modules can be regarded as the control unit for determining the coordination of multiple processors”; section 2.2 “The control microarchitecture implemented in the Quantum Control Processor (QCP) accepts post-compilation instructions as input … These quantum instructions are executed in the QCP to issue corresponding quantum operations to the QPU”):
send a plurality of instructions for the processor to the processor (Zhang Fig. 5 and section 5.2.2 “When the block passes the dependency check, it starts to request for allocation. Its status can be changed to "in execution" when there is an idle processor, and the corresponding instructions are fetched into the private instruction cache”; section 5.2.3 “the instructions in the program block will be fetched from the centralized main memory to the private instruction cache of each processor. The processor needs to switch to the next program after the current execution is complete. It takes certain time for the scheduler to fetch new instructions into the private cache”),
wherein the plurality of instructions for the processor comprises one or more digital instructions and one or more analog instructions, wherein the one or more analog instructions, when executed by the processor, cause the processor to generate or measure an analog signal at an input/output of the processor (Zhang Fig. 8 and section 5.3.1 “The pre-decoder buffers the fetched instructions and distinguishes whether they are classical or quantum instructions, and then determines the dispatch of the instructions”; digital instructions – classical instructions; analog instructions – quantum instructions; section 2.2; section 2.4 “The QCP executes the measurement instruction and starts to wait for the result to return. The measurement operation is performed on the QPU … Repeat-Until-Success (RUS) [28] is a special case of dynamic quantum circuits, which repeatedly execute certain quantum operations and perform a measurement until a success measurement outcome occurs”; program 1 and program 2; section 5.4 “This example indicates that the operation to be performed on qubit 1 should be determined based on the measurement result of qubit 0 … (1) The valid measurement result is returned”; section 6.1),
wherein the one or more analog instructions, when executed by the processor, cause the processor to send an analog signal to a qubit of the plurality of qubits or measure an analog signal from a qubit of the plurality of qubits (Zhang Figs. 1-2, 5 and 8-9; section 2.2 “quantum instructions that describe quantum operations. These quantum instructions are executed in the QCP to issue corresponding quantum operations to the QPU” section 2.4 “The QCP executes the measurement instruction and starts to wait for the result to return. The measurement operation is performed on the QPU … Repeat-Until-Success (RUS) [28] is a special case of dynamic quantum circuits, which repeatedly execute certain quantum operations and perform a measurement until a success measurement outcome occurs”; program 1 and program 2; section 5.4 “This example indicates that the operation to be performed on qubit 1 should be determined based on the measurement result of qubit 0 … (1) The valid measurement result is returned”; section 6.1; section 6.2 “The QCP sends codeword to AWGs to trigger the waveform generation, and receives measurement results from DAQs”).
Regarding claims 10 and 22, they recite similar limitations as claim 26. Claim 26 analysis applies equally to claims 10 and 22 (see also remarks page 1 submitted on 05/18/2026 which includes Applicant’s statement that claim 26 recites similar features as claims 10 and 22).
Regarding claim 14, Zhang teaches all the limitations of claim 10 as stated above. Further, Zhang teaches wherein the processor is to execute an instruction to generate an analog pulse and measure a reflection of the generated analog pulse (Zhang Figs. 1-2, 9; section 2.3 “The measurement operation usually requires a pulse”; section 5.2.4 (4); section 6.2 “The QCP sends codeword to AWGs to trigger the waveform generation, and receives measurement results from DAQs”).
Regarding claim 15, Zhang teaches all the limitations of claim 10 as stated above. Further, Zhang teaches wherein the processor comprises a plurality of processor cores, wherein individual processor cores of the plurality of processor cores are to execute digital instructions and analog instructions, wherein to execute analog instructions comprises to send an analog signal to a qubit of the plurality of qubits or measure an analog signal from a qubit of the plurality of qubits (Zhang Figs. 5 and 8 and section 5.3.2 “Each processor has one classical pipeline and multiple quantum pipelines, which decode and execute classical and quantum instructions respectively”; section 2.2 “quantum instructions that describe quantum operations. These quantum instructions are executed in the QCP to issue corresponding quantum operations to the QPU” section 2.4 “The QCP executes the measurement instruction and starts to wait for the result to return. The measurement operation is performed on the QPU … Repeat-Until-Success (RUS) [28] is a special case of dynamic quantum circuits, which repeatedly execute certain quantum operations and perform a measurement until a success measurement outcome occurs”; program 1 and program 2; section 5.4 “This example indicates that the operation to be performed on qubit 1 should be determined based on the measurement result of qubit 0 … (1) The valid measurement result is returned”; section 6.1; section 6.2).
Regarding claim 19, Zhang teaches all the limitations of claim 10 as stated above. Further, Zhang teaches wherein the processor comprises a plurality of digital signal processors, wherein the plurality of digital signal processors are to execute a plurality of analog instructions in parallel (Zhang Figs. 8-9; section 5.3; section 5.3.1 “we further employ quantum superscalar to exploit the parallelism of quantum instructions. Figure 8 shows an example of a 4-way quantum superscalar structure. In this architecture, four instructions are fetched into the pre-decoder in one cycle and then dispatched to different pipelines for execution”; plurality of digital signal processors – quantum decoders and/or quantum execution units x4).
Regarding claim 20, Zhang teaches all the limitations of claim 19 as stated above. Further, Zhang teaches wherein individual digital signal processors of the plurality of digital signal processors are to control two or more qubits of the plurality of qubits (Zhang Fig. 1 and section 2.4 plurality of qubits - the Superconducting Qubits (SQ); Figs. 5 and 8-9; section 5.2.4 (4) “The last stage of the execution unit is to convert the operation for each qubit into a codeword sent to the low-level control electronics”; section 7; section 8 “ The QuAPE processor implemented for the experiment targets a 10-qubit one-dimension superconducting chip, which requires 38 analog channels for control and readout in our experimental setup”).
Regarding claim 23, Zhang teaches all the limitations of claim 22 as stated above. Further, Zhang teaches
wherein the plurality of instructions for the first processor further cause the first processor to: compile code into the plurality of instructions for the second processor, wherein to compile the code into the plurality of instructions for the second processor comprises to optimize the one or more digital instructions and the one or more analog instructions of the plurality of instructions for the second processor (Zhang Fig. 1; abstract “As in classical micro architecture, parallelism in quantum programs needs to be exploited for speedup”; page 899 left col bottom “an ideal control micro architecture should be capable to exploit this parallelism and support issuing quantum operations to different qubits in parallel within a certain period of time”; section 31.1. and 3.1.2; section 5.1; section 5.3).
Regarding claim 24, Zhang teaches all the limitations of claim 23 as stated above. Further, Zhang teaches
wherein the second processor comprises a plurality of cores (Zhang Figs. 5, 8-9 plurality of cores – processors or execution units), wherein to optimize the one or more digital instructions and the one or more analog instructions of the plurality of instructions for the second processor comprises to optimize the one or more digital instructions and the one or more analog instructions of the plurality of instructions for the plurality of cores (Zhang abstract “As in classical micro architecture, parallelism in quantum programs needs to be exploited for speedup”; page 899 left col bottom “an ideal control micro architecture should be capable to exploit this parallelism and support issuing quantum operations to different qubits in parallel within a certain period of time”; section 31.1. and 3.1.2; section 5.1; section 5.3).
Regarding claim 25, Zhang teaches all the limitations of claim 23 as stated above. Further, Zhang teaches wherein to optimize the one or more digital instructions and the one or more analog instructions of the plurality of instructions for the second processor comprises to optimize the one or more digital instructions and the one or more analog instructions of the plurality of instructions for a plurality of second processors (Zhang Figs. 5, 8-9; abstract “As in classical micro architecture, parallelism in quantum programs needs to be exploited for speedup”; page 899 left col bottom “an ideal control micro architecture should be capable to exploit this parallelism and support issuing quantum operations to different qubits in parallel within a certain period of time”; section 31.1. and 3.1.2; section 5.1; section 5.3; a plurality of second processors – processors).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang as applied to claim 1 and 10 above, and further in view of Khammassi (US 20210182071 A1). Khammassi is cited in the IDS submitted on 07/07/2026.
Regarding claim 2, Zhang teaches all the limitations of claim 1 as stated above.
Zhang does not explicitly teach wherein the digital instruction execution circuitry is to execute instructions to load one or more parameters in one or more registers, wherein the analog instruction execution circuitry is to execute instructions to generate an analog pulse based on the one or more parameters in the one or more registers.
However, on the same field of endeavor, Khammassi discloses executing instructions to load one or more parameters in one or more registers, wherein an analog instruction execution circuitry is to execute instructions to generate an analog pulse based on the one or more parameters in the one or more registers (Khammassi paragraph [0042] “processor/core 210 may include various other/additional non-quantum functional units (e.g., such as load/store address generation units”; paragraph [0043] “the quantum engine functional units 204E share the same set of register files 204A-B used by the legacy processor functional units 204C-D”; paragraph [0067] “other values may be specified via opcodes which map to registers or memory locations where the actual input values are stored (e.g., having been calculated by prior instructions and/or loaded from memory)”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Zhang using Khammassi and configure the digital instruction execution circuitry to execute instructions to load one or more parameters in one or more registers used by the analog instruction execution circuitry when executing instructions to generate an analog pulse because a load instruction is normally a classical instruction for loading operands used by the analog instruction execution circuitry to execute the quantum instruction/operation (Zhang section 2.2 “classical instructions, mainly used for constructing different types of control flow, and usually consisting of four kinds of instructions: control, data transfer, logical, and arithmetic; Khammassi paragraph [0042, 0067]).
Therefore, the combination of Zhang as modified in view of Khammassi teaches wherein the digital instruction execution circuitry is to execute instructions to load one or more parameters in one or more registers, wherein the analog instruction execution circuitry is to execute instructions to generate an analog pulse based on the one or more parameters in the one or more registers.
Regarding claim 3, Zhang as modified in view of Khammassi teaches all the limitations of claim 2 as stated above. Further, Zhang as modified in view of Khammassi teaches wherein the one or more parameters in the one or more registers are used to control an amplitude and a frequency of the analog pulse (Khammassi Fig. 6 and paragraphs [0060, 0062]).
Regarding claim 12, Zhang teaches all the limitations of claim 10 as stated above.
Zhang does not explicitly teach wherein the processor is to execute instructions to load one or more parameters in one or more registers, wherein the processor is to execute instructions to generate an analog pulse based on the one or more parameters in the one or more registers.
However, on the same field of endeavor, Khammassi discloses executing instructions to load one or more parameters in one or more registers, and executing instructions to generate an analog pulse based on the one or more parameters in the one or more registers (Khammassi paragraph [0042] “processor/core 210 may include various other/additional non-quantum functional units (e.g., such as load/store address generation units”; paragraph [0043] “the quantum engine functional units 204E share the same set of register files 204A-B used by the legacy processor functional units 204C-D”; paragraph [0067] “other values may be specified via opcodes which map to registers or memory locations where the actual input values are stored (e.g., having been calculated by prior instructions and/or loaded from memory)”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Zhang using Khammassi and configure the processor to execute instructions to load one or more parameters in one or more registers and execute the instructions to generate an analog pulse based on the one or more parameters in the one or more registers in order to set the operand values for executing the quantum instruction/operation (Zhang section 2.2; Khammassi paragraph [0042, 0067]).
Therefore, the combination of Zhang as modified in view of Khammassi teaches wherein the processor is to execute instructions to load one or more parameters in one or more registers, wherein the processor is to execute instructions to generate an analog pulse based on the one or more parameters in the one or more registers.
Regarding claim 13, Zhang as modified in view of Khammassi teaches all the limitations of claim 12 as stated above. Further, Zhang as modified in view of Khammassi teaches wherein the one or more parameters in the one or more registers are used to control an amplitude and a frequency of the analog pulse (Khammassi Fig. 6 and paragraphs [0060, 0062]).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang as applied to claim 1 above, and further in view of Chen et al. (NPL – “3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation”), hereinafter Chen.
Regarding claim 5, Zhang teaches all the limitations of claim 1 as stated above.
Zhang does not explicitly teach wherein the analog instruction execution circuitry operates in a first clock domain, wherein the digital instruction execution circuitry operates in a second clock domain different from the first clock domain.
However, on the same field of endeavor, Chen discloses a hybrid processing system where one component operates in a different clock domain than another component (Chen page 1652 left col middle “The generated accelerator usually works at a lower frequency than the CPU core … To connect an accelerator to a CPU core working in another clock domain, we add a wrapper to the generated accelerator for interclock-domain communication”; Fig. 4).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Zhang and configure the analog instruction execution circuitry and the digital instruction execution circuitry to operate in different clock domains because analog instruction execution circuitry normally operates at a different (lower) clock frequency than a digital instruction execution circuitry. Further, timing and control of different quantum instructions cannot be guaranteed while one classical instruction is normally processed at each clock cycle (Chen page 1652 left col; Zhang section 5.3.2).
Therefore, the combination of Zhang as modified in view of Chen teaches wherein the analog instruction execution circuitry operates in a first clock domain, wherein the digital instruction execution circuitry operates in a second clock domain different from the first clock domain.
Claims 11 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang as applied to claim 10 above, and further in view of Lacey et al. (US 20200319974 A1), hereinafter Lacey.
Regarding claim 11, Zhang teaches all the limitations of claim 10 as stated above. Further, Zhang teaches further comprising a plurality of processors, (Zhang Figs. 5 and 8; page 907 left col bottom and page 907 right col bottom),
wherein individual processors of the plurality of processors are to execute digital instructions and analog instructions, wherein to execute analog instructions comprises to send an analog signal to a qubit of the plurality of qubits or measure an analog signal from a qubit of the plurality of qubits (Zhang section 5.3; section 5.3.1 “we further employ quantum superscalar to exploit the parallelism of quantum instructions. Figure 8 shows an example of a 4-way quantum superscalar structure. In this architecture, four instructions are fetched into the pre-decoder in one cycle and then dispatched to different pipelines for execution”; section 2.4 “The QCP executes the measurement instruction and starts to wait for the result to return. The measurement operation is performed on the QPU … Repeat-Until-Success (RUS) [28] is a special case of dynamic quantum circuits, which repeatedly execute certain quantum operations and perform a measurement until a success measurement outcome occurs”; program 1 and program 2; section 5.4 “This example indicates that the operation to be performed on qubit 1 should be determined based on the measurement result of qubit 0 … (1) The valid measurement result is returned”; section 6.1).
Zhang does not explicitly teach wherein individual processors are in separate packages.
However, on the same field of endeavor, Lacey discloses a plurality of processors, wherein individual processors are in separate packages (Lacey Figs. 1-2 and paragraph [0058] “each of the processors 2 may be implemented on a separate chip (die) … The chips could be packaged on … different packages”).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Zhang using Lacey and package each processor in a separate package. Lacey discloses that each of the processors may be implemented on a separate chip and the chips could be packaged on the same integrated circuit (IC) package, or different packages, or some on the same package and some on different packages. Therefore, implementing each processor in separate package is obvious to one of ordinary skill in the art. See also MPEP 2144.04(V)(C) for more information.
Therefore ,the combination of Zhang as modified in view of Lacey teaches further comprising a plurality of processors, wherein individual processors are in separate packages.
Regarding claim 17, Zhang teaches all the limitations of claim 10 as stated above. Further, Zhang teaches
further comprising a plurality of processors, (Zhang Figs. 5 and 8; page 907 left col bottom and page 907 right col bottom),
wherein individual processors of the plurality of processors (Zhang section 5.3; section 5.3.1 “we further employ quantum superscalar to exploit the parallelism of quantum instructions. Figure 8 shows an example of a 4-way quantum superscalar structure. In this architecture, four instructions are fetched into the pre-decoder in one cycle and then dispatched to different pipelines for execution”; section 2.4 “The QCP executes the measurement instruction and starts to wait for the result to return. The measurement operation is performed on the QPU … Repeat-Until-Success (RUS) [28] is a special case of dynamic quantum circuits, which repeatedly execute certain quantum operations and perform a measurement until a success measurement outcome occurs”; program 1 and program 2; section 5.4 “This example indicates that the operation to be performed on qubit 1 should be determined based on the measurement result of qubit 0 … (1) The valid measurement result is returned”; section 6.1).
Zhang does not explicitly teach wherein individual processors of the plurality of processors comprises a plurality of processor cores, wherein individual processor cores of the plurality of processor cores of individual processors of the plurality of processors are to execute digital instructions and analog instructions.
However, on the same field of endeavor, Lacey discloses a plurality of processors, wherein individual processors are in separate packages, wherein individual processors of the plurality of processors comprises a plurality of processor cores (Lacey Figs. 1-2 and paragraphs [0058, 0060, 0064] plurality of processor cores – tiles 4).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Zhang using Lacey and package each processor in a separate package. Lacey discloses that each of the processors may be implemented on a separate chip and the chips could be packaged on the same integrated circuit (IC) package, or different packages, or some on the same package and some on different packages. Therefore, implementing each processor in separate package is obvious to one of ordinary skill in the art. See also MPEP 2144.04(V)(C) for more information. Further, configure each processor to include a plurality of processor cores for executing execute digital instructions and analog instructions to increase or achieve parallelism (Lacey paragraph [0006]).
Therefore ,the combination of Zhang as modified in view of Lacey teaches further comprising a plurality of processors, wherein individual processors are in separate packages, wherein individual processors of the plurality of processors comprises a plurality of processor cores, wherein individual processor cores of the plurality of processor cores of individual processors of the plurality of processors are to execute digital instructions and analog instructions, wherein to execute analog instructions comprises to send an analog signal to a qubit of the plurality of qubits or measure an analog signal from a qubit of the plurality of qubits.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang as applied to claim 15 above, and further in view of Nimon (US 5432781 A).
Regarding claim 16, Zhang teaches all the limitations of claim 15 as stated above.
Zhang does not explicitly teach wherein the processor further comprises a core synchronization matrix to synchronize between processor cores of the plurality of processor cores.
However, on the same field of endeavor, Nimon discloses a synchronization matrix to synchronize between processors of a plurality of processors (Nimon claim 1).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Zhang and generalize the teaching of Nimon and configure the processor to include a synchronization matrix to synchronize between processor cores of the plurality of processor cores by generating a synchronization signal and for connecting the processor cores of the plurality of processor cores (Nimon claim 1; col 1 lines 21-47).
Therefore, the combination of Zhang as modified in view of Nimon teaches wherein the processor further comprises a core synchronization matrix to synchronize between processor cores of the plurality of processor cores.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Lacey as applied to claim 17 above, and further in view of Nimon.
Regarding claim 18, Zhang as modified in view of Lacey teaches all the limitations of claim 17 as stated above.
Zhang does not explicitly teach wherein individual processors of the plurality of processors comprise a core synchronization matrix to synchronize with other processors of the plurality of processors.
However, on the same field of endeavor, Nimon discloses a synchronization matrix to synchronize between processors of a plurality of processors (Nimon claim 1).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention, to modify Zhang and generalize the teaching of Nimon and configure each processor to include a synchronization matrix to synchronize between other processors of the plurality of processor cores by generating a synchronization signal and for connecting the processors of the plurality of processor cores (Nimon claim 1; col 1 lines 21-47).
Therefore, the combination of Zhang as modified in view of Nimon teaches wherein individual processors of the plurality of processors comprise a core synchronization matrix to synchronize with other processors of the plurality of processors.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Fu et al. (NPL – “eQASM: An Executable Quantum Instruction Set Architecture”) and Zou (US 20190042971 A1) both discloses an apparatus comprising: a processor comprising a processor core, the processor core comprising: instruction management circuitry, digital instruction execution circuitry and analog instruction execution circuitry, the instruction management circuitry to: receive a plurality of instructions; determine whether individual instructions of the plurality of instructions are digital instructions or analog instructions; transmit individual digital instructions of the plurality of instructions to the digital instruction execution circuitry in response to a determination that the corresponding individual instructions are digital instructions; and transmit individual analog instructions of the plurality of instructions to the analog instruction execution circuitry in response to a determination that the corresponding individual instructions are analog instructions, the analog instruction execution circuitry to execute analog instructions received from the instruction management circuitry, wherein to execute analog instructions comprises to generate or measure an analog signal at an input/output of the processor. Fu et al and Zou are cited in the IDS submitted on 07/07/2026.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlo Waje whose telephone number is (571)272-5767. The examiner can normally be reached 9:00-6:00 M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Carlo Waje/Examiner, Art Unit 2151 (571)272-5767
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