DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 04/16/2026 has been fully considered and entered into record. Claims 1-25 remain pending in the application.
Response to Arguments
Applicant's arguments filed 04/16/2026 have been fully considered but they are not persuasive for the reasons set forth below.
Regarding the Rejection of Claims Under § 112
The § 112(b) rejection of Claim 23 is withdrawn. Applicant’s amendment to the preamble of Claim 23 resolves the indefiniteness issue previously identified. Applicant’s request for withdrawal of this rejection is granted.
Regarding the Rejection of Claims of Claims 1-25 Under 35 U.S.C. § 103
Venugopalan’s Core Teachings Are Not Overcome.
Applicant argues that Venugopalan describes only a horizontal peer-monitoring architecture that is notably different than the vertically- layered architecture of the compute/processing circuitry and therefore does not teach programmable attack detection and response circuitry separate from the compute circuitry or provide the claimed arrangement for attestation between different circuitry.
This argument is partially persuasive with respect to with respect to the specific architectural separation and attestation flow limitation added by amendment, and accordingly a new ground of rejection is set forth below introducing Cheruvu et al. (US 20210089685 A1) to supply those teachings. However, applicant’s argument does not overcome Venugopalan’s core teachings, which remain valid and are not disputed, including:
Identification of operational data from compute circuitry obtained from monitoring of an operational layer, see Venugopalan, section III (d)” logs all IP core deviation in the presence of an attack…”
Evaluation of operational data to identify an attack condition, see ([Venugopalan, [section III (d)]”… Wi detects the anomaly between the specified and the issued duty cycle parameter”;
Provision of a digital attack response causing a countermeasure at the operational layer, see Venugopalan, section III (d)]”… prevents the output of the PWM module from issuing the corrupted duty cycle parameter”;
A hardware RoT serving as the foundation for trust within the apparatus, see Venugopalan, Introduction” hardware Root-of-Trust (RoT) serves as
the foundation for building trust within a CPS”;
These core teachings of Venugopalan are undisputed by applicant’s arguments and remain the basis for the new ground of rejection set forth below.
The Separate Programmable Circuitry Limitation (Claims 1 and 6)
Applicant argues that Venugopalan does not teach programmable attack detection and response circuitry separate from the compute circuitry, characterizing Venugopalan’s TE-FIDES as a horizontal peer-monitoring architecture rather than a vertically-layered architecture with a distinct separate monitoring component.
The Examiner acknowledges that Venugopalan’s TE-FIDES architecture, as presented in the cited portions, does not explicitly frame the Trusted Anchor (TA) as programmable attack detection circuitry separate from the compute circuitry in the manner recited in the amended claims. Accordingly, the Examiner introduces Cheruvu et al. (US 20210089685 A1) in the new ground of rejection below to supply this teaching.
The Attestation Wherein Clause
Applicant argues that neither Venugopalan nor Schulz teaches attestation information being provided from the compute circuitry to the programmable attack detection and response circuitry to verify the attestation of the hardware RoT.
The Examiner acknowledges that Venugopalan does not explicitly disclose this attestation flow, and that Schulz’s attestation teachings are directed to a boot stage measurement sequence rather than the runtime attestation verification flow recited in the amended claims. Accordingly, the Examiner introduces Cheruvu et al. (US 20210089685 A1) in the new ground of rejection below to supply this teaching
Regarding Dependent Claims 4 and 15 (FPGA/ASIC/CPLD)
Applicant ARGUES that Venugopalan does not operate separate attack detection functions on its FPGA fabric and therefore does not teach the specific use of an FPGA, ASIC, or CPLD for the programmable attack detection and response circuitry as recited in claim 4 and 15.
This argument is not persuasive in view of Cheruvu et al. (US 20210089685 A1). Cheruvu explicitly discloses a Field Programmable Gate Array (FPGA) as the separate programmable attack detection circuitry, see Cheruvu Abstract; “processing circuitry operably coupled to the DRAM device, and a field programmable gate array (FPGA) configured to install and provision a memory monitor”. Claims 4 and 15 are therefore rendered obvious by the combination of Venugopalan and Cheruvu as set forth in the new ground of rejection below.
Regarding Dependent Claims 8, 18 and 24-Attestation Enabling Countermeasure.
Applicant argues that Schulz describes only a boot stage which is not the same as the claimed technique for provisioning and enabling a countermeasure after attestation is successfully performed.
This argument is not persuasive in view of Cheruvu. Cheruvu explicitly discloses runtime attestation not merely boot-stage attestation wherein the monitor is deployed onto the FPGA in response to satisfactory attestation DICE RoT, see Cheruvu [0131]:” the FPGA device executes the Monitor, which sends the attestation information to the cloud verifier (e.g., with operation 924)… the cloud verifier listens for attestation information (e.g., in operation 912), verifies the attestation information sent by the FPGA device (e.g., with evaluation 914), and upon failure, reinstalls the monitor onto the FPGA device. Should it happen that the target platform or FPGA in it is restarted (e.g., as a result of a restart), the installed design will again be reverified, or a new design installed.”, and wherein upon attestation failure during ongoing operation, the monitor is reinstalled as corrective countermeasure, see Cheruvu[0131]:” a policy enforcement is triggered (operation 930). Meanwhile, the cloud verifier listens for attestation information (e.g., in operation 912), verifies the attestation information sent by the FPGA device (e.g., with evaluation 914), and upon failure, reinstalls the monitor onto the FPGA device.” The countermeasure is thus directly provisioned and enabled by the outcome of attestation, precisely as recited in claims 8, 18, and 24. Schulz is no longer relied upon for this limitation.
Regarding Dependent Claim 16-DICE Attestation Architecture
Applicant argues that Schulz describes only a generic boot measurement sequence, which is not the same as a DICE attestation architecture and that a person of ordinary skill in the art would recognize that the use of a DICE attestation architecture would involve additional elements and techniques not performed by Schulz.
This argument is well-taken with respect to Schulz. However, it does not result in allowance of claim 16, because Cheruvu explicitly and extensively discloses a DICE attestation architecture with layered IP block trust. See Cheruvu:[0002]”a hardware-based root of trust (RoT) established according to a Device Identifier Composition Engine (DICE) security standard”, [0031] “attestation is performed following the DICE industry standard for obtaining secure identities without secrets being compromised by firmware updates”, [0044]” a DICE (Device Identity Composition Engine) architecture where a DICE hardware building block is used to construct layered trusted computing base contexts for secured and authenticated layering of device capabilities (such as with use of a Field Programmable Gate Array (FPGA))” and [0139]” a DICE RoT at the CPU) … memory controller RoT”.
Regarding Claims 17 and 23
Applicant argues that Venugopalan and Schulz do not teach an attack detection and response engine implemented by circuitry separate from the processing circuitry, nor the attestation flow wherein clause, for the same reasons argued with respect to Claims 1 and 6.
For substantially the same reasons discussed with respect to Claims 1 and 6 above, these arguments are not persuasive in view of Cheruvu. Cheruvu’s FPGA-based TMM architecture satisfies the separate circuitry limitation of Claims 17 and 23. See [0032]” the resources used to implement the TMM are separate from CPU-based resources and are not shared by other CPU workloads. If the TMM becomes corrupted or compromised, a cloud verifier, orchestrator, or other entity may re-deploy a new TMM design rapidly. Finally, as will be well understood, the use of a dedicated FPGA design to contain and operate a TMM enables significant performance and maintainability over the use of alternative approaches.”, and Cheruvu’s DICE-based attestation flow satisfies the attestation wherein clause. The new ground of rejection for claims 17 and 23 is set forth below.
In view of the foregoing, Applicant’s arguments are not persuasive. A new ground of rejection under 35 U.S.C. § 103 of claims 1-25 is set forth below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-25 are rejected under 35 U.S.C. §103 as being unpatentable over Venugopalan et al., “Detecting and Thwarting Hardware Trojan Attacks in Cyber-Physical Systems,” IEEE 2016 [hereinafter “Venugopalan”] in view of Schulz et al., “Boot Attestation: Secure Remote Reporting with Off-The-Shelf IoT Sensors,” ESORICS 2017, LNCS 10493, pp. 437–455 [hereinafter “Schulz”] and in view of Cheruvu et al. (US 20210089685 A1) [hereinafter “Cheruvu”].
As per claim 1, Venugopalan discloses an apparatus, comprising: an interface to compute circuitry, ([Venugopalan, Introduction]” Communication between the IP cores provide
considerable insight into their functionality and can be used to detect anomalies during system operation” and “Legal communication between IP cores is permitted through a declassification process, which enables the higher tag associated with sensitive IP core to declassify to a lower tag to receive information from a non-sensitive IP core or from an I/O peripheral”) the compute circuitry to operate with multiple layers of hardware and software, ([Venugopalan, Introduction]” Cybersecurity encompasses software, hardware, and physical security. Modern System-On-Chip (SoC) platforms blur the distinction between software and hardware boundaries. A CPS may use a mix of microcontrollers, ARM-based SoCs, and Field Programmable Gate Arrays (FPGAs)”)the programmable attack detection and response circuitry to: identify operational data from the compute circuitry, the operational data obtained from monitoring of an operational layer of the multiple layers([Venugopalan, Section III(d)]” logs all IP core deviation in the presence of an attack and also saves the snapshots of the trust metric Qi of each IP core i embedded in the system. Figure 2 shows the TE-FIDES architecture with the components described above and highlights the communication flow from IP core to IP core and from IP core to I/O peripherals”) evaluate the operational data to identify an attack condition; ([Venugopalan, [section III (d)]” Wi detects the anomaly between the specified and the issued duty cycle parameter”) and provide a digital attack response to the compute circuitry, based on identification of the attack condition, the digital attack response to cause a countermeasure at the operational layer; ([Venugopalan, [section III (d)]” Wi prevents the output of the PWM module from issuing the corrupted duty cycle parameter, thus preserving the state of the inverter. In addition, the IP core deviation due to the presence of an attack is also logged in B” and “Thus, TE-FIDES enforces trust in an embedded system in the following ways:
Detection and Prevention: Unauthorized communication of IP cores violating the predefined IP core policy Πi is prevented by the Trusted Wrapper Wi and the Trusted Anchor T A.”).
Venugopalan does not explicitly disclose wherein trust of the compute circuitry is established within the apparatus based on attestation of a hardware root of trust (RoT) at a lower layer of the multiple layers of the compute circuitry; and programmable attack detection and response circuitry separate from the compute circuitry; wherein attestation information is provided from the compute circuitry to the programmable attack detection and response circuitry, to enable the programmable attack detection and response circuitry to verify the attestation of the hardware RoT.
However, Schulz in the same field of endeavor discloses a hardware root of trust (RoT) at a lower layer of the multiple layers of the compute circuitry;([ Schulz, ESORICS 2017, Section 3.2, pp. 442–443]” The prover hardware starts execution at the platform Root of Trust (RoT). This ‘stage 0’ has exclusive access to the root attestation key… Execution then continues at stage 1… The scheme continues through other boot stages … until the main application/runtime has launched”) The examiner interprets this as multiple layers of hardware and software with trust anchored in a lower-layer RoT”).
Therefore, It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to modify Venugopalan apparatus, interface to compute circuitry to further include a hardware root of trust (RoT) at a lower layer of the multiple layers of the compute circuitry as suggested by Schulz. One of ordinary skills in the art would have been motivated to do so because combining Schulz’s RoT-based attestation into Venugopalan’s detection approach represents a predictable use of known security mechanisms to enhance physical device trustworthiness by ensuring that anomaly detection is performed only after the underlying layers have been verified.
The combination of Venugopalan and Schulz fails to disclose wherein trust of the compute circuitry is established within the apparatus based on attestation of a hardware root of trust (RoT) programmable attack detection and response circuitry separate from the compute circuitry; wherein attestation information is provided from the compute circuitry to the programmable attack detection and response circuitry, to enable the programmable attack detection and response circuitry to verify the attestation of the hardware RoT.
However, Cheruvu in the same field of endeavor discloses programmable attack ([Cheruvu, Abstract] “processing circuitry operably coupled to the DRAM device, and a field programmable gate array (FPGA) configured to install and provision a memory monitor”) detection and response circuitry([Cheruvu, [0030]]” a cloud-based verifier may install a TMM, implemented with an FPGA configuration, onto FPGA hardware of an edge computing system, to configure the FPGA hardware to perform internal monitoring and processing of its DRAM status within the edge computing hardware”) separate([Cheruvu, [0032]]” the resources used to implement the TMM are separate from CPU-based resources and are not shared by other CPU workloads.”) from the compute circuitry; wherein attestation information([Cheruvu, [0129]]” Each processing unit may have a different RoT, and a secure interaction that is established and attested between the memory controller RoT and the respective processing unit RoT”) is provided from the compute circuitry to the programmable attack detection and response circuitry, ([Cheruvu, [0131]]” the FPGA device executes the Monitor, which sends the attestation information”) to enable the programmable attack detection and response circuitry to verify ([Cheruvu, [0132]]” apply design 905 may contain a policy for matching memory images that are expected to be or known as good, or otherwise considered to be the reference template or trained template that performs the function of operation 920. Also, operation 910 may obtain reference values (otherwise known as manifests, platform certificates, signed documents, endorsements or attestation tokens) from various manufacturers or vendors of discrete logic, firmware, or software for workloads under inspection,”) the attestation of the hardware RoT([Cheruvu, [0129]]” a secure interaction that is established and attested between the memory controller RoT and the respective processing unit RoT”).
Therefore, It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to modify Venugopalan apparatus, interface to compute circuitry to include a hardware root of trust (RoT) at a lower layer of the multiple layers of the compute circuitry as suggested by Schulz to further include wherein trust of the compute circuitry is established within the apparatus based on attestation of a hardware root of trust (RoT) ; wherein attestation information is provided from the compute circuitry to the programmable attack detection and response circuitry, to enable the programmable attack detection and response circuitry to verify the attestation of the hardware RoT as taught by Cheruvu. One of ordinary skills in the art would have been motivated to do so because incorporating Cheruvu’s FPGA-based monitoring and attestation verification functionality into the modified Venugopalan-Schulz system would have provided an independent hardware mechanism for validating the integrity of the hardware Root of Trust before relying on anomaly detection results. Such modification represents the predictable use of known security techniques to improve trustworthiness, detect compromised system states earlier, and enhance the reliability of attack detection and response operations.
As per claim 2, the references as combined above disclose the apparatus of claim 1. Venugopalan further discloses communication circuitry to communicate the operational data to an attack management service operated by another computing system; ([Venugopalan, [section III ]]” Commercial state-of-the-art DSPs have dedicated hardware for vector control of three-phase systems [26] and therefore used in this example. Untrusted PWM blocks are instantiated in the PL. The Zynq receives system commands and parameters from a remote supervisory unit through the Ethernet controller, while the duty cycles for synthesizing the voltages are received through the SPI module from the DSP. The PWM module generates waveforms with the appropriate duty cycle to drive the three-phase inverter…. Response and Diagnostics: In the event of an attack, the logging buffer B records the details of the attack, which can be accessed externally for further diagnostics” The examiner interprets this as a remote analysis system). Venugopalan further discloses wherein the attack management service coordinates with the programmable attack detection and response circuitry to identify the attack condition and identify the countermeasure.([Venugopalan, [section III (d)]”… Response and Diagnostics: In the event of an attack, the logging buffer B records the details of the attack, which can be accessed externally for further diagnostics” And that “Wi detects the anomaly between the specified and the issued duty cycle parameter”). Claim 2 is rejected under the same rationale as claim 1 above.
As per claim 3, the references as combined above disclose the apparatus of claim 1. Venugopalan further discloses at least one attack detection sensor, operable at the compute circuitry, to generate the operational data from monitoring of the operational layer of the multiple layers.( ([Venugopalan, [section III ]]” The DoS attack interrupts the communication between the sensors and the control system, and may also affect system integrity by modifying sensor data. In contrast, protecting control algorithm code does not also ensure trust in sensor and actuator communication that ultimately bridges the cyber and physical domains.”).Claim 3 is rejected under the same rationale as claim 1 above.
As per claim 4, the references as combined above disclose the apparatus of claim 1. Venugopalan further discloses wherein the programmable attack detection and response circuitry comprises: a field programmable gate array (FPGA), an Application Specific Integrated Circuit (ASIC), or a Complex Programmable Logic Device (CPLD).([ Venugopalan, IV Figure 3]” shows the control interface for driving the three-phase inverter connected to a load. The interface is realized on a MicroZed development board containing a Xilinx Zynq-7020 possessing a dual-core ARM processor and an Artix FPGA with 85K logic cells. The Zynq platform is partitioned into processing system (PS) and programmable logic (PL) sections. The PS region includes peripheral controllers accessible to the ARM cores, whereas the PL region’s FPGA fabric can be used to implement custom computational and controller cores. The Ethernet and Serial Peripheral Interface (SPI) controller cores are trusted, fixed silicon cores implemented in the PS region.”). Claim 4 is rejected under the same rationale as claim 1 above.
As per claim 5, the references as combined disclose the apparatus of claim 1. Venugopalan further discloses wherein the compute circuitry includes at least one of: a central processing unit (CPU) processor, a graphics processing unit (GPU) processor, or a network processor. ([Venugopalan, ]”The interface is realized on a MicroZed development board containing a Xilinx Zynq-7020 possessing a dual-core ARM processor and an Artix FPGA with 85K logic cells. The Zynq platform is partitioned into processing system (PS) and programmable logic (PL) sections”).Claim 5 is rejected under the same rationale as claim 1 above.
As per claim 6, Venugopalan discloses a computing device, comprising: processing circuitry to perform compute operations, ([Venugopalan, Introduction]” Communication between the IP cores provide considerable insight into their functionality and can be used to detect anomalies during system operation” and “Legal communication between IP cores is permitted through a declassification process, which enables the higher tag associated with sensitive IP core to declassify to a lower tag to receive information from a non-sensitive IP core or from an I/O peripheral”)wherein the processing circuitry is to perform the compute operations with use of multiple layers of an IP block of the processing circuitry, ([Venugopalan, Introduction]” Cybersecurity encompasses software, hardware, and physical security. Modern System-On-Chip (SoC) platforms blur the distinction between software and hardware boundaries. A CPS may use a mix of microcontrollers, ARM-based SoCs, and Field Programmable Gate Arrays (FPGAs)”) the attack detection and response circuitry to: identify operational data from the processing circuitry, the operational data obtained from monitoring of an operational layer of the multiple layers of the IP block; ([Venugopalan, Section III(d)]” logs all IP core deviation in the presence of an attack and also saves the snapshots of the trust metric Qi of each IP core i embedded in the system. Figure 2 shows the TE-FIDES architecture with the components described above and highlights the communication flow from IP core to IP core and from IP core to I/O peripherals”)evaluate the operational data to identify an attack condition; ([Venugopalan, [section III (d)]” Wi detects the anomaly between the specified and the issued duty cycle parameter”) and provide a digital attack response to the processing circuitry, based on identification of the attack condition, the digital attack response to cause a countermeasure at the operational layer, ([Venugopalan, [section III (d)]” Wi prevents the output of the PWM module from issuing the corrupted duty cycle parameter, thus preserving the state of the inverter. In addition, the IP core deviation due to the presence of an attack is also logged in B” and “Thus, TE-FIDES enforces trust in an embedded system in the following ways:
Detection and Prevention: Unauthorized communication of IP cores violating the predefined IP core policy Πi is prevented by the Trusted Wrapper Wi and the Trusted Anchor T A.”).
Venugopalan does not explicitly disclose wherein trust of the IP block is established within the computing device based on attestation of a hardware root of trust (RoT) at a lower layer of the multiple layers of the IP block of the processing circuitry; and attack detection and response circuitry separate from the processing circuitry, wherein attestation information is provided from the processing circuitry to the attack detection and response circuitry, to enable the attack detection and response circuitry to verify the attestation of the hardware RoT.
However, Schulz in the same field of endeavor discloses a hardware root of trust (RoT) at a lower layer of the multiple layers of the IP block of the processing circuitry;([ Schulz, ESORICS 2017, Section 3.2, pp. 442–443]” The prover hardware starts execution at the platform Root of Trust (RoT). This ‘stage 0’ has exclusive access to the root attestation key… Execution then continues at stage 1… The scheme continues through other boot stages … until the main application/runtime has launched”) The examiner interprets this as multiple layers of hardware and software with trust anchored in a lower-layer RoT”).
Therefore, It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to modify Venugopalan to include a hardware root of trust (RoT) at a lower layer of the multiple layers of the IP block of the processing circuitry as suggested by Schulz. One of ordinary skills in the art would have been motivated to do so because combining Schulz’s RoT-based attestation into Venugopalan’s detection approach represents a predictable use of known security mechanisms to enhance physical device trustworthiness by ensuring that anomaly detection is performed only after the underlying layers have been verified.
The combination of Venugopalan and Schulz fails to disclose attack detection and response circuitry separate from the processing circuitry, wherein attestation information is provided from the processing circuitry to the attack detection and response circuitry, to enable the attack detection and response circuitry to verify the attestation of the hardware RoT.
However, Cheruvu in the same field of endeavor discloses wherein trust of the IP block is established within the computing device ([Cheruvu, [0125]]”the verifier entity 710 establishes operations based on an implementation of a DICE security architecture, to install the monitor (e.g., a TMM, installed with operation 701) to the configurable hardware 720 in response to satisfactory authentication and attestation of the configurable hardware 720 (e.g., as provided by the DICE RoT 730)” based on attestation of a hardware root of trust (RoT); ([Cheruvu, [0044]]” a DICE hardware building block is used to construct layered trusted computing base contexts for secured and authenticated layering of device capabilities (such as with use of a Field Programmable Gate Array (FPGA)). The RoT also may be used for a trusted computing context to support respective tenant operations, etc”) attack detection ([Cheruvu, [0135]]” This ensures that the cloud verifier can detect possible attacks to the TMM”) and response circuitry ([Cheruvu, [0030]]” a cloud-based verifier may install a TMM, implemented with an FPGA configuration, onto FPGA hardware of an edge computing system, to configure the FPGA hardware to perform internal monitoring and processing of its DRAM status within the edge computing hardware”) separate ([Cheruvu, [0032]]” the resources used to implement the TMM are separate from CPU-based resources and are not shared by other CPU workloads.”) from the processing circuitry, wherein attestation information ([Cheruvu, [0129]]” Each processing unit may have a different RoT, and a secure interaction that is established and attested between the memory controller RoT and the respective processing unit RoT”) is provided from the processing circuitry to the attack detection and response circuitry, ([Cheruvu, [0131]]” the FPGA device executes the Monitor, which sends the attestation information”) to enable the attack detection and response circuitry to verify ([Cheruvu, [0132]]” apply design 905 may contain a policy for matching memory images that are expected to be or known as good, or otherwise considered to be the reference template or trained template that performs the function of operation 920. Also, operation 910 may obtain reference values (otherwise known as manifests, platform certificates, signed documents, endorsements or attestation tokens) from various manufacturers or vendors of discrete logic, firmware, or software for workloads under inspection,”) the attestation of the hardware RoT. ([Cheruvu, [0129]]” a secure interaction that is established and attested between the memory controller RoT and the respective processing unit RoT”).
Therefore, It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to modify Venugopalan apparatus, interface to compute circuitry to include a hardware root of trust (RoT) at a lower layer of the multiple layers of the IP block of the processing circuitry as suggested by Schulz to further include wherein trust of the IP block is established within the computing device based on attestation of a hardware root of trust (RoT); attack detection and response circuitry separate from the processing circuitry, wherein attestation information is provided from the processing circuitry to the attack detection and response circuitry, to enable the attack detection and response circuitry to verify the attestation of the hardware RoT as taught by Cheruvu. One of ordinary skills in the art would have been motivated to do so because incorporating Cheruvu’s FPGA-based monitoring and attestation verification functionality into the modified Venugopalan-Schulz system would have provided an independent hardware mechanism for validating the integrity of the hardware Root of Trust before relying on anomaly detection results. Such modification represents the predictable use of known security techniques to improve trustworthiness, detect compromised system states earlier, and enhance the reliability of attack detection and response operations.
As per claim 7, the references as combined above disclose the computing device of claim 6. Cheruvu further discloses wherein the attack detection and response circuitry is further to, prior to identification of the attack condition: ([Cheruvu, [0131]]” the FPGA device verifies the Monitor (e.g., with verification of a digital signature, in operation 920). If the verification succeeds (e.g., the signature is ok, in evaluation 922), the FPGA device executes the Monitor…the FPGA device then continues monitoring operations by checking the DRAM state with the Monitor. If the DRAM state… is corrupt…a policy enforcement is triggered”) perform attestation of the IP block of the processing circuitry, ([Cheruvu, [0125]]” the verifier entity 710 establishes operations based on an implementation of a DICE security architecture, to install the monitor (e.g., a TMM, installed with operation 701) to the configurable hardware 720 in response to satisfactory authentication and attestation of the configurable hardware 720 (e.g., as provided by the DICE RoT 730)”)based on the attestation of the multiple layers including the operational layer of the IP block; ([Cheruvu, [0128], [0139]]” The memory hierarchy, accessible through the DRAM memory 850, the Cache 860, and the CPU/GPU 870, and the execution and instruction pipeline that relates those pieces together, may be verified through monitoring memory via a deployed and attested TMM instance 840 operated in the configurable hardware, as depicted with an ASIC/FPGA 820” and “The memory controller 1080 and the uncore 1090 may have an associated DICE RoT (e.g., with memory controller RoT 1084, and with S3M 1094, a DICE RoT at the CPU) which enables trusted software operations to be attested and performed.”)and cause provisioning at the IP block of the processing circuitry([Cheruvu, [0125]]” the verifier entity 710 establishes operations based on an implementation of a DICE security architecture, to install the monitor (e.g., a TMM, installed with operation 701) to the configurable hardware 720 in response to satisfactory authentication and attestation of the configurable hardware 720 (e.g., as provided by the DICE RoT 730)”) to enable the countermeasure at the operational layer([Cheruvu, [0131]]” If the DRAM state (e.g., regions 1 and/or 2) is corrupt (e.g., collected with operation 926, and identified in evaluation 928), a policy enforcement is triggered (operation 930).”). Claim 7 is rejected under the same rationale as claim 6 above.
As per claim 8, the references as combined above disclose the computing device of claim 6. Cheruvu further discloses wherein the countermeasure at the operational layer is pre-provisioned to enable the countermeasure([Cheruvu, [0131]]” the FPGA device verifies the Monitor (e.g., with verification of a digital signature, in operation 920). If the verification succeeds (e.g., the signature is ok, in evaluation 922), the FPGA device executes the Monitor…the FPGA device then continues monitoring operations by checking the DRAM state with the Monitor. If the DRAM state… is corrupt…a policy enforcement is triggered”. The Examiner interprets Cheruvu’s disclosure as the policy enforcement mechanism which is the countermeasure is already deployed/installed as part of the FPGA design at operation 910 before any DRAM corruption detected. Thus, the countermeasure is pre-provisioned at the time of FPGA design installation and is subsequently enabled upon detection of the attack condition as claimed [0030]” a cloud-based verifier may install a TMM, implemented with an FPGA configuration, onto FPGA hardware of an edge computing system, to configure the FPGA hardware to perform internal monitoring and processing of its DRAM status within the edge computing hardware”). Claim 8 is rejected under the same rationale as claim 6 above.
As per claim 9, the references as combined above disclose the computing device of claim 6. Schulz further discloses wherein the attack detection and response circuitry includes a plurality of operational layers, and wherein the attack detection and response circuitry is further to provide attestation of the plurality of operational layers .([ Schulz, ESORICS 2017, Section 3.2, pp. 442-443]” The scheme continues through other boot stages x ∈ {1,..., k} until the main application/runtime has launched in stage k. In each stage, a measurement mx+1 of the next firmware stage is taken and extended into the measurement state ...” to an attestation verifier service operated by another computing device.([ Schulz, ESORICS 2017, Section 2.3, pp. 440]” Remote Attestation is a security scheme where a verifier V wants to gain assurance that the firmware state of the prover P has not been subject to compromise”). Therefore, it would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to modify Venugopalan’s computing device to include wherein the attack detection and response circuitry is further to provide attestation of the plurality of operational layers to an attestation verifier service operated by another computing as suggested by Schulz. One of ordinary skill in the art would have been motivated to do so because Schulz teaches remote attestation of multiple operational layers to an external verifier to establish platform trust, thereby enabling a separate computing device to validate system integrity and security state during operation.
As per claim 10, the references as combined above disclose the computer device of claim 6. Venugopalan discloses wherein identification of the attack condition is based on at least one detection algorithm that analyzes the operational data obtained from the processing circuitry. ([Venugopalan, [section III ]]” Each core <Core>i will provide a suite of measurements based on its statistical properties such as memory utilization and latency. These properties will be monitored to detect behavior deviations in the presence of a HTT.”).Claim 10 is rejected under the same rationale as claim 6 above.
As per claim 11, the references as combined above disclose the computer device of claim 6. Venugopalan further discloses wherein the attack detection and response circuitry is further to: communicate operational data to an attack management service operated by another computing device; ([Venugopalan, [section III ]]” Commercial state-of-the-art DSPs have dedicated hardware for vector control of three-phase systems [26] and therefore used in this example. Untrusted PWM blocks are instantiated in the PL. The Zynq receives system commands and parameters from a remote supervisory unit through the Ethernet controller, while the duty cycles for synthesizing the voltages are received through the SPI module from the DSP. The PWM module generates waveforms with the appropriate duty cycle to drive the three-phase inverter…. Response and Diagnostics: In the event of an attack, the logging buffer B records the details of the attack, which can be accessed externally for further diagnostics” The examiner interprets this as a remote analysis system).wherein the attack management service coordinates with the attack detection and response circuitry to identify the attack condition and identify the countermeasure. ([Venugopalan, [section III (d)]”… Response and Diagnostics: In the event of an attack, the logging buffer B records the details of the attack, which can be accessed externally for further diagnostics” And that “Wi detects the anomaly between the specified and the issued duty cycle parameter”). Claim 11 is rejected under the same rationale as claim 6 above.
As per claim 12, the references as combined above disclose the computing device of claim 6. Venugopalan discloses wherein the operational data received from the processing circuitry includes an attack detect message generated by the processing circuitry, the attack detect message including data from at least one attack detection sensor at the processing circuitry. ([Venugopalan, [section III ]]” The Zynq receives system commands and parameters from a remote supervisory unit through the Ethernet controller, while the duty cycles for synthesizing the voltages are received through the SPI module from the DSP. The PWM module generates waveforms with the appropriate duty cycle to drive the three-phase inverter.”). Claim 12 is rejected under the same rationale as claim 6 above.
As per claim 13, the references as combined above disclose the computing device of claim 12. Venugopalan discloses wherein the at least one attack detection sensor is operated for at least one of the multiple layers using at least one: tamper sensor; traffic monitoring sensor, or bus monitoring sensor.([Venugopalan, pp. 1-introduction, pp.4–6, Fig. 2] “In addition, the trust metric is implemented using a secure enclave approach for access and cannot be modified by the Trusted Anchor or external events ….TE-FIDES relies on tag-based information flow control to implement decentralized and safe flow of information between various elements in a system. During the initialization phase, each IP core <Core>i has its Trusted Wrapper
W
i
assigned a tag
τ
i
corresponding to the characteristics (
α
) of the information accessed/processed by…. facilitate legal communication between IP cores and peripherals”.”) The examiner interprets trusted wrapper and a secure enclave as a trusted environment for monitoring internal signals, bus activity as operation of tamper, traffic monitoring, and bus monitoring sensors during execution. Venugopalan does not disclose wherein the computing operations performed by the processing circuitry include execution of a workload in a trusted execution environment. However, Schulz discloses wherein the computing operations performed by the processing circuitry include execution of a workload in a trusted execution environment ([ Schulz, ESORICS 2017, Section 3.2, pp. 442–443]” The prover hardware starts execution at the platform Root of Trust (RoT). This ‘stage 0’ has exclusive access to the root attestation key… Execution then continues at stage 1… The scheme continues through other boot stages … until the main application/runtime has launched”). Claim 13 is rejected under the same rationale as claim 6 above.
As per claim 14, the references as combined above disclose the computing device of claim 6. Venugopalan discloses wherein the attack condition is identified as a cyber-attack, a physical attack, or a side-channel attack, and wherein the countermeasure includes at least one of: erasing memory; disabling access; halting processor operations; sandboxing; data substitution; activation of a honeypot; or a cryptographic lockdown. ([Venugopalan, abstract, p.1, p.5 ] “Many of the cyber-attacks are successful as they are designed to selectively target a specific hardware or software component in an embedded system and trigger its failure....Existing security measures also use attack vector models and isolate the malicious component as a countermeasure.” (Abstract, p.1) and “Wi prevents the output of the PWM module from issuing the corrupted duty cycle parameter, thus preserving the state of the inverter.” (p.5) ). Claim 14 is rejected under the same rationale as claim 6 above.
As per claim 15, the references as combined above disclose the computing device of claim 6. Venugopalan discloses wherein the attack detection and response circuitry is a configured field programmable gate array (IiPGA), Application Specific Integrated Circuit (ASIC), or Complex Programmable Logic Device (CPLD). ([ Venugopalan, IV Figure 3]” shows the control interface for driving the three-phase inverter connected to a load. The interface is realized on a MicroZed development board containing a Xilinx Zynq-7020 possessing a dual-core ARM processor and an Artix FPGA with 85K logic cells. The Zynq platform is partitioned into processing system (PS) and programmable logic (PL) sections. The PS region includes peripheral controllers accessible to the ARM cores, whereas the PL region’s FPGA fabric can be used to implement custom computational and controller cores. The Ethernet and Serial Peripheral Interface (SPI) controller cores are trusted, fixed silicon cores implemented in the PS region.”) Venugopalan does not explicitly disclose wherein the processing circuitry is a System-on-Chip device. However, Schulz in the same field of endeavor disclose wherein the processing circuitry is a System-on-Chip device, ([Schulz, Section 2.1, pp. 439]” Modern MCUs combine CPU, memory, basic peripherals, and selected communication interfaces on a single System on Chip (SoC), as illustrated in Fig. 1”). Claim 15 is rejected under the same rationale as claim 6 above.
As per claim 16, the references as combined above disclose the computing device of claim 6. Schulz further discloses wherein the multiple layers of the IP block are established according to a Device Identifier Composition Engine (DICE) attestation architecture, and wherein the attestation of the hardware RoT is based on attestation according to the DICE attestation architecture. ([Schulz, Section 3.2, pp. 442–443] “the prover P builds its chain of trust from the Root of Trust to a possible stage 1 (bootloader) and stage 2 (application). Once booted, the prover may be challenged by V to report its firmware state by demonstrating possession of the implicitly authenticated measurement state AK2….The prover hardware starts execution at the platform Root of Trust (RoT”). The examiner interprets this staged, compositional measurement process as corresponding to a DICE-style attestation architecture. Claim 16 is rejected under the same rationale as claim 6 above.
As per claim 17, Venugopalan discloses a method for implementing attack detection and response in a computing system, comprising operations performed by an attack detection and response engine of the computing system, the method comprising: identifying operational data from processing circuitry of the computing system, ([Venugopalan, Section III(d)]” logs all IP core deviation in the presence of an attack and also saves the snapshots of the trust metric Qi of each IP core i embedded in the system. Figure 2 shows the TE-FIDES architecture with the components described above and highlights the communication flow from IP core to IP core and from IP core to I/O peripherals”) wherein the processing circuitry is to perform computing operations with use of multiple layers of the processing circuitry, ([Venugopalan, Introduction]” Cybersecurity encompasses software, hardware, and physical security. Modern System-On-Chip (SoC) platforms blur the distinction between software and hardware boundaries. A CPS may use a mix of microcontrollers, ARM-based SoCs, and Field Programmable Gate Arrays (FPGAs)”) evaluating the operational data to identify an attack condition at the processing circuitry, ([Venugopalan, [section III (d)]” Wi detects the anomaly between the specified and the issued duty cycle parameter”) and providing a digital attack response to the processing circuitry, based on identifying the attack condition, the digital attack response to cause a countermeasure at the operational layer ([Venugopalan, [section III (d)]” Wi prevents the output of the PWM module from issuing the corrupted duty cycle parameter, thus preserving the state of the inverter. In addition, the IP core deviation due to the presence of an attack is also logged in B” and “Thus, TE-FIDES enforces trust in an embedded system in the following ways:
Detection and Prevention: Unauthorized communication of IP cores violating the predefined IP core policy Πi is prevented by the Trusted Wrapper Wi and the Trusted Anchor T A.”) wherein the operational data is obtained from monitoring of an operational layer of the multiple layers; , ([Venugopalan, Section III(d)]” logs all IP core deviation in the presence of an attack and also saves the snapshots of the trust metric Qi of each IP core i embedded in the system. Figure 2 shows the TE-FIDES architecture with the components described above and highlights the communication flow from IP core to IP core and from IP core to I/O peripherals”) .
Venugopalan does not explicitly disclose wherein trust of the processing circuitry is established in the computing system based on attestation of a hardware root of trust (RoT) at a lower layer of the multiple layers of the processing circuitry; wherein attestation information is provided from the processing circuitry to the attack detection and response engine, to enable the attack detection and response engine to verify the attestation of the hardware RoT, and wherein the attack detection and response engine is implemented by circuitry separate from the processing circuitry.
However, Schulz in the same field of endeavor discloses a hardware root of trust (RoT) at a lower layer of the multiple layers of the processing circuitry;([ Schulz, ESORICS 2017, Section 3.2, pp. 442–443]” The prover hardware starts execution at the platform Root of Trust (RoT). This ‘stage 0’ has exclusive access to the root attestation key… Execution then continues at stage 1… The scheme continues through other boot stages … until the main application/runtime has launched”) The examiner interprets this as multiple layers of hardware and software with trust anchored in a lower-layer RoT”).
Therefore, It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to modify Venugopalan to further include a hardware root of trust (RoT) at a lower layer of the multiple layers of the processing circuitry as suggested by Schulz. One of ordinary skills in the art would have been motivated to do so because combining Schulz’s RoT-based attestation into Venugopalan’s detection approach represents a predictable use of known security mechanisms to enhance physical device trustworthiness by ensuring that anomaly detection is performed only after the underlying layers have been verified.
The combination of Venugopalan and Schulz fails to disclose wherein trust of the processing circuitry is established in the computing system based on attestation of a hardware root of trust (RoT) ; wherein attestation information is provided from the processing circuitry to the attack detection and response engine, to enable the attack detection and response engine to verify the attestation of the hardware RoT, and wherein the attack detection and response engine is implemented by circuitry separate from the processing circuitry.
However, Cheruvu in the same field of endeavor discloses wherein trust of the processing circuitry is established in the computing system([Cheruvu, [0125]]”the verifier entity 710 establishes operations based on an implementation of a DICE security architecture, to install the monitor (e.g., a TMM, installed with operation 701) to the configurable hardware 720 in response to satisfactory authentication and attestation of the configurable hardware 720 (e.g., as provided by the DICE RoT 730)” based on attestation of a hardware root of trust (RoT); ([Cheruvu, [0044]]” a DICE hardware building block is used to construct layered trusted computing base contexts for secured and authenticated layering of device capabilities (such as with use of a Field Programmable Gate Array (FPGA)). The RoT also may be used for a trusted computing context to support respective tenant operations, etc”) wherein attestation information ([Cheruvu, [0129]]” Each processing unit may have a different RoT, and a secure interaction that is established and attested between the memory controller RoT and the respective processing unit RoT”) is provided from the processing circuitry to the attack detection and response engine, ([Cheruvu, [0131]]” the FPGA device executes the Monitor, which sends the attestation information”)to enable the attack detection and response engine to verify ([Cheruvu, [0132]]” apply design 905 may contain a policy for matching memory images that are expected to be or known as good, or otherwise considered to be the reference template or trained template that performs the function of operation 920. Also, operation 910 may obtain reference values (otherwise known as manifests, platform certificates, signed documents, endorsements or attestation tokens) from various manufacturers or vendors of discrete logic, firmware, or software for workloads under inspection,”) the attestation of the hardware RoT, ([Cheruvu, [0129]]” a secure interaction that is established and attested between the memory controller RoT and the respective processing unit RoT”) and wherein the attack detection and response engine is implemented by circuitry separate([Cheruvu, [0032]]” the resources used to implement the TMM are separate from CPU-based resources and are not shared by other CPU workloads.”) from the processing circuitry.
Therefore, It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to modify Venugopalan apparatus, interface to compute circuitry to include a hardware root of trust (RoT) at a lower layer of the multiple layers of the compute circuitry as suggested by Schulz to further include wherein attestation information is provided from the processing circuitry to the attack detection and response engine, to enable the attack detection and response engine to verify the attestation of the hardware RoT, and wherein the attack detection and response engine is implemented by circuitry separate from the processing circuitry as taught by Cheruvu. One of ordinary skills in the art would have been motivated to do so because incorporating Cheruvu’s FPGA-based monitoring and attestation verification functionality into the modified Venugopalan-Schulz system would have provided an independent hardware mechanism for validating the integrity of the hardware Root of Trust before relying on anomaly detection results. Such modification represents the predictable use of known security techniques to improve trustworthiness, detect compromised system states earlier, and enhance the reliability of attack detection and response operations.
As per claim 18, the substance of the claimed invention is identical or substantially similar to that of claim 7. Accordingly, this claim is rejected under the same rationale.
As per claim 19, the substance of the claimed invention is identical or substantially similar to that of claim 8. Accordingly, this claim is rejected under the same rationale.
As per claim 20, the substance of the claimed invention is identical or substantially similar to that of claim 10. Accordingly, this claim is rejected under the same rationale.
As per claim 21, the substance of the claimed invention is identical or substantially similar to that of claim 11. Accordingly, this claim is rejected under the same rationale.
As per claim 22, the substance of the claimed invention is identical or substantially similar to that of claim 14. Accordingly, this claim is rejected under the same rationale.
As per claim 23, Venugopalan discloses at least one non-transitory machine-readable storage medium comprising instructions stored thereupon, wherein the instructions, when executed by a computing system, cause the computing system to perform operations with an attack detection and response engine comprising: identifying operational data from processing circuitry of the computing system, ([Venugopalan, Section III(d)]” logs all IP core deviation in the presence of an attack and also saves the snapshots of the trust metric Qi of each IP core i embedded in the system. Figure 2 shows the TE-FIDES architecture with the components described above and highlights the communication flow from IP core to IP core and from IP core to I/O peripherals”)wherein the processing circuitry is to perform computing operations with use of multiple layers of the processing circuitry, ([Venugopalan, Introduction]” Cybersecurity encompasses software, hardware, and physical security. Modern System-On-Chip (SoC) platforms blur the distinction between software and hardware boundaries. A CPS may use a mix of microcontrollers, ARM-based SoCs, and Field Programmable Gate Arrays (FPGAs)”)evaluating the operational data to identify an attack condition at the processing circuitry, ([Venugopalan, [section III (d)]” Wi detects the anomaly between the specified and the issued duty cycle parameter”) and providing a digital attack response to the processing circuitry, based on identifying the attack condition, the digital attack response to cause a countermeasure at the operational layer ([Venugopalan, [section III (d)]” Wi prevents the output of the PWM module from issuing the corrupted duty cycle parameter, thus preserving the state of the inverter. In addition, the IP core deviation due to the presence of an attack is also logged in B” and “Thus, TE-FIDES enforces trust in an embedded system in the following ways:
Detection and Prevention: Unauthorized communication of IP cores violating the predefined IP core policy Πi is prevented by the Trusted Wrapper Wi and the Trusted Anchor T A.”)wherein the operational data is obtained from monitoring of an operational layer of the multiple layers; ([Venugopalan, Section III(d)]” logs all IP core deviation in the presence of an attack and also saves the snapshots of the trust metric Qi of each IP core i embedded in the system. Figure 2 shows the TE-FIDES architecture with the components described above and highlights the communication flow from IP core to IP core and from IP core to I/O peripherals”) .
Venugopalan does not explicitly disclose wherein trust of the processing circuitry is established in the computing system based on attestation of a hardware root of trust (RoT at a lower layer of the multiple layers of the processing circuitry; wherein attestation information is provided from the processing circuitry to the attack detection and response engine, to enable the attack detection and response engine to verify the attestation of the hardware RoT, and wherein the attack detection and response engine is implemented by circuitry separate from the processing circuitry.
However, Schulz in the same field of endeavor discloses a hardware root of trust (RoT) at a lower layer of the multiple layers of the processing circuitry;([ Schulz, ESORICS 2017, Section 3.2, pp. 442–443]” The prover hardware starts execution at the platform Root of Trust (RoT). This ‘stage 0’ has exclusive access to the root attestation key… Execution then continues at stage 1… The scheme continues through other boot stages … until the main application/runtime has launched”) The examiner interprets this as multiple layers of hardware and software with trust anchored in a lower-layer RoT”).
Therefore, It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to modify Venugopalan to further include a hardware root of trust (RoT) at a lower layer of the multiple layers of the processing circuitry as suggested by Schulz. One of ordinary skills in the art would have been motivated to do so because combining Schulz’s RoT-based attestation into Venugopalan’s detection approach represents a predictable use of known security mechanisms to enhance physical device trustworthiness by ensuring that anomaly detection is performed only after the underlying layers have been verified.
The combination of Venugopalan and Schulz fails to disclose wherein trust of the processing circuitry is established in the computing system based on attestation of a hardware root of trust (RoT); wherein attestation information is provided from the processing circuitry to the attack detection and response engine, to enable the attack detection and response engine to verify the attestation of the hardware RoT, and wherein the attack detection and response engine is implemented by circuitry separate from the processing circuitry.
However, Cheruvu in the same field of endeavor discloses wherein trust of the processing circuitry is established in the computing system ([Cheruvu, [0125]]”the verifier entity 710 establishes operations based on an implementation of a DICE security architecture, to install the monitor (e.g., a TMM, installed with operation 701) to the configurable hardware 720 in response to satisfactory authentication and attestation of the configurable hardware 720 (e.g., as provided by the DICE RoT 730)” based on attestation of a hardware root of trust (RoT); ([Cheruvu, [0044]]” a DICE hardware building block is used to construct layered trusted computing base contexts for secured and authenticated layering of device capabilities (such as with use of a Field Programmable Gate Array (FPGA)). The RoT also may be used for a trusted computing context to support respective tenant operations, etc”) wherein attestation information ([Cheruvu, [0129]]” Each processing unit may have a different RoT, and a secure interaction that is established and attested between the memory controller RoT and the respective processing unit RoT”) is provided from the processing circuitry to the attack detection and response engine, ([Cheruvu, [0131]]” the FPGA device executes the Monitor, which sends the attestation information”)to enable the attack detection and response engine to verify ([Cheruvu, [0132]]” apply design 905 may contain a policy for matching memory images that are expected to be or known as good, or otherwise considered to be the reference template or trained template that performs the function of operation 920. Also, operation 910 may obtain reference values (otherwise known as manifests, platform certificates, signed documents, endorsements or attestation tokens) from various manufacturers or vendors of discrete logic, firmware, or software for workloads under inspection,”) the attestation of the hardware RoT, ([Cheruvu, [0129]]” a secure interaction that is established and attested between the memory controller RoT and the respective processing unit RoT”) and wherein the attack detection and response engine is implemented by circuitry separate([Cheruvu, [0032]]” the resources used to implement the TMM are separate from CPU-based resources and are not shared by other CPU workloads.”) from the processing circuitry.
Therefore, It would have been obvious before the effective filing date of the claimed invention for one of ordinary skill in the art to modify Venugopalan apparatus, interface to compute circuitry to include a hardware root of trust (RoT) at a lower layer of the multiple layers of the compute circuitry as suggested by Schulz to further include wherein trust of the processing circuitry is established in the computing system; wherein attestation information is provided from the compute circuitry to the programmable attack detection and response circuitry, to enable the programmable attack detection and response circuitry to verify the attestation of the hardware RoT as taught by Cheruvu. One of ordinary skills in the art would have been motivated to do so because incorporating Cheruvu’s FPGA-based monitoring and attestation verification functionality into the modified Venugopalan-Schulz system would have provided an independent hardware mechanism for validating the integrity of the hardware Root of Trust before relying on anomaly detection results. Such modification represents the predictable use of known security techniques to improve trustworthiness, detect compromised system states earlier, and enhance the reliability of attack detection and response operations.
As per claim 24, the substance of the claimed invention is identical or substantially similar to that of claim 7. Accordingly, this claim is rejected under the same rationale.
As per claim 25, the references as combined above disclose at least one non-transitory machine-readable storage medium of claim 23. Venugopalan discloses the operations further comprising: communicating the operational data to an attack management service operated by another computing system; wherein the attack management service provides data to identify the attack condition and identify the countermeasure. ([Venugopalan, [section III ]]” Commercial state-of-the-art DSPs have dedicated hardware for vector control of three-phase systems [26] and therefore used in this example. Untrusted PWM blocks are instantiated in the PL. The Zynq receives system commands and parameters from a remote supervisory unit through the Ethernet controller, while the duty cycles for synthesizing the voltages are received through the SPI module from the DSP. The PWM module generates waveforms with the appropriate duty cycle to drive the three-phase inverter.” The examiner interprets this as a remote analysis system).Claim 25 is rejected under the same rationale as claim 23 above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
Abbaszadeh et al, (US 20200089874 A1) discloses local and global fusion for Cyber-Physical system abnormal detection.
Cambou et al, (US10454691 B2) discloses Systems implementing hierarchical levels of security.
Rieger et al, (US 20200175171 A1) discloses system and methods for control system security.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Komi N. AMEVIGBE whose telephone number is (571)272-3381. The examiner can normally be reached Monday-Friday 2pm-10pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Carl Colin can be reached at (571) 272-3862. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/K.N.A./
Examiner, Art Unit 2493
/CARL G COLIN/Supervisory Patent Examiner, Art Unit 2493
Prosecution Insights