DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this application.
Response to Arguments
Applicant’s arguments regarding the rejections of claims 1-20 under 35 U.S.C. 112b have been fully considered and are persuasive. The rejections have been withdrawn. However, new 35 U.S.C. 112b rejections are applied to claims 1-20 based on the amendments.
Applicant’s arguments regarding the rejections of claims 1-20 under 35 U.S.C. 101 have been fully considered and are persuasive. The rejections have been withdrawn.
Applicant's arguments regarding the 35 U.S.C. 103 rejections of claims 1-20 have been fully considered but they are moot in light of the references being applied in the current rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claims 1, 7, and 15 (line numbers refer to claim 1):
Line 13 recites “memory commands” and line 18 recites “memory commands” so it is unclear if they refer to the same memory commands.
Claims 2-6, 8-14, 16-20 are dependent claims of claims 1, 7, and 15, respectively, and fail to resolve the deficiencies of claims 1, 7, and 15, so they are rejected for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-10, and 13-18 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 20190188078 A1 hereinafter Yu), in view of Shekar et al. (US 20180232142 A1 hereinafter Shekar), and further in view of Wu et al. (US 20110238775 A1 hereinafter Wu).
As per claim 1, Yu teaches a method for managing diversified memory, the method comprising: in a first execution pipeline that targets a first memory device, translating a first job descriptor into one or more first commands for transmission to a first memory manager of the first memory device, and in parallel with translating the first job descriptor, and in a second execution pipeline, translating a second job descriptor into one or more second commands for transmission to a second memory manager of the second memory device (Fig. 13; [0081] Memory interfaces 211_1 to 211_k may be connected to memory devices 230_1 to 230_k via channels CH1 to CHk, respectively. Each of ECC circuits 212_1 to 212_k may divide data received together with a write request from a host and perform parallel encoding to thereby generate sub-codewords. The generated sub-codewords may be stored in memory devices 230_1 to 230_k in a distributed manner; Encoding is a form of translation.).
Yu fails to teach a method for managing diversified virtual memory, the method comprising: one or more first commands for transmission to a first virtual memory manager ("VMM") of the first memory device, wherein the one or more first commands are memory commands for a first interface protocol for the first VMM; one or more second commands for transmission to a second VMM of the second memory device, wherein the one or more second commands are memory commands for a second interface protocol different than the first interface protocol.
However, Shekar teaches a method for managing diversified virtual memory, the method comprising ([0079] Both storage systems 700A of FIG. 7A and storage system 700B of FIG. 7B include a storage array 102, and two storage VMs (e.g., virtual storage controllers); [0034] For network storage, one or more storage arrays 102 provide storage services to one or more host applications executing on host servers 116, 118 and/or host applications on HCIs 200. In addition, one or more storage arrays 102 may provide storage services to one or more clients 120. The configuration of the one or more storage arrays 102 working in combination will depend on the implementation of the storage arrays 102 and the demand by application. Network 122 provides transport for the data exchanges between the one or more storage arrays 102 and hosts 116 or clients 120.): one or more first commands for transmission to a first virtual memory manager ("VMM") of the first memory device ([0008] the first virtual storage controller when operating in active mode is configured for handling the IOs originating from the first applications and the second applications and accessing the storage array.), wherein the one or more first commands are memory commands for a first interface protocol for the first VMM ([0047] When an IO operation is requested by one of the applications 155, the initiator 244 establishes a connection with storage array 102 in one of the supported formats (e.g., iSCSI, or any other protocol); [0057] the first virtual storage controller is configured for direct iSCSI access to the storage array.); one or more second commands for transmission to a second VMM of the second memory device ([0058] the second virtual storage controller is configured for direct access to the storage array, and includes operating in a pass-through mode with regards to the second virtualization layer, such that accesses to the storage array from the second virtual storage controller bypasses the second virtualization layer; [0055] That is, the second storage controller is also configured for handling IOs requesting access to the storage array and includes a storage operating system used to perform operating system functions (e.g., for handling IOs) used to access the physical storage array).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Yu with the teachings of Shekar to increase performance (see Shekar [0007] The present embodiments are directed to providing increased performance to host systems when accessing data storage.).
Yu and Shekar fail to teach wherein the one or more second commands are memory commands for a second interface protocol different than the first interface protocol.
However, Wu teaches wherein the one or more second commands are memory commands for a second interface protocol different than the first interface protocol ([0032] Examples of storage array network interfaces suitable for use with embodiments of the invention include Ethernet, Fibre Channel, IP, and InfiniBand interfaces. Examples of storage array network protocols include ATA, Fibre Channel Protocol, and SCSI. Various combinations of storage array network interfaces and protocols are suitable for use with embodiments of the invention, including iSCSI, HyperSCSI, Fibre Channel over Ethernet, and iFCP. In cases where the storage array network interface uses Ethernet, an embodiment of the branch virtual storage array interface 120 can use the branch LAN's physical connections and networking equipment for communicating with client systems and application services. In other embodiments, separate connections and networking equipment, such as Fibre Channel networking equipment, is used to connect the branch virtual storage array interface 120 with client systems 108 and/or application servers 109; [0090] As described above, storage clients can interact with virtual storage arrays in the same manner that they would interact with physical storage arrays. This includes issuing storage commands to the branch virtual storage interface using storage array network protocols such as iSCSI or Fibre Channel protocol. Most storage array network protocols organize data according to storage blocks, each of which has a unique storage address or location. A storage block's unique storage address may include logical unit number (using the SCSI protocol) or other representation of a logical volume; [0041] In an embodiment, each of the branches 155 includes its own separate virtual storage array; [0042] In a further embodiment, data optimizations such as data compression and data deduplication can be applied to each branch's virtual storage array data 180 separately).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Yu and Shekar with the teachings of Wu to improve efficiency (see Wu [0002] The present invention relates generally to data storage systems, and systems and methods to improve storage efficiency, compactness, performance, reliability, and compatibility.).
As per claim 2, Yu, Shekar, and Wu teach the method of claim 1. Wu teaches further comprising selecting the first execution pipeline for the first job descriptor based on the first execution pipeline being designated to process job descriptors for a range of physical addresses that corresponds to one or more addresses of the indication in the job descriptor ([0090] Most storage array network protocols organize data according to storage blocks, each of which has a unique storage address or location. A storage block's unique storage address may include logical unit number (using the SCSI protocol) or other representation of a logical volume; [0091] In an embodiment, the virtual storage arrays provided by branch virtual storage interfaces allow storage clients to access storage blocks by their unique storage address within the virtual storage array; [0042] In a further embodiment, data optimizations such as data compression and data deduplication can be applied to each branch's virtual storage array data 180 separately).
As per claim 3, Yu, Shekar, and Wu teach the method of claim 1. Wu teaches wherein the first execution pipeline receives job descriptors in an order that is according to priority values associated with the job descriptors ([0108] In a first embodiment, data center and/or branch virtual storage array interfaces prioritize storage block requests from the storage client 939 ahead of storage requests for prefetched storage blocks for communication over the WAN 930. In a further embodiment, the virtual storage array interfaces may prioritize storage requests from different client and server systems, different storage clients, and/or different applications for communication over the WAN 930; [0110] Similarly, an embodiment of the data center virtual storage array interface may prioritize storage block accesses from different branch locations, different storage clients, different client and server systems, and/or to different LUNs in the physical storage array 903; [0037] The data center virtual storage array interface 125 translates data communications from branch virtual storage array interfaces 120 into storage accesses of a physical storage array network).
As per claim 4, Yu, Shekar, and Wu teach the method of claim 1. Wu teaches wherein translating the first job descriptor comprises: generating the one or more first commands according to an interface protocol of the first VMM ([0045] The file server 210 translates these file protocol reads into one or more storage area network reads; [0089] These storage operations can be carried out in the background by the data center virtual storage array interface in addition to translating virtual storage array operations from one or more branch virtual storage array interfaces into corresponding physical storage array operations; [0090] As described above, storage clients can interact with virtual storage arrays in the same manner that they would interact with physical storage arrays. This includes issuing storage commands to the branch virtual storage interface using storage array network protocols such as iSCSI or Fibre Channel protocol. Most storage array network protocols organize data according to storage blocks, each of which has a unique storage address or location. A storage block's unique storage address may include logical unit number (using the SCSI protocol) or other representation of a logical volume.).
As per claim 7, it is a system claim of claim 1, so it is rejected for similar reasons. Additionally, Yu teaches an engine; circuitry of a job controller, configured to: receive a first job descriptor and a second job descriptor; circuitry of a first execution pipeline; circuitry of a second execution pipeline (Fig. 13; [0081] Referring to FIG. 13, memory system 200 may include a memory controller 210 and a plurality of memory devices 230_1 to 230_k. Memory controller 210 may include a memory interface unit 211, an ECC logic element 212, a host interface 213, a RAM 214 and a central processing unit 215. In various embodiments, ECC logic element 212 may comprise a logic circuit and/or a processor configured to perform logic operations in response to instructions stored in a memory, etc. Hereinafter, ECC logic element 212 is referred to as “ECC logic 212” for convenience of description. ECC logic 212 may include first to kth ECC circuits 212_1 to 212_k, and memory interface unit 211 may include first to kth memory interfaces 211_1 to 211_k. Memory interfaces 211_1 to 211_k may be connected to memory devices 230_1 to 230_k via channels CH1 to CHk, respectively. Each of ECC circuits 212_1 to 212_k may divide data received together with a write request from a host and perform parallel encoding to thereby generate sub-codewords. The generated sub-codewords may be stored in memory devices 230_1 to 230_k in a distributed manner. And then, upon receiving a read request for data from the host, each of ECC circuits 212_1 to 212_k may receive the sub-codewords from memory devices 230_1 to 230_k through memory interface unit 211. Each of ECC circuits 212_1 to 212_k may perform parallel decoding on the received sub-codewords, and then may merge data generated as a result of decoding by using RAM 214 and output the merged data to the host through host interface 213.).
As per claims 8-10, they are system claims of claims 2-4, so they are rejected for similar reasons.
As per claim 13, Yu, Shekar, and Wu teach the system of claim 7. Yu teaches wherein the first job descriptor specifies a memory operation that comprises allocation, deletion, migration, or a combination thereof, of memory data ([0034] Memory controller 10 may transmit and receive data and the like to and from the host HOST through host interface 11 and may transmit and receive data and the like to memory device 20 through memory interface 15. For example, memory controller 10 may receive from the host HOST a write request and write data to be stored in memory system 1 by writing the data to one or more memory devices 20.).
As per claim 14, Yu, Shekar, and Wu teach the system of claim 7. Wu teaches wherein the first job descriptor specifies a memory operation that comprises invalidation, clearing, or a combination thereof, of cache data ([0020] a branch storage client accesses the virtual storage array using storage block based protocols to specify reads, writes, modifications, and/or deletions of storage blocks; [0035] In an embodiment, the branch virtual storage array interfaces 120 includes virtual storage array caches 122).
As per claim 15, it is a non-transitory computer-readable medium claim of claim 1, so it is rejected for similar reasons. Additionally, Yu teaches a non-transitory computer-readable medium storing instructions that, when executed by a processor, cause the processor to perform operations ([0032] Referring to FIG. 1, memory system 1 may include a memory controller 10 and one or more memory devices 20. Memory system 1 shown in FIG. 1 may correspond to any one of various data storage media based on a non-volatile memory; [0033] Memory controller 10 may include a host interface 11, a central processing unit (or processor) 13).
As per claims 16-18, they are non-transitory computer-readable medium claims of claims 2-4, so they are rejected for similar reasons.
Claims 5, 11, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Catthoor et al. (US 6223274 B1 hereinafter Catthoor).
As per claim 5, Yu, Shekar, and Wu teach the method of claim 4. Yu teaches wherein translating the first job descriptor further comprises ([0081] Memory interfaces 211_1 to 211_k may be connected to memory devices 230_1 to 230_k via channels CH1 to CHk, respectively. Each of ECC circuits 212_1 to 212_k may divide data received together with a write request from a host and perform parallel encoding to thereby generate sub-codewords.).
Yu, Shekar, and Wu fail to teach packing the one or more first commands into packets, wherein commands that can be performed in parallel are combined into one packet.
However, Catthoor teaches packing the one or more first commands into packets, wherein commands that can be performed in parallel are combined into one packet (Col. 14 lines 49-54 For the multi-media extended instructions, which almost always rely on processing n words in parallel which are packed in a 32 or 64 bit data packet, this means that first the n-word packing has to happen row-wise and then column-wise.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Yu, Shekar, and Wu with the teachings of Catthoor to optimize data transfers (see Catthoor Col. 10 lines 20-21 Determine the most optimized data transfer and storage architecture (DTSA)).
As per claims 11 and 19, they are system and non-transitory computer-readable medium claims of claim 5, so they are rejected for the same reasons.
Claims 6, 12, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mummidi et al. (US 11868617 B2 hereinafter Mummidi).
As per claim 6, Yu, Shekar, Wu, and Catthoor teach the method of claim 5. Yu teaches wherein translating the first job descriptor further comprises ([0081] Memory interfaces 211_1 to 211_k may be connected to memory devices 230_1 to 230_k via channels CH1 to CHk, respectively. Each of ECC circuits 212_1 to 212_k may divide data received together with a write request from a host and perform parallel encoding to thereby generate sub-codewords.).
Additionally, Catthoor teaches performance of commands in the packets (Col. 14 lines 49-54 For the multi-media extended instructions, which almost always rely on processing n words in parallel which are packed in a 32 or 64 bit data packet, this means that first the n-word packing has to happen row-wise and then column-wise.).
Yu, Shekar, Wu, and Catthoor fail to teach receiving feedback from the first VMM indicating completion of the performance of commands; and sending a completion message, indicating completion of a memory operation specified by the job descriptor.
However, Mummidi teaches receiving feedback from the first VMM indicating completion of the performance of commands; and sending a completion message, indicating completion of a memory operation specified by the job descriptor (claim 1 provide, based on an acknowledgement of the physical access request from the non-volatile storage device, an indication of completion for the access request via the virtual storage interface; Col. 10 lines 54-57 The writing of entry 526 may trigger a Message Signal Interrupt (MSI) which may notify the virtual compute instance that the write request is complete.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined Yu, Shekar, Wu, and Catthoor with the teachings of Mummidi to provide an improvement to performance (see Mummidi Col. 14 lines 11-12 provide improvements to performance of resources).
As per claims 12 and 20, they are system and non-transitory computer-readable medium claims of claim 6, so they are rejected for the same reasons.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HSING CHUN LIN whose telephone number is (571)272-8522. The examiner can normally be reached Mon - Fri 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Aimee Li can be reached at (571) 272-4169. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/H.L./Examiner, Art Unit 2195
/Aimee Li/Supervisory Patent Examiner, Art Unit 2195
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