Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is in response to communication filed on 3/11/2026.
Claims 1, 2, 4-10, 12-15 and 17-22 are pending.
Claims 9 and 17 have been amended.
Response to Arguments
Applicant's argument(s) filed on 3/11/2026 with respect to claim(s) 1, 2, 4-10, 12-15 and 17-22 have been fully considered but they are not persuasive.
In the communication field, applicant argues in substance that:
a. Regarding claim(s) 1, 9 and 17, Applicant argues (Remark page(s) 6-10)
“Here, Ramey, teaches that the programmable classification processor uses software defined rules and forwards to the tile processor those packets that should be handled by the tile processors as defined by the software defined rules, while the tile processor at most can direct the programmable classification processor to implement new policies or rules. Thus, Ramey teaches defining and implementing rules in software; Ramey does not teach or suggest programming new rules by programming programmable logic blocks and reprogrammable interconnects as required in independent claim 1; and Ramey does not teach "wherein the programmable hardware device comprises an array of programmable logic blocks and reprogrammable interconnects programmable to interconnect the programmable logic blocks to program the new rule in the programmable hardware device", as recited in independent claim 1.
None of Yang, Krivitski, Ramey, Hughes, Huang and Chan, alone or in combination, teaches or suggests at least "a programmable hardware device to and a microcontroller to program a new rule in the programmable hardware device wherein the programmable hardware device comprises an array of programmable logic blocks and reprogrammable interconnects programmable to interconnect the programmable logic blocks to program the new rule in the programmable hardware device", as recited in independent claim 1. Arguments presented above with respect to independent claim 1 are applicable to amended independent claims 9 and 17 as well.”
In response to argument [a], Examiners respectfully disagrees.
Ramey teaches col.1 lines, 12-50; col.7, lines 2-8; the system described in this section (with reference to FIGS. 1A and 1B) provides an overview of various aspects of a parallel processing environment that can be used for a variety of the techniques described in other sections. The parallel processing environment can be implemented by FPGAs (Field Programmable Gate Arrays) and ASICs (Application Specific Integrated Circuits). Col.2, lines 55-67; col.3, lines, 1-20; The programmable classification processor provides a dynamically programmable data plane in the multicore processor network interface. The programmable classification processor disposed at the front end of the network interface enables use of software defined rules for packet delivery and switching. The programmable classification processor provides a programmable front end directs packets out of any port on the processor without any intervention from the tile processors. However, when the programmable classifier processor based on the rules determines that a packet should be handled by a tile processor rather than the programmable classification processor, the programmable classification processor forwards the packet to a processing queue of the tile processor. Thus, the tile processors can implement exception handling and slow path operations, while allowing the programmable classification processor to direct all fast-path operations. Fast-path operations on packets are directed by the programmable classification processor out of any port with minimal latency and processing overhead. As conditions change (new flows, new processing rules, new applications, network topology changes), the tile processors can dynamically direct the programmable classification processor to implement new policies for forwarding and local processing (“rules”). Updates to rules can happen in real time while traffic is arriving at full line rates and thus no packets would generally be lost during updates. The tile processors can be used to handle higher level application and control plane workloads without the burden of data-plane operations/tasks [examiner notes: in advanced software-defined architectures—particularly those using FPGAs (Field-Programmable Gate Arrays)—a new software rule or instruction can reprogram the interconnections between programmable logic blocks.].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20140280857 A1) in view of Ramey (US 10037299 B1).
With respect to independent claims:
Regarding claim(s) 17, a computing device comprising:
Yang teaches a programmable hardware device; (Yang, [0054], after the host system updates the network adapter policy table and the host policy table, a CPU of the host system may be used to perform corresponding processing (such as TCP checksum calculation and GRO processing) for the uplink packet.)
and a microcontroller to, (Yang, [0054], after the host system updates the network adapter policy table and the host policy table, a CPU of the host system may be used to perform corresponding processing (such as TCP checksum calculation and GRO processing) for the uplink packet.) based on a policy and parameters of a first, unknown, packet received by the programmable hardware device, program a new rule, not included in a set of rules programmed in the programmable hardware device, the new rule indicating how to process a second packet received by the programmable hardware device and having same parameters as the first, previously unknown, packet; (Yang, [0058], FIG.5; 502. The host system searches the host policy table according to the protocol keyword, where the host policy table includes the policy entry, and the policy entry includes the policy type; if the protocol keyword matches a policy type of an existing policy entry in the host policy table, the data packet is a data packet known to the network adapter, and 503 is performed; otherwise, the data packet is a data packet unknown to the network adapter, and 504 is performed. [0061] 504. The host system parses the packet, generates a new policy entry, and updates the policy entry into the host policy table and the network adapter policy table. [examiner notes: Fig.5 shows if a second/new packet is received by the host system, if the second packet match the new policy type, processing the packet by the new policy.])
Yang does not teach wherein the programmable hardware device comprises an array of programmable logic blocks and reprogrammable interconnects programmable to interconnect the programmable logic blocks to program the new rule in the programmable hardware device.
Yang does not teach wherein the programmable hardware device comprises an array of programmable logic blocks and reprogrammable interconnects programmable to interconnect the programmable logic blocks to program the new rule in the programmable hardware device.
Ramey however in the same field of computer networking teaches wherein the programmable hardware device comprises an array of programmable logic blocks and reprogrammable interconnects programmable to interconnect the programmable logic blocks to program the new rule in the programmable hardware device. (Ramey, col.1 lines, 12-50; col.7, lines 2-8; the system described in this section (with reference to FIGS. 1A and 1B) provides an overview of various aspects of a parallel processing environment that can be used for a variety of the techniques described in other sections. The parallel processing environment can be implemented by FPGAs (Field Programmable Gate Arrays) and ASICs (Application Specific Integrated Circuits). Col.2, lines 55-67; col.3, lines, 1-20; The programmable classification processor provides a dynamically programmable data plane in the multicore processor network interface. The programmable classification processor disposed at the front end of the network interface enables use of software defined rules for packet delivery and switching. The programmable classification processor provides a programmable front end directs packets out of any port on the processor without any intervention from the tile processors. However, when the programmable classifier processor based on the rules determines that a packet should be handled by a tile processor rather than the programmable classification processor, the programmable classification processor forwards the packet to a processing queue of the tile processor. Thus, the tile processors can implement exception handling and slow path operations, while allowing the programmable classification processor to direct all fast-path operations. Fast-path operations on packets are directed by the programmable classification processor out of any port with minimal latency and processing overhead. As conditions change (new flows, new processing rules, new applications, network topology changes), the tile processors can dynamically direct the programmable classification processor to implement new policies for forwarding and local processing (“rules”). Updates to rules can happen in real time while traffic is arriving at full line rates and thus no packets would generally be lost during updates. The tile processors can be used to handle higher level application and control plane workloads without the burden of data-plane operations/tasks [examiner notes: in advanced software-defined architectures—particularly those using FPGAs (Field-Programmable Gate Arrays)—a new software rule or instruction can reprogram the interconnections between programmable logic blocks.].)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to modify Yang by incorporating the teachings of Ramey. The motivation/suggestion would have been because there is a need to avoid stalling in many instances and obtain some of the performance improvements of out-of-order execution or speculative execution with little hardware cost (Ramey, col.2, lines 20-25).
2. Claims 1, 2, 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 20140280857 A1)
With respect to independent claims:
Regarding claim(s) 1, a computing device comprising:
Yang teaches a programmable hardware device to: (Yang, [0054], after the host system updates the network adapter policy table and the host policy table, a CPU of the host system may be used to perform corresponding processing (such as TCP checksum calculation and GRO processing) for the uplink packet.)
and if it is determined that the first packet does not meet any rule in the programmed set of rules, determine that the first packet is unknown; and (Yang, [0058], FIG.5; 502. The host system searches the host policy table according to the protocol keyword, where the host policy table includes the policy entry, and the policy entry includes the policy type; if the protocol keyword matches a policy type of an existing policy entry in the host policy table, the data packet is a data packet known to the network adapter, and 503 is performed; otherwise, the data packet is a data packet unknown to the network adapter, and 504 is performed. [0061] 504. The host system parses the packet, generates a new policy entry, and updates the policy entry into the host policy table and the network adapter policy table. [examiner notes: the data packet equivalent to the first packet.])
a microcontroller to, (Yang, [0054], after the host system updates the network adapter policy table and the host policy table, a CPU of the host system may be used to perform corresponding processing (such as TCP checksum calculation and GRO processing) for the uplink packet.) based on a policy and the parameters of the first packet, program a new rule, not included in the programmed set of rules, in the programmable hardware device, the new rule indicating how to process a second packet received by the programmable hardware device and having same parameters as the first, previously unknown, packet. (Yang, [0058], FIG.5; 502. The host system searches the host policy table according to the protocol keyword, where the host policy table includes the policy entry, and the policy entry includes the policy type; if the protocol keyword matches a policy type of an existing policy entry in the host policy table, the data packet is a data packet known to the network adapter, and 503 is performed; otherwise, the data packet is a data packet unknown to the network adapter, and 504 is performed. [0061] 504. The host system parses the packet, generates a new policy entry, and updates the policy entry into the host policy table and the network adapter policy table. [examiner notes: Fig.5 shows if a second/new packet is received by the host system, if the second packet match the new policy type, processing the packet by the new policy.])
Yang does not teach based on parameters of a first packet, determine whether or not the first packet meets a rule in a set of rules programmed in the programmable hardware device, wherein the programmable hardware device comprises an array of programmable logic blocks and reprogrammable interconnects programmable to interconnect the programmable logic blocks to program the new rule in the programmable hardware device.
Krivitski however in the same field of computer networking teaches based on parameters of a first packet, determine whether or not the first packet meets a rule in a set of rules, (Krivitski, col.2, lines 10-25; the apparatus can include a key constructor configured to construct a search key based on parameters of a packet and indications of ranges among a group of ranges within which a parameter of the packet belongs, a rule tester coupled to the key constructor, the rule tester being configured to determine a rule that the search key satisfies the rule, and a packet handler coupled to the rule tester, the packet handler being configured to execute an action associated with the rule on the packet. col.8, lines 50-60; FIG.6; The range comparator unit 630 can compare a packet with a group of ranges to determine a relationship of the packet to the group of ranges, such as whether a parameter of the packet, for example a port number, is within one of the ranges. The encoder 640 can encode the relationship along with other parameters, such as transport protocol, source port, destination port, and the like, into a search key.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to modify Yang by incorporating the teachings of Krivitski. The motivation/suggestion would have been because there is a need to reduce hardware cost (Krivitski, col.1, lines 40-45).
Yang does not teach wherein the programmable hardware device comprises an array of programmable logic blocks and reprogrammable interconnects programmable to interconnect the
programmable logic blocks to program the new rule in the programmable hardware device.
Ramey however in the same field of computer networking teaches wherein the programmable hardware device comprises an array of programmable logic blocks and reprogrammable interconnects programmable to interconnect the programmable logic blocks to program the new rule in the programmable hardware device. (Ramey, col.1 lines, 12-50; col.7, lines 2-8; the system described in this section (with reference to FIGS. 1A and 1B) provides an overview of various aspects of a parallel processing environment that can be used for a variety of the techniques described in other sections. The parallel processing environment can be implemented by FPGAs (Field Programmable Gate Arrays) and ASICs (Application Specific Integrated Circuits). Col.2, lines 55-67; col.3, lines, 1-20; The programmable classification processor provides a dynamically programmable data plane in the multicore processor network interface. The programmable classification processor disposed at the front end of the network interface enables use of software defined rules for packet delivery and switching. The programmable classification processor provides a programmable front end directs packets out of any port on the processor without any intervention from the tile processors. However, when the programmable classifier processor based on the rules determines that a packet should be handled by a tile processor rather than the programmable classification processor, the programmable classification processor forwards the packet to a processing queue of the tile processor. Thus, the tile processors can implement exception handling and slow path operations, while allowing the programmable classification processor to direct all fast-path operations. Fast-path operations on packets are directed by the programmable classification processor out of any port with minimal latency and processing overhead. As conditions change (new flows, new processing rules, new applications, network topology changes), the tile processors can dynamically direct the programmable classification processor to implement new policies for forwarding and local processing (“rules”). Updates to rules can happen in real time while traffic is arriving at full line rates and thus no packets would generally be lost during updates. The tile processors can be used to handle higher level application and control plane workloads without the burden of data-plane operations/tasks [examiner notes: in advanced software-defined architectures—particularly those using FPGAs (Field-Programmable Gate Arrays)—a new software rule or instruction can reprogram the interconnections between programmable logic blocks.].)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to modify Yang by incorporating the teachings of Ramey. The motivation/suggestion would have been because there is a need to avoid stalling in many instances and obtain some of the performance improvements of out-of-order execution or speculative execution with little hardware cost (Ramey, col.2, lines 20-25).
Regarding claim(s) 9, a method comprising,
Yang teaches using a computing device operating a programable hardware device and a microcontroller: by the programable hardware device: (Yang, [0054], after the host system updates the network adapter policy table and the host policy table, a CPU of the host system may be used to perform corresponding processing (such as TCP checksum calculation and GRO processing) for the uplink packet.)
and if it is determined that the first packet does not meet any rule in the programmed set of rules, determining that the first packet is unknown; and by the microcontroller, based on a policy and the parameters of the first packet, programming a new rule, not included in the programmed set of rules, in the programmable hardware device, the new rule indicating how to process a second packet received by the programmable hardware device and having same parameters as the first, previously unknown, packet; (Yang, [0058], FIG.5; 502. The host system searches the host policy table according to the protocol keyword, where the host policy table includes the policy entry, and the policy entry includes the policy type; if the protocol keyword matches a policy type of an existing policy entry in the host policy table, the data packet is a data packet known to the network adapter, and 503 is performed; otherwise, the data packet is a data packet unknown to the network adapter, and 504 is performed. [0061] 504. The host system parses the packet, generates a new policy entry, and updates the policy entry into the host policy table and the network adapter policy table. [examiner notes: Fig.5 shows if a second/new packet is received by the host system, if the second packet match the new policy type, processing the packet by the new policy.])
Yang does not teach based on parameters of a first packet, determining whether or not
the first packet meets a rule in a set of rules programmed in the programmable hardware device, wherein the programmable hardware device comprises an array of programmable logic blocks and reprogrammable interconnects programmable to interconnect the programmable logic blocks to program the new rule in the programmable hardware device.
Krivitski however in the same field of computer networking teaches based on parameters of a first packet, determining whether or not the first packet meets a rule in a set of rules programmed in the programmable hardware device, (Krivitski, col.2, lines 10-25; the apparatus can include a key constructor configured to construct a search key based on parameters of a packet and indications of ranges among a group of ranges within which a parameter of the packet belongs, a rule tester coupled to the key constructor, the rule tester being configured to determine a rule that the search key satisfies the rule, and a packet handler coupled to the rule tester, the packet handler being configured to execute an action associated with the rule on the packet. col.8, lines 50-60; FIG.6; The range comparator unit 630 can compare a packet with a group of ranges to determine a relationship of the packet to the group of ranges, such as whether a parameter of the packet, for example a port number, is within one of the ranges. The encoder 640 can encode the relationship along with other parameters, such as transport protocol, source port, destination port, and the like, into a search key.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to modify Yang by incorporating the teachings of Krivitski. The motivation/suggestion would have been because there is a need to reduce hardware cost (Krivitski, col.1, lines 40-45).
Yang does not teach wherein the programmable hardware device comprises an array of programmable logic blocks and reprogrammable interconnects programmable to interconnect the programmable logic blocks to program the new rule in the programmable hardware device
Ramey however in the same field of computer networking teaches wherein the programmable hardware device comprises an array of programmable logic blocks and reprogrammable interconnects programmable to interconnect the programmable logic blocks to program the new rule in the programmable hardware device (Ramey, col.1 lines, 12-50; col.7, lines 2-8; the system described in this section (with reference to FIGS. 1A and 1B) provides an overview of various aspects of a parallel processing environment that can be used for a variety of the techniques described in other sections. The parallel processing environment can be implemented by FPGAs (Field Programmable Gate Arrays) and ASICs (Application Specific Integrated Circuits). Col.2, lines 55-67; col.3, lines, 1-20; The programmable classification processor provides a dynamically programmable data plane in the multicore processor network interface. The programmable classification processor disposed at the front end of the network interface enables use of software defined rules for packet delivery and switching. The programmable classification processor provides a programmable front end directs packets out of any port on the processor without any intervention from the tile processors. However, when the programmable classifier processor based on the rules determines that a packet should be handled by a tile processor rather than the programmable classification processor, the programmable classification processor forwards the packet to a processing queue of the tile processor. Thus, the tile processors can implement exception handling and slow path operations, while allowing the programmable classification processor to direct all fast-path operations. Fast-path operations on packets are directed by the programmable classification processor out of any port with minimal latency and processing overhead. As conditions change (new flows, new processing rules, new applications, network topology changes), the tile processors can dynamically direct the programmable classification processor to implement new policies for forwarding and local processing (“rules”). Updates to rules can happen in real time while traffic is arriving at full line rates and thus no packets would generally be lost during updates. The tile processors can be used to handle higher level application and control plane workloads without the burden of data-plane operations/tasks [examiner notes: in advanced software-defined architectures—particularly those using FPGAs (Field-Programmable Gate Arrays)—a new software rule or instruction can reprogram the interconnections between programmable logic blocks.].)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to modify Yang by incorporating the teachings of Ramey. The motivation/suggestion would have been because there is a need to avoid stalling in many instances and obtain some of the performance improvements of out-of-order execution or speculative execution with little hardware cost (Ramey, col.2, lines 20-25).
With respect to dependent claims:
Regarding claim(s) 2, the computing device of claim 1,
Yang-Krivitski-Ramey teach wherein the programmable hardware device is to: if it is determined that the first packet meets the rule in the programmed set of rules, process the first packet as indicated by the rule. (Yang, [0058], FIG.5; 502. The host system searches the host policy table according to the protocol keyword, where the host policy table includes the policy entry, and the policy entry includes the policy type; if the protocol keyword matches a policy type of an existing policy entry in the host policy table, the data packet is a data packet known to the network adapter, and 503 is performed;)
Claim(s) 10 is/are substantially similar to claim 2, and is thus rejected under substantially the same rationale.
3. Claim(s) 19, 20 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Ramey further in view of Hughes (US 20210352109 A1).
Regarding claim(s) 19, the computing device of claim 17,
Yang-Ramey do not teach wherein processing the first packet comprises at least one of modifying the first packet, monitoring the first packet and transmitting the first packet to a port.
Hughes however in the same field of computer networking teaches wherein processing the first packet comprises at least one of modifying the first packet, monitoring the first packet and transmitting the first packet to a port. (Hughes, [0040], Fig.4; in a step 415, the outgoing packet is associated with the policy configuration 390 related to the network appliance 250 that received the packet. The association includes the classification of the packet by the port on which the packet was received and a determination of the application from which the packet originated. A person skilled in the art of network programing and design would know how to inspect and classify the packets. This information is matched up against the policy configuration 390 parameters for the port and application.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to modify Yang by incorporating the teachings of Hughes. The motivation/suggestion would have been because there is a need to managing access control for hundreds or thousands of segments, tunnels between segments, and security for these segments can be complex and prone to human error (Hughes, [0004]).
Regarding claim(s) 20, the computing device of claim 17,
Yang-Ramey-Hughes teach wherein processing the first packet comprises modifying network address information in an Internet Protocol (IP) header of the first packet as part of a network address translation (NAT) operation. (Hughes, [0057], Fig.5; in an optional step 535, if indicated by the second policy header, the destination address is translated. Multiple branch offices may be using the same IP address and thus would, if used, cause a conflict. Translating the IP address can be done using standard NAT protocols including but not limited to D-NAT and S-NAT. [examiner notes: Network address translation (NAT) is a method of mapping an IP address space into another by modifying network address information in the IP header of packets while they are in transit across a traffic routing device.])
The same motivation to combine as the dependent claim 19 applies here.
Regarding claim(s) 22, the computing device of claim 17,
Yang-Ramey-Hughes teach wherein processing the first packet comprises dropping the first packet. (Hughes, [0055], there can also be a security validation where the firewall zones of the port and destination network addresses are verified. If the packet does not meet the policy configuration for the networking segments, the applications allowed, and security, then the packet can be dropped.)
The same motivation to combine as the dependent claim 19 applies here.
4. Claim(s) 4, 5, 7, 8, 12, 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Krivitski in view of Ramey further in view of Hughes (US 20210352109 A1).
Regarding claim(s) 4, Yang teaches the computing device of claim 1,
Yang-Krivitski-Ramey do not teach wherein processing the first packet comprises at least one of modifying the first packet, monitoring the first packet and transmitting the first packet to a port.
Hughes however in the same field of computer networking teaches wherein processing the first packet comprises at least one of modifying the first packet, monitoring the first packet and transmitting the first packet to a port. (Hughes, [0040], Fig.4; in a step 415, the outgoing packet is associated with the policy configuration 390 related to the network appliance 250 that received the packet. The association includes the classification of the packet by the port on which the packet was received and a determination of the application from which the packet originated. A person skilled in the art of network programing and design would know how to inspect and classify the packets. This information is matched up against the policy configuration 390 parameters for the port and application.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to modify Yang by incorporating the teachings of Hughes. The motivation/suggestion would have been because there is a need to managing access control for hundreds or thousands of segments, tunnels between segments, and security for these segments can be complex and prone to human error (Hughes, [0004]).
Regarding claim(s) 5, the computing device of claim 1,
Yang-Krivitski-Ramey-Hughes teach wherein processing the first packet comprises modifying network address information in an Internet Protocol (IP) header of the first packet as part of a network address translation (NAT) operation. (Hughes, [0057], Fig.5; in an optional step 535, if indicated by the second policy header, the destination address is translated. Multiple branch offices may be using the same IP address and thus would, if used, cause a conflict. Translating the IP address can be done using standard NAT protocols including but not limited to D-NAT and S-NAT. [examiner notes: Network address translation (NAT) is a method of mapping an IP address space into another by modifying network address information in the IP header of packets while they are in transit across a traffic routing device.])
The same motivation to combine as the dependent claim 4 applies here.
Regarding claim(s) 7, the computing device of claim 1,
Yang- Ramey-Krivitski-Hughes teach wherein processing the first packet comprises dropping the first packet. (Hughes, [0055], there can also be a security validation where the firewall zones of the port and destination network addresses are verified. If the packet does not meet the policy configuration for the networking segments, the applications allowed, and security, then the packet can be dropped.)
The same motivation to combine as the dependent claim 4 applies here.
Regarding claim(s) 8, the computing device of claim 1,
Yang-Krivitski-Ramey-Hughes teach wherein the computing device is one of a network interface controller (NIC), a graphical processing unit (GPU), Field Programmable Gate Array (FPGA) or reduced instruction set computer (RISC). (Hughes, Fig. 3A shows a network appliance comprising, a wide area network interface, a local area network interface, a processor, and memory; and an SD-WAN.)
The same motivation to combine as the dependent claim 4 applies here.
Claim(s) 12 is/are substantially similar to claim 4, and is thus rejected under substantially the same rationale.
Claim(s) 13 is/are substantially similar to claim 5, and is thus rejected under substantially the same rationale.
Claim(s) 15 is/are substantially similar to claim 7, and is thus rejected under substantially the same rationale.
5. Claim(s) 21 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Ramey further in view of Huang (US 20230336472 A1).
Regarding claim(s) 21, the computing device of claim 17,
Yang- Ramey does not teach wherein the microcontroller is to: if a connection defined by the first packet is inactive for more than a specified time duration, program the programmable hardware device to delete a rule related to the first packet. (Huang, [0025], the connection table is present in a memory of the software NAT. In some embodiments, the software NAT may be an application microcontroller, but the present invention is not limited thereto. If the time period that the software NAT does not receive any data packet relative to the routing rule is longer than the timeout, the software NAT may remove the routing rule.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to modify Yang by incorporating the teachings of Huang. The motivation/suggestion would have been because there is a need to saving power, and in particular it is related to a method and an electronic device for saving power applied to a router (Huang, [0001]).
6. Claim(s) 6 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Krivitski in view of Ramey further in view of Huang (US 20230336472 A1).
Regarding claim(s) 6, the computing device of claim 1,
Yang- Ramey-Krivitski does not teach wherein the microcontroller is to: if a connection defined by the first packet is inactive for more than a specified time duration, program the programmable hardware device to delete the new rule related to the first packet.
Huang however in the same field of computer networking teaches wherein the microcontroller is to: if a connection defined by the first packet is inactive for more than a specified time duration, program the programmable hardware device to delete the new rule related to the first packet.
(Huang, [0025], the connection table is present in a memory of the software NAT. In some embodiments, the software NAT may be an application microcontroller, but the present invention is not limited thereto. If the time period that the software NAT does not receive any data packet relative to the routing rule is longer than the timeout, the software NAT may remove the routing rule.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to modify Yang by incorporating the teachings of Huang. The motivation/suggestion would have been because there is a need to saving power, and in particular it is related to a method and an electronic device for saving power applied to a router (Huang, [0001]).
Claim(s) 14 is/are substantially similar to claim 6, and is thus rejected under substantially the same rationale.
7. Claim(s) 18 is rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Ramey further in view of Chan (US 20150016464 A1).
Regarding claim(s) 18, the computing device of claim 17,
Yang-Ramey teach wherein the programmable hardware device is to: based on the parameters of the first packet, determine whether or not the packet meets a rule in the set of rules programmed in the programmable hardware device; and (Krivitski, col.2, lines 10-25; the apparatus can include a key constructor configured to construct a search key based on parameters of a packet and indications of ranges among a group of ranges within which a parameter of the packet belongs, a rule tester coupled to the key constructor, the rule tester being configured to determine a rule that the search key satisfies the rule, and a packet handler coupled to the rule tester, the packet handler being configured to execute an action associated with the rule on the packet. col.8, lines 50-60; FIG.6; The range comparator unit 630 can compare a packet with a group of ranges to determine a relationship of the packet to the group of ranges, such as whether a parameter of the packet, for example a port number, is within one of the ranges. The encoder 640 can encode the relationship along with other parameters, such as transport protocol, source port, destination port, and the like, into a search key.)
Yang-Ramey do not teach if it is determined that the packet does not meet any rule in the set of rules, transmit the packet to the microcontroller.
Chan however in the same field of computer networking teaches if it is determined that the first packet does not meet any rule in the set of rules, transmit the first packet to the microcontroller. (Chan, [0065], If the IP data packet does not satisfy the interception policy, digital processor(s) 804 forwards the IP data packet via network interface 812 according to the destination address of the IP data packet.)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective date of the claimed invention to modify Yang by incorporating the teachings of Chan. The motivation/suggestion would have been because there is a need for a network gateway to communicate with other nodes in an IP network in which the network gateway is not assigned with an IP address (Chan, [0010]).
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WUJI CHEN whose telephone number is (571)270-0365. The examiner can normally be reached on 9am-6pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, VIVEK SRIVASTAVA can be reached on (571) 272-7304. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WUJI CHEN/
Examiner, Art Unit 2449
/VIVEK SRIVASTAVA/Supervisory Patent Examiner, Art Unit 2449
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