DETAILED ACTION
This action is responsive to the communication filed 15 June 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of the Group I invention is acknowledged.
Accordingly, claims 16-20, drawn to a nonelected invention, are withdrawn from further consideration.
Drawings
The objections to the drawings are withdrawn, responsive to Applicant’s amendment of the claims.
Claim Rejections - 35 USC § 112
The rejections of the claims under § 112(b) are withdrawn, responsive to Applicant’s amendment of the claims.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 8 is rejected under 35 U.S.C. § 102(a)(1) as being anticipated by U.S. Patent Publication No. 2020/0135645 (published Apr. 30, 2020) (hereinafter “Rubin”).
Regarding independent claim 8, Rubin discloses: A semiconductor structure (FIG. 1, depicting a semiconductor device 10, [0036]) comprising:
a device layer (FIG. 1, e.g., device tier T1, [0036]) disposed between an interlayer dielectric (ILD) (FIG. 1, e.g., insulating material 104, [0036], [0041]) and a back-end-of-line (BEOL) comprising BEOL components (FIG. 1, depicting components of the BEOL layer, e.g., metallic structure M3, [0041]);
a power distribution network (PDN) (FIG. 1, power distribution plane 102, [0036]) within the ILD (FIG. 1, depicting wherein the power distribution plane 102 is within the insulating layer 104); and
backside transistors (FIG. 1, device tier T2 including FinFET transistors, [0039]) disposed over the ILD (FIG. 1, depicting wherein the device tier t2 is disposed over the insulating layer 104).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 14 and 15 are rejected under 35 U.S.C. § 103 as being unpatentable over Rubin.
Regarding claim 14, Rubin does not specifically disclose in the FIG. 1 embodiment wherein bonding dielectric layers are disposed directly between the device layer and the PDN.
In FIGS. 6-9, however, Rubin discloses wherein various layers may be bonded by dielectric layers (FIGS. 6-9, depicting wherein various structures of the device such as device tier T1 and backside layer BSL are bonded using dielectric bonding layers 206/208, [0059], and device tiers T1/T2 are bonded using dielectric bonding layer 232). Regarding the bonding, in [0059], Rubin states: “To begin, FIG. 6 is a schematic cross-sectional side view of the semiconductor device 20 at an intermediate stage of fabrication in which a wafer bonding process is performed to bond a semiconductor-on-insulator (SOI) substrate to a backside layer BSL comprising a backside power distribution plane.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed semiconductor device of FIG. 10 of Rubin by adding the bonding layers of FIGS. 6-9 of Rubin in order to bond the power distribution plane 102 with the device tier T1. See Rubin [0059].
Moreover, addition of the bonding dielectric layers of FIGS. 6-9 of Rubin would result in a configuration wherein the bonding dielectric layers are disposed directly between the device layer (FIG. 1, device tier T1) and the PDN (FIG. 1, power distribution plane 102).
Regarding claim 15, Rubin FIG. 1, as modified by Rubin FIGS. 6-9 further discloses wherein via-to- backside power rail (VBPR) contacts (FIG. 1, e.g., contacts C1/C2, contacts 124, contacts 116, contacts 114, [0036]-[0041]) of the device layer extend through the bonding dielectric layers to the PDN (FIG. 1, depicting wherein the contacts C1/C2, contacts 124, contacts 116, contacts 114 would extend through bonding dielectric layers disposed at the interface between the device tier T1 and the backside layer BSL layer to the power distribution plane 102).
Claims 1-7 and 9-13 are rejected under 35 U.S.C. § 103 as being unpatentable over Rubin in view of U.S. Patent Publication No. 2023/0005863 (filed Sept. 22, 2021) (hereinafter “Yang”).
Regarding independent claim 1, Rubin discloses: A semiconductor structure (FIG. 10, depicting a semiconductor device 30, [0069]) comprising:
a device layer (FIG. 10, e.g., second device tier T2, [0036]) including a plurality of active devices (FIG. 10, depicting a plurality of FinFET devices, [0036]);
a back-end-of-line (BEOL) comprising BEOL components (FIG. 10, depicting BEOL layer comprising various components, e.g., metallic structure M1, [0041], [0074]) disposed under the device layer (FIG. 10, depicting wherein the BEOL layer is disposed under the second device tier T2);
a power distribution network (PDN) (FIG. 10, depicting power distribution plane 320, [0069]) within an interlayer dielectric (ILD) disposed over the device layer (FIG. 1, depicting wherein the power distribution plane 320 is within the insulating material 322, and the insulating material 322 is disposed over the second device tier T2, [0071], [0074]); and
backside transistors disposed on a single crystal silicon (Si) layer disposed over the ILD.
While Rubin states in [0042] that “the device tiers T1 and T2 can additionally or alternately include other types of FET devices such as planar FET devices,” Rubin does not specifically disclose backside transistors disposed on a single crystal silicon (Si) layer disposed over the PDN.
In the same field of endeavor, Yang discloses a semiconductor structure (FIG. 29A, 3D memory device 2900, [0294]) including backside transistors (FIG. 29A, e.g., transistors 2908/2910, [0295]) disposed on a single crystal silicon (Si) layer (FIG. 29A, semiconductor layer 1004, which may be formed from single crystalline silicon, [0295]) disposed over a PDN (FIG. 29A, e.g., interconnect layer 2926, [0302]). Regarding the configuration of the transistors, in [0115], Yang states: “It is understood that in some examples, different from polysilicon layer 106 in first semiconductor structure 102, semiconductor layer 1004 on which the transistors are formed may include single crystalline silicon, but not polysilicon, due to the superior carrier mobility of single crystalline silicon that is desirable for transistors' performance.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Rubin by substituting the transistor configuration of Yang in order to improve the performance of the transistors. See Yang [0115].
Moreover, the substitution of the transistor configuration of Yang would result in a configuration wherein the transistors are disposed over the power distribution plane 320.
Regarding claim 2, Rubin in view of Yang further discloses wherein bonding dielectric layers (FIG. 10, depicting bonding layers 330/332, which may be formed from dielectric material, [0059]) are disposed directly between the device layer and the PDN (FIG. 10, depicting wherein the bonding layers 330/332 are disposed directly between the second device tier T2 and the power distribution plane 320).
Regarding claim 3, Rubin in view of Yang further discloses wherein a through silicon via (TSV) (FIG. 10, e.g., contact 314, contact C1, contact pad 328, contact 344, contact C4, and metallic structures M0 forming a through silicon via, [0036]-[0041]) extends from a TSV area disposed on the single crystal Si layer through the BEOL (FIG. 10, depicting wherein the through silicon via extends from a first area disposed on the layer in which the transistor configuration of Yang is formed through the BEOL layer).
Regarding claim 4, Rubin in view of Yang further discloses wherein an upper through silicon via (uTSV) (FIG. 10, e.g., contact 314, contact C1, contact pad 328 forming an upper through silicon via, [0036]-[0041]) extends from the PDN through a through silicon via (TSV) area disposed on the single crystal Si layer (FIG. 10, depicting wherein the upper through silicon via extends from the power distribution plane 320 a first area disposed on the layer in which the transistor configuration of Yang is formed through the BEOL layer).
Regarding claim 5, Rubin in view of Yang further discloses wherein via-to- via-to- backside power rail (VBPR) contacts (FIG. 10, contacts 344, [0073]) of the device layer (FIG. 10, e.g., second device tier T2) extend through bonding dielectric layers to the PDN (FIG. 10, depicting wherein the contacts 344 extend through bonding layers 330/332 to the power distribution plane 320).
Regarding claim 6, Rubin in view of Yang further discloses wherein source contacts and drain contacts (FIG. 29A, depicting wherein the transistors 2908/2910 include source and drain contacts, [0295]) are disposed over the backside transistors disposed on the single crystal Si layer (FIG. 29A, depicting wherein the source and drain contacts are disposed over the transistors 2908/2910 on the substrate 1004).
Regarding claim 7, Rubin in view of Yang further discloses wherein an etch stop layer (FIG. 10, e.g., insulating layer 318 formed from silicon oxide, which is an etch stop material, [0061], [0070]) is disposed directly between the PDN and the backside transistors disposed on the single crystal Si layer (FIG. 10, depicting wherein the insulating layer 318 is disposed directly between the power distribution plane 320 and the layer in which the transistor configuration of Yang is formed).
Regarding claim 9, while Rubin states in [0042] that “the device tiers T1 and T2 can additionally or alternately include other types of FET devices such as planar FET devices,” Rubin does not specifically disclose wherein the backside transistors are disposed on a single crystal silicon (Si) layer.
In the same field of endeavor, Yang discloses a semiconductor structure (FIG. 29A, 3D memory device 2900, [0294]) including backside transistors (FIG. 29A, e.g., transistors 2908/2910, [0295]) disposed on a single crystal silicon (Si) layer (FIG. 29A, semiconductor layer 1004, which may be formed from single crystalline silicon, [0295]). Regarding the configuration of the transistors, in [0115], Yang states: “It is understood that in some examples, different from polysilicon layer 106 in first semiconductor structure 102, semiconductor layer 1004 on which the transistors are formed may include single crystalline silicon, but not polysilicon, due to the superior carrier mobility of single crystalline silicon that is desirable for transistors' performance.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Rubin by substituting the transistor configuration of Yang in order to improve the performance of the transistors. See Yang [0115].
Regarding claim 10, Rubin in view of Yang further discloses wherein a through silicon via (TSV) (FIG. 1, e.g., contact 114, contact C3, contact 124, contact C8, metallic structure M0, via V0, metallic structure M1, via V1, metallic structure M2, via V2, metallic structure M3 forming a through silicon via, [0036]-[0041]) extends from a TSV area disposed on the single crystal Si layer through the BEOL (FIG. 1, depicting wherein the through silicon via extends from a first area disposed on the layer in which the transistor configuration of Yang is formed through the BEOL layer).
Regarding claim 11, Rubin in view of Yang further discloses wherein an upper TSV (uTSV) (FIG. 1, e.g., contact 114, contact C3, contact 124, contact C8, metallic structure M0, via V0, metallic structure M1, via V1, metallic structure M2 forming an upper through silicon via) extends from the PDN through a through silicon via (TSV) area disposed on the single crystal Si layer (FIG. 1, depicting wherein the upper through silicon via extends from the power distribution plane 102 a first area disposed on the layer in which the transistor configuration of Yang is formed through the BEOL layer).
Regarding claim 12, Rubin in view of Yang further discloses wherein source contacts and drain contacts (FIG. 29A, depicting wherein the transistors 2908/2910 include source and drain contacts, [0295]) are disposed over the backside transistors disposed on the single crystal Si layer (FIG. 29A, depicting wherein the source and drain contacts are disposed over the transistors 2908/2910 on the substrate 1004).
Regarding claim 13, Rubin in view of Yang further discloses wherein an etch stop layer (FIG. 1, e.g., insulating layer 118 formed from silicon oxide, which is an etch stop material, [0037], [0061]) is disposed directly between the PDN and the backside transistors disposed on the single crystal Si layer (FIG. 1, depicting wherein the insulating layer 118 is disposed directly between the power distribution plane 102 and the layer in which the transistor configuration of Yang is formed).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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