DETAILED ACTION
This action is responsive to U.S. Patent Application No. 17/954,514 filed on 28 September 2022.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of Applicant' s Information Disclosure Statement(s) (IDS). The IDS(es) has/have been considered.
Election/Restrictions
Applicant’s election without traverse of the Group I invention is acknowledged.
Accordingly, claims 16-20, drawn to a nonelected invention, are withdrawn from further consideration.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the claimed subject matter of:
Claim 4: “wherein an upper TSV (uTSV) extends from the PDN through the backside transistors”;
Claim 8: “A semiconductor structure comprising: a power distribution network (PDN) disposed between a device layer and back-end-of-line (BEOL) components; and backside transistors disposed over the PDN.”
Claim 9: “The semiconductor structure of claim 8, wherein the backside transistors are disposed on a single crystal silicon (Si) layer.”;
Claim 10: “The semiconductor structure of claim 9, wherein a through silicon via (TSV) extends from the backside transistors disposed on the single crystal Si layer through the BEOL.”;
Claim 11: “The semiconductor structure of claim 9, wherein an upper TSV (uTSV) extends from the PDN through the backside transistors disposed on the single crystal Si layer.”;
Claim 12: “The semiconductor structure of claim 9, wherein source/drain (S/D) contacts are disposed over the backside transistors disposed on the single crystal Si layer.”;
Claim 13: “The semiconductor structure of claim 9, wherein an etch stop layer is disposed directly between the PDN and the backside transistors disposed on the single crystal Si layer.”;
Claim 14: “The semiconductor structure of claim 8, wherein bonding dielectric layers are disposed directly between the device layer and the PDN.”;
Claim 15: “The semiconductor structure of claim 14, wherein via-to-BPRs (VBPRs) of the device layer extend through the bonding dielectric layers to the PDN.”;
must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 5, 6, 10, 12, and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
“The essential inquiry pertaining to this requirement is whether the claims set out and circumscribe a particular subject matter with a reasonable degree of clarity and particularity. ‘As the statutory language of “particular[ity]” and “distinct[ness]” indicates, claims are required to be cast in clear—as opposed to ambiguous, vague, indefinite—terms. It is the claims that notify the public of what is within the protections of the patent, and what is not.’” MPEP § 2173.02(II) (quoting In re Packard, 751 F.3d 1307, 1313 (Fed. Cir. 2014)).
Regarding claim 3: claim 3 recites the limitation "the BEOL.” There is insufficient antecedent basis for this limitation in the claim.
Regarding claim 5: claim 5 states, in relevant part, “wherein via-to-BPRs (VBPRs) of the device layer extend through bonding dielectric layers to the PDN.” It is unclear whether the recited limitations encompass (1) a physical structure, e.g., a VBPR contact, of the device layer or (2) some spatial configuration of the device layer with respect to the VBPR limitations. For the purposes of examination, the relevant limitation has been interpreted in accordance with interpretation (1).
Regarding claim 6: claim 6 states, in relevant part, “wherein source/drain (S/D) contacts are disposed over the backside transistors . . . .” It is unclear whether the recited limitation encompasses (1) both source and drain contacts, (2) only source contacts, or (3) only drain contacts. For the purposes of examination, the relevant limitation has been interpreted in accordance with interpretation (1).
Regarding claim 10: claim 10 recites the limitation "the BEOL.” There is insufficient antecedent basis for this limitation in the claim.
Regarding claim 12: claim 12 states, in relevant part, “wherein source/drain (S/D) contacts are disposed over the backside transistors . . . .” It is unclear whether the recited limitation encompasses (1) both source and drain contacts, (2) only source contacts, or (3) only drain contacts. For the purposes of examination, the relevant limitation has been interpreted in accordance with interpretation (1).
Regarding claim 15: claim 15 states, in relevant part, “wherein via-to-BPRs (VBPRs) of the device layer extend through bonding dielectric layers to the PDN.” It is unclear whether the recited limitations encompass (1) a physical structure, e.g., a VBPR contact, of the device layer or (2) some spatial configuration of the device layer with respect to the VBPR limitations. For the purposes of examination, the relevant limitation has been interpreted in accordance with interpretation (1).
Applicant may cancel the claims, amend the claims, or present a sufficient showing that the claims comply with the statutory requirements.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 8 is rejected under 35 U.S.C. § 102(a)(1) as being anticipated by U.S. Patent Publication No. 2020/0135645 (published Apr. 30, 2020) (hereinafter “Rubin”).
Regarding independent claim 8, Rubin discloses: A semiconductor structure (FIG. 1, depicting a semiconductor device 10, [0036]) comprising:
a power distribution network (PDN) (FIG. 1, power distribution plane 132, [0045]) disposed between a device layer and back-end-of-line (BEOL) components (FIG. 1, depicting wherein the power distribution plane 132 is disposed between a second device tier T2 and components of the BEOL layer, e.g., metallic structure M3, [0041]); and
backside transistors (FIG. 1, device tier T1 including FinFET transistors, [0042]) disposed over the PDN (FIG. 1, depicting wherein the device tier T1 including FinFET transistors is disposed over the power distribution plane 132).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 14 and 15 are rejected under 35 U.S.C. § 103 as being unpatentable over Rubin.
Regarding claim 14, Rubin does not specifically disclose in the FIG. 1 embodiment wherein bonding dielectric layers are disposed directly between the device layer and the PDN.
In FIGS. 6-9, however, Rubin discloses wherein various layers may be bonded by dielectric layers (FIGS. 6-9, depicting wherein various structures of the device such as device tier T1 and backside layer BSL are bonded using dielectric bonding layers 206/208, [0059], and device tiers T1/T2 are bonded using dielectric bonding layer 232). Regarding the bonding, in [0059], Rubin states: “To begin, FIG. 6 is a schematic cross-sectional side view of the semiconductor device 20 at an intermediate stage of fabrication in which a wafer bonding process is performed to bond a semiconductor-on-insulator (SOI) substrate to a backside layer BSL comprising a backside power distribution plane.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the disclosed semiconductor device of FIG. 10 of Rubin by adding the bonding layers of FIGS. 6-9 of Rubin in order to bond the BEOL layer, which includes a power distribution plane 132 with the device tier T2. See Rubin [0059].
Moreover, addition of the bonding dielectric layers of FIGS. 6-9 of Rubin would result in a configuration wherein the bonding dielectric layers are disposed directly between the device layer (FIG. 1, device tier T2) and the PDN (FIG. 1, power distribution plane 132).
Regarding claim 15, Rubin FIG. 1, as modified by Rubin FIGS. 6-9 further discloses wherein via-to-BPRs (VBPRs) (FIG. 1, e.g., contacts C4/C5/C6/C7, metallic layers M0, via V0, metallic layer M1, via V1, [0036]-[0041]) of the device layer extend through the bonding dielectric layers to the PDN (FIG. 1, depicting wherein the contacts contacts C4/C5/C6/C7, metallic layers M0, via V0, metallic layer M1, via V1 would extend through bonding dielectric layers disposed at the interface between the device tier T2 and the BEOL layer to the power distribution plane 132).
Claims 1-7 and 9-13 are rejected under 35 U.S.C. § 103 as being unpatentable over Rubin in view of U.S. Patent Publication No. 2023/0005863 (filed Sept. 22, 2021) (hereinafter “Yang”).
Regarding independent claim 1, Rubin discloses: A semiconductor structure (FIG. 10, depicting a semiconductor device 30, [0069]) comprising: a device layer (FIG. 10, e.g., second device tier T2, [0036]) including a plurality of active devices (FIG. 10, depicting a plurality of FinFET devices, [0036]);
back-end-of-line (BEOL) components (FIG. 10, depicting BEOL layer, [0074]) disposed under the device layer (FIG. 10, depicting wherein the BEOL layer is disposed under the second device tier T2);
a power distribution network (PDN) (FIG. 10, depicting power distribution plane 320, [0069]) disposed over the device layer (FIG. 10, depicting wherein the power distribution plane is disposed over the second device tier T2).
While Rubin states in [0042] that “the device tiers T1 and T2 can additionally or alternately include other types of FET devices such as planar FET devices,” Rubin does not specifically disclose backside transistors disposed on a single crystal silicon (Si) layer disposed over the PDN.
In the same field of endeavor, Yang discloses a semiconductor structure (FIG. 29A, 3D memory device 2900, [0294]) including backside transistors (FIG. 29A, e.g., transistors 2908/2910, [0295]) disposed on a single crystal silicon (Si) layer (FIG. 29A, semiconductor layer 1004, which may be formed from single crystalline silicon, [0295]) disposed over a PDN (FIG. 29A, e.g., interconnect layer 2926, [0302]). Regarding the configuration of the transistors, in [0115], Yang states: “It is understood that in some examples, different from polysilicon layer 106 in first semiconductor structure 102, semiconductor layer 1004 on which the transistors are formed may include single crystalline silicon, but not polysilicon, due to the superior carrier mobility of single crystalline silicon that is desirable for transistors' performance.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Rubin by substituting the transistor configuration of Yang in order to improve the performance of the transistors. See Yang [0115].
Moreover, the substitution of the transistor configuration of Yang would result in a configuration wherein the transistors are disposed over the power distribution plane 320.
Regarding claim 2, Rubin in view of Yang further discloses wherein bonding dielectric layers (FIG. 10, depicting bonding layers 330/332, which may be formed from dielectric material, [0059]) are disposed directly between the device layer and the PDN (FIG. 10, depicting wherein the bonding layers 330/332 are disposed directly between the second device tier T2 and the power distribution plane 320).
Regarding claim 3, Rubin in view of Yang further discloses wherein a through silicon via (TSV) (FIG. 10, e.g., contact 314, contact C1, contact pad 328, contact 344, contact C4, and metallic structures M0 forming a through silicon via, [0036]-[0041]) extends from the backside transistors disposed on the single crystal Si layer through the BEOL (FIG. 10, depicting wherein the through silicon via extends from the layer in which the transistor configuration of Yang is formed through the BEOL layer).
Regarding claim 4, Rubin in view of Yang further discloses wherein an upper TSV (uTSV) (FIG. 10, e.g., contact 314, contact C1, contact pad 328 forming an upper through silicon via, [0036]-[0041]) extends from the PDN through the backside transistors disposed on the single crystal Si layer (FIG. 10, depicting wherein the upper through silicon via extends from the power distribution plane 320 through the layer in which the transistor configuration of Yang is formed).
Regarding claim 5, Rubin in view of Yang further discloses wherein via-to-BPRs (VBPRs) (FIG. 10, contacts 344, [0073]) of the device layer (FIG. 10, e.g., second device tier T2) extend through bonding dielectric layers to the PDN (FIG. 10, depicting wherein the contacts 344 extend through bonding layers 330/332 to the power distribution plane 320).
Regarding claim 6, Rubin in view of Yang further discloses wherein source/drain (S/D) contacts (FIG. 29A, depicting wherein the transistors 2908/2910 include source and drain contacts, [0295]) are disposed over the backside transistors disposed on the single crystal Si layer (FIG. 29A, depicting wherein the source and drain contacts are disposed over the transistors 2908/2910 on the substrate 1004).
Regarding claim 7, Rubin in view of Yang further discloses wherein an etch stop layer (FIG. 10, e.g., insulating layer 318 formed from silicon oxide, which is an etch stop material, [0061], [0070]) is disposed directly between the PDN and the backside transistors disposed on the single crystal Si layer (FIG. 10, depicting wherein the insulating layer 318 is disposed directly between the power distribution plane 320 and the layer in which the transistor configuration of Yang is formed).
Regarding claim 9, while Rubin states in [0042] that “the device tiers T1 and T2 can additionally or alternately include other types of FET devices such as planar FET devices,” Rubin does not specifically disclose wherein the backside transistors are disposed on a single crystal silicon (Si) layer.
In the same field of endeavor, Yang discloses a semiconductor structure (FIG. 29A, 3D memory device 2900, [0294]) including backside transistors (FIG. 29A, e.g., transistors 2908/2910, [0295]) disposed on a single crystal silicon (Si) layer (FIG. 29A, semiconductor layer 1004, which may be formed from single crystalline silicon, [0295]). Regarding the configuration of the transistors, in [0115], Yang states: “It is understood that in some examples, different from polysilicon layer 106 in first semiconductor structure 102, semiconductor layer 1004 on which the transistors are formed may include single crystalline silicon, but not polysilicon, due to the superior carrier mobility of single crystalline silicon that is desirable for transistors' performance.”
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Rubin by substituting the transistor configuration of Yang in order to improve the performance of the transistors. See Yang [0115].
Regarding claim 10, Rubin in view of Yang further discloses wherein a through silicon via (TSV) (FIG. 1, e.g., contact 114, contact C3, contact 124, contact C8, metallic structure M0, via V0, metallic structure M1, via V1, metallic structure M2, via V2, metallic structure M3 forming a through silicon via, [0036]-[0041]) extends from the backside transistors disposed on the single crystal Si layer through the BEOL (FIG. 1, depicting wherein the through silicon via extends from the layer in which the transistor configuration of Yang is formed through the BEOL layer).
Regarding claim 11, Rubin in view of Yang further discloses wherein an upper TSV (uTSV) (FIG. 1, e.g., contact 114, contact C3, contact 124, contact C8, metallic structure M0, via V0, metallic structure M1, via V1, metallic structure M2 forming an upper through silicon via) extends from the PDN through the backside transistors disposed on the single crystal Si layer (FIG. 1, depicting wherein the upper through silicon via extends from the power distribution plane 132 through the layer in which the transistor configuration of Yang is formed).
Regarding claim 12, Rubin in view of Yang further discloses wherein source/drain (S/D) contacts (FIG. 29A, depicting wherein the transistors 2908/2910 include source and drain contacts, [0295]) are disposed over the backside transistors disposed on the single crystal Si layer (FIG. 29A, depicting wherein the source and drain contacts are disposed over the transistors 2908/2910 on the substrate 1004).
Regarding claim 13, Rubin in view of Yang further discloses wherein an etch stop layer (FIG. 1, e.g., insulating layer 118 formed from silicon oxide, which is an etch stop material, [0037], [0061]) is disposed directly between the PDN and the backside transistors disposed on the single crystal Si layer (FIG. 1, depicting wherein the insulating layer 118 is disposed directly between the power distribution plane 132 and the layer in which the transistor configuration of Yang is formed).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: U.S. Patent Publication Nos.: 2023/0352369; 2015/0021784; 2011/0193240.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
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/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813