DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 9 and 17 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Seetharaman (US 11243252 B1)
Regarding Claim 1, Seetharaman teaches:
A processor comprising: remote test data registers; (Seetharaman, Fig. 1, TDR(120), Col. 2, FIG. 1 shows a system 100 including CPU2TDR interface logic 150 that enables a CPU (not shown) to directly interact with test data registers 120. Examiner's note: According to spec, [0038] Remote test data registers are registers that are outside the corresponding TAP controller. )
a JTAG (Joint Test Action Group) port including a serial communications interface to provide access to the remote test data registers; (Seetharaman, Col. 2, FIG. 1 shows JTAG ports 110, which are compliant with, e.g., the JTAG standard wherein automatic test equipment (ATE) (not shown) supports signals such as TMS (test mode select), test data in (TDI), and test data out (TDO), for example. JTAG ports 110 are in communication with TAP controller 115, which is, in turn, in communication, via bus 118, to one or more TDRs 120.)
and a Test Access Port Bridge (Seetharaman, Fig. 2, CPU2TDR(250)) to provide access to a subset of the remote test data registers (Seetharaman, Col. 3, FIG. 2 shows a system including CPU2TDR interface logic 250 that enables a CPU to directly interact with TDRs 120, and bypass TAP controller 115) in parallel. (Seetharaman, Col. 3, CPU2TDR interface logic 250 provides an interface 265 to TAP controller 115 enabling, for example, signals received via bus 260, to be broadcast to multiple TDRs simultaneously.)
Regarding Claim 9,
The system of claim 9 performs the same method steps as the processor of claim 1, and claim 9 is therefore rejected using the same rationale set forth above in the rejection of claim 1.
Seetharaman further teaches:
A system comprising: memory to store instructions and data; (Seetharaman, Col.7, The computer program product may include a non-transitory computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of presented herein.)
and a processor coupled to the memory to execute the instructions, (Seetharaman, Col.7, The computer program product may include a non-transitory computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of presented herein.)
Regarding Claim 17,
The system of claim 17 performs the same method steps as the processor of claim 1, and claim 17 is therefore rejected using the same rationale set forth above in the rejection of claim 1.
Allowable Subject Matter
Claims 2-8, 10-16, 18-24 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
(US 11243252 B1): A method includes disconnecting a data bus connecting a test access port (TAP) controller of an integrated circuit (IC) chip to a plurality of test data registers deployed on the chip, simultaneously supplying test data to multiple test data registers among the plurality of test data registers, and storing test response data, received from the plurality of test data registers and responsive to the test data, in storage registers deployed on the chip.
(US 20190128963 A1): A distributed test circuit includes partitions arranged in series to form a scan path, each partition including a scan multiplexer, a test data register, and a segment insertion bit component. The scan multiplexer of each partition provides inputs to the corresponding test data register of the each partition. Broadcast control logic generates a select signal to the scan multiplexer of each partition to place the test circuit in a broadcast mode when the select signal is asserted, and to switch the test circuit to a daisy mode when select signal is de-asserted. The segment insertion bit is operable to include or bypass each partition from the scan path.
(US 11782092 B1): A method for testing a chip comprising: receiving N scan-in chains of test data; using the N scan-in chains of test data to perform tests on the chip; receiving a merged expected test-result and masking-instruction signal on X pins of the chip from the off-chip test equipment, X being less than 2*N; decoding the merged expected test-result and masking-instruction signal to extract N decoded output signals, each of the N decoded output signals corresponding to a respective chain of test results.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XINYUAN YU whose telephone number is (571)272-7140. The examiner can normally be reached Monday-Friday 8:30-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at 571-272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/XINYUAN YU/Examiner, Art Unit 2113 /BRYCE P BONZO/Supervisory Patent Examiner, Art Unit 2113