DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: “Semiconductor Device for performing a Product-Sum calculation”.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the flip-flop as in claim 3, and claim 9 must be shown or the feature canceled from the claims. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 2-5 are objected to because of the following informalities.
Claim 2 line 5 recites “wherein each of plurality of pieces of quantized input data”. For antecedent basis reasons, this should recite “wherein each of the plurality of pieces of quantized input data”.
Claim 3 recites “configurated”. This appears to be a typographical error and should possibly recite “configured”. Claims 4-5 inherit the same deficiency as claim 3 based on dependence.
Claim 4 lines 5-6 recite “the first buffer of the second buffer”. This appears to be a typographical error and should possibly recite “the first buffer or the second buffer”. Claim 5 inherits the same deficiency as claim 4 based on dependence.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 line 3 recites “a first buffer holding output data”, and line 5-6 further recites “quantizing a plurality of pieces of output data”, and line 7-8 further recites “the plurality of pieces of output data being composed of the output data”, and lines 15-16 further recite “storing the output data in the first buffer”. It is unclear whether each of the recitations of “output data” is the same output data. Furthermore it is unclear how the same first buffer holds the output data, that is then apparently sequentially operated upon, and then the same output data is stored in the first buffer after it has previously been held in the first buffer. Said another way it is not clear which action comes first if this is the same data, or if this is different data whether it replaces the output data or overwrites, or appends, or other. Claims 2-6 inherit the same deficiency as claim 1 based on dependence. Claim 7 recites substantially the same limitations and is rejected for the same reasons. Claims 8-12 inherit the same deficiency as claim 7 based on dependence.
Claim 3 recites “the first buffer is configurated by a flip-flop”. Examiner interprets as configured instead of configurated. It is unclear how a flip-flop configures a buffer. For purposes of examination, Examiner interprets as “the first buffer comprises a flip-flop”. Claims 4-5 inherit the same deficiency as claim 3 based on dependence. Claim 9 recites substantially the same limitation and is rejected for the same reason. Claims 10-11 inherit the same deficiency as claim 9 based on dependence.
Claim 4 line 3 recites “a second buffer holding the output data”. It is unclear whether both the first buffer and the second buffer hold the same data, whether the first buffer holds a portion of the output data, the second buffer holds another portion of the output data or other. For purposes of examination, Examiner interprets as the first buffer holds a first portion of the output data, and the second buffer holds a second portion of the output data. Claim 4 further recites “a demultiplexer making a selection of which one of the first buffer or the second buffer the output data is stored in”, and “selecting any one of the output data held in the first buffer or the output data held in the second buffer”. Similarly, it is unclear whether this refers to the same output data or different output data. For purposes of examination, Examiner interprets as different output data. Claim 5 inherits the same deficiency as claim 4 based on dependence. Claim 10 recites substantially the same limitation and is rejected for the same reason. Claim 11 inherits the same deficiency as claim 10 based on dependence.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 6-7, 9, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over US 20190294413 A1 Vantrease et al., (hereinafter “Vantrease”) in view of Technologies, (hereinafter “Vantrease”) in view of B. Holdsworth et al., Counters and Registers, Digital Logic Design, Ch 7, (Fourth Edition), 2002 (hereinafter “Holdsworth”).
Regarding claim 1, Vantrease teaches the following:
a first buffer holding output data (Fig. 5, state buffer 522 for first buffer, [0074] state buffer includes input data and weights, and output data from computing engine 524, and/or output data from post-processor 528);
sequentially generating a plurality of pieces of quantized input data by quantizing a plurality of pieces of output data sequentially inputted from the first buffer by bit-shifting, the plurality of pieces of output data being composed of the output data ([0096-0098], shifted quantized inputs as in [0098] first sentence and in [0103], fig 8 820;825;830 for quantization, the bit shifted data composed of output data as in [0074], the output data is input to the computing engine wherein quantizing is performed);
a product-sum operator generating operation data by performing a product-sum operation to a plurality of parameters and the plurality of pieces of quantized input data from quantizer (fig 5 computing engine 524, [0074], and fig 6, [0076] showing details of the computing engine include product sum operators); and
a second shift generating the output data by inversely quantizing the operation data from the product -sum operator by bit-shifting ([0091], fig 7B 770, fig 8 850, [0099] eqn 20), and
storing the output data in the first buffer (Fig. 5, state buffer 522 for first buffer, [0074] state buffer includes input data and weights, and output data from computing engine 524, and/or output data from post-processor 528).
Vantrease discloses sequentially generating a plurality of pieces of quantized input data by quantizing/dequantizing a plurality of pieces of output data sequentially inputted from the first buffer by bit-shifting, but does not explicitly disclose quantizing/dequantizing the plurality of pieces of output data by bit-shifting using a first shift register/second shift register. However, in the same field of endeavor of bit-shifting, Holdsworth discloses a shift register for bit-shifting (7.15 Shift registers). It would have been obvious to one of ordinary skill in the art before the effective filling date for Vantrease to use a first and second shift register disclosed by Holdsworth for bit shifting to quantize/dequantize the plurality of pieces of output data sequentially inputted from the first buffer. It is obvious to use a known technique to a known device ready for improvement to achieve predictable results. MPEP 2141.III.(D).
Regarding claim 3, Vantrease in view of Holdsworth teach the claim 1 limitations. Holdsworth further teaches:
wherein the first buffer is configurated by a flip-flop (section 7.15 fig 7.23).
The motivation to combine provided with respect to claim 1 applies equally to claim 3.
Regarding claim 6, in addition to the teachings addressed in the claim 1 analysis, Vantrease further teaches:
a buffer controller variously controlling a bit width of the output data ([0124]).
Regarding claim 7, Vantrease teaches the following:
a neural network engine executing a neural network processing (fig 5 502);
one or more memories holding a plurality of pieces of data and a plurality of parameter (fig 5 512 memory, [0071]);
a processor (fig 11 1100 computing device): and
a bus connecting the neural network engine, the one or more memories, and the processor to one another (fig 5 518 interconnect, [0069]),
wherein the neural network engine includes:
a first buffer holding output data (Fig. 5, state buffer 522 for first buffer, [0074] state buffer includes input data and weights, and output data from computing engine 524, and/or output data from post-processor 528);
sequentially generating a plurality of pieces of quantized input data by quantizing a plurality of pieces of output data sequentially inputted from the first buffer by bit-shifting, the plurality of pieces of output data being composed of the output data ([0096-0098], shifted quantized inputs as in [0098] first sentence and in [0103], fig 8 820;825;830 for quantization, the bit shifted data composed of output data as in [0074], the output data is input to the computing engine wherein quantizing is performed);
a product-sum operator generating operation data by performing a product-sum operation to a plurality of parameters and the plurality of pieces of quantized input data from quantizer (fig 5 computing engine 524, [0074], and fig 6, [0076] showing details of the computing engine include product sum operators); and
a second shift generating the output data by inversely quantizing the operation data from the product -sum operator by bit-shifting ([0091], fig 7B 770, fig 8 850, [0099] eqn 20), and
storing the output data in the first buffer (Fig. 5, state buffer 522 for first buffer, [0074] state buffer includes input data and weights, and output data from computing engine 524, and/or output data from post-processor 528).
Vantrease discloses sequentially generating a plurality of pieces of quantized input data by quantizing/dequantizing a plurality of pieces of output data sequentially inputted from the first buffer by bit-shifting, but does not explicitly disclose quantizing/dequantizing the plurality of pieces of output data by bit-shifting using a first shift register/second shift register. However, in the same field of endeavor of bit-shifting, Holdsworth discloses a shift register for bit-shifting (7.15 Shift registers). It would have been obvious to one of ordinary skill in the art before the effective filling date for Vantrease to use a first and second shift register disclosed by Holdsworth for bit shifting to quantize/dequantize the plurality of pieces of output data sequentially inputted from the first buffer. It is obvious to use a known technique to a known device ready for improvement to achieve predictable results. MPEP 2141.III.(D).
Regarding claim 9, Vantrease in view of Holdsworth teach the claim 7 limitations. Holdsworth further teaches:
wherein the first buffer is configurated by a flip-flop (section 7.15 fig 7.23).
The motivation to combine provided with respect to claim 7 applies equally to claim 9.
Regarding claim 12, in addition to the teachings addressed in the claim 7 analysis, Vantrease further teaches:
wherein the neural network engine further includes a buffer controller variously controlling a bit width of the output data ([0124]).
Claims 2, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Vantrease in view of Holdsworth in view of US 20200264876 A1 Lo et al., (hereinafter “Lo”).
Regarding claim 2, Vantrease in view of Holdsworth teach the claim 1 limitations. Vantrease further teaches a memory holding the plurality of parameters (Fig 5 512, [0071]), and wherein each of the plurality of pieces of quantized input data and the plurality of parameters is an integer of 8 bits or less ([0017-0018], [0041], [0084-0085]). Vantrease does not, however, explicitly disclose wherein the plurality of parameters are quantized in advance and are stored in the memory. However, in the same field of endeavor, Lo discloses an apparatus similar to Vantrease for training a neural network accelerated using quantized data formats (abstract). Lo further discloses wherein the plurality of parameters are quantized in advance and are stored in the memory (fig 6 630, fig 7 770 [0107]). It would have been obvious to one of ordinary skill in the art before the effective data to further include storing the plurality of parameters quantized by Vantrease in memory as disclosed by Lo. It would have been obvious to achieve the benefit of reusing the quantized plurality of parameters in subsequent layers (fig 7, [0199-0131]).
Regarding claim 8, Vantrease in view of Holdsworth teach the claim 7 limitations. Vantrease further teaches a memory holding the plurality of parameters (Fig 5 512, [0071]), and wherein each of the plurality of pieces of quantized input data and the plurality of parameters is an integer of 8 bits or less ([0017-0018], [0041], [0084-0085]). Vantrease does not, however, explicitly disclose wherein the plurality of parameters are quantized in advance and are stored in the memory. However, in the same field of endeavor, Lo discloses an apparatus similar to Vantrease for training a neural network accelerated using quantized data formats (abstract). Lo further discloses wherein the plurality of parameters are quantized in advance and are stored in the memory (fig 6 630, fig 7 770 [0107]). It would have been obvious to one of ordinary skill in the art before the effective data to further include storing the plurality of parameters quantized by Vantrease in memory as disclosed by Lo. It would have been obvious to achieve the benefit of reusing the quantized plurality of parameters in subsequent layers (fig 7, [0199-0131]).
Claims 4, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Vantrease in view of Holdsworth in view of us 20200174749 A1 Kang et al., (hereinafter “Kang”).
Regarding claim 4, Vantrease in view of Holdsworth teach the claim 3 limitations. Vantrease is silent with respect to a second buffer holding the output data and configured by a SRAM; a demultiplexer making a selection of which one of the first buffer of the second buffer the output data is stored in; and a multiplexer selecting any one of the output data held in the first buffer or the output data held in the second buffer, and outputting it to the first shift register. However, in the same field of endeavor Kang discloses an apparatus for performing arithmetic processing including matrix multiplication comprising multiplications and accumulations (fig 7). Kang further discloses:
a second buffer holding the output data (fig 6 635);
a demultiplexer making a selection of which one of the first buffer of the second buffer the output data is stored in (fig 6 645 selecting either Buffer 1 630 or Buffer 2 635); and
a multiplexer selecting any one of the output data held in the first buffer or the output data held in the second buffer, and outputting it to the arithmetic logic unit (ALU) (Fig 6 Mux 650).
Kang does not explicitly disclose that the second buffer is configured by a SRAM. However, in a separate section, Kang discloses memory may be SRAM ([0124]). It would have been obvious to one of ordinary skill in the art before the effective filing date to choose the SRAM as disclosed by Kang as the type of buffer for the second buffer of Kang. It is obvious to use a known technique to a known device ready for improvement to achieve predictable results. MPEP 2141.III.(D).
It would have been further obvious to one of ordinary skill in the art before the effective filing data to substitute the first buffer of Vantrease with the demultiplexer, first buffer, second buffer, and multiplexer as disclosed by Kang, wherein the output of Kang’s multiplexer being output to the first shift register of Vantrease. It would have been obvious to achieve the benefit of choosing between different sources of the plurality of pieces of data to be operated on by the product-sum operator (Kang [0084-0087]).
Regarding claim 10, Vantrease in view of Holdsworth teach the claim 9 limitations. Vantrease is silent with respect to a second buffer holding the output data and configured by a SRAM; a demultiplexer making a selection of which one of the first buffer of the second buffer the output data is stored in; and a multiplexer selecting any one of the output data held in the first buffer or the output data held in the second buffer, and outputting it to the first shift register. However, in the same field of endeavor Kang discloses an apparatus for performing arithmetic processing including matrix multiplication comprising multiplications and accumulations (fig 7). Kang further discloses wherein the neural network engine further includes:
a second buffer holding the output data (fig 6 635);
a demultiplexer making a selection of which one of the first buffer of the second buffer the output data is stored in (fig 6 645 selecting either Buffer 1 630 or Buffer 2 635); and
a multiplexer selecting any one of the output data held in the first buffer or the output data held in the second buffer, and outputting it to the arithmetic logic unit (ALU) (Fig 6 Mux 650).
Kang does not explicitly disclose that the second buffer is configured by a SRAM. However, in a separate section, Kang discloses memory may be SRAM ([0124]). It would have been obvious to one of ordinary skill in the art before the effective filing date to choose the SRAM as disclosed by Kang as the type of buffer for the second buffer of Kang. It is obvious to use a known technique to a known device ready for improvement to achieve predictable results. MPEP 2141.III.(D).
It would have been further obvious to one of ordinary skill in the art before the effective filing data to substitute the first buffer of Vantrease with the demultiplexer, first buffer, second buffer, and multiplexer as disclosed by Kang, wherein the output of Kang’s multiplexer being output to the first shift register of Vantrease. It would have been obvious to achieve the benefit of choosing between different sources of the plurality of pieces of data to be operated on by the product-sum operator (Kang [0084-0087]).
Allowable Subject Matter
Claim 5, and 11 would be allowable if rewritten to overcome the rejections under 35 USC 112b, and if claim 5 were rewritten to overcome the claim objection, and if claims 5 and 11 were rewritten to overcome the claim objections, and rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter.
Applicant claims apparatus for executing a neural network processing, wherein the apparatus comprises a first buffer, a first shift register, a product-sum operator, and a second shift register. The apparatus as in claims 5, and 11 further comprise a second buffer. The primary reason for indication of allowable subject matter are the limitations in combination with the remaining limitations wherein a bit width of the first buffer is smaller than a bit width of the second shift register, and a bit width of the second buffer is the same as a bit width of the second shift register.
Vantrease is the closest prior art found. Vantrease discloses the claimed invention according to the above claim mappings. Vantrease discloses a buffer controller variously controlling a bit width of the output data ([0124]), but does not teach or suggest wherein a bit width of the first buffer is smaller than a bit width of the second shift register, and a bit width of the second buffer is the same as a bit width of the second shift register.
Kang discloses an apparatus for performing arithmetic processing including matrix multiplication comprising multiplications and accumulations (fig 7), and in accordance with the above claim mappings. Kang further discloses first and second buffer (fig 6), but does not teach or suggest wherein a bit width of the first buffer is smaller than a bit width of the second shift register, and a bit width of the second buffer is the same as a bit width of the second shift register.
Lo discloses an apparatus for training a neural network accelerated using quantized data formats, and various different precision (abstract, [0049], [0088-0090]). Lo does not, however, teach or suggest wherein a bit width of the first buffer is smaller than a bit width of the second shift register, and a bit width of the second buffer is the same as a bit width of the second shift register.
US 20220114426 Kim et al., (hereinafter “Kim”) discloses a neural network operation apparatus that includes a multiply-accumulate array, a memory, and a controller (abstract, fig 3). Kim further discloses that a weight buffer may have a height and a width that may vary, be set by the controller depending on the type of operation ([0084]). Kim does not, however, teach or suggest wherein a bit width of the first buffer is smaller than a bit width of the second shift register, and a bit width of the second buffer is the same as a bit width of the second shift register.
US 20180121795 A1 Kato et al., (hereinafter “Kato”) discloses a data processing apparatus including a storage unit storing reference data of a filter operation and coefficient data of the filters, and wherein an operation includes a product-sum operation (abstract, fig 3). Kato further discloses reference data registers, coefficient data registers are shift registers having a data load function including a plurality of registers having a same bit width as a reference data buffer and the coefficient data buffer respectively ([0058]). Kato does not, however, teach or suggest wherein one buffer is smaller than a shift register, only teaching wherein the buffer is the same width. Kato therefore, does not teach or suggest wherein a bit width of the first buffer is smaller than a bit width of the second shift register, and a bit width of the second buffer is the same as a bit width of the second shift register.
Conclusion
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/EMILY E LAROCQUE/Examiner, Art Unit 2182
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