DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to Applicant’s Amendment and Remarks filed on 02 February 2026.
Claims 1-2 and 4-21 are pending in this application. Claim 3 was cancelled. Claim 21 is newly added.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-2 and 4-21 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Claim 1 is rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1, Statutory Category: Yes, the claim 1 is a method that performing a series of steps and therefore falls in the statutory category of a process.
Step 2A- Prong 1: Judicial Exception Recited: Yes, the claim recites: “identifying, based on a dependency relationship, one of the first tasks in one of the plurality of task sets associated with the target task; scheduling, in response to the one of the first tasks being executed and based on the dependency relationship indicating that the target task is to be executed after the one of the first tasks is executed, the hardware accelerator to execute the target task”. As drafted, the claim as a whole recites a scheduling method that performing a series of steps that could be performed in the human mind, but for the recitation of generic computing components. The human mind can easily judging/evaluating/determining/identifying the dependency relationship between the tasks, determining/identifying the associated dependent task based on the identified dependency, judging/evaluating/determining if the parent task or producer task (i.e., one of the first tasks in one of the plurality of task sets) has been executed, then scheduling/planning the hardware accelerator to execute the target task or consumer task based on the dependent task has been executed. Therefore, but for the recitation of generic computing components, these steps may be a Mental Processes that can be performed in the human mind (including an observation, evaluation, judgment, opinion).
Therefore, yes, the claims do recite judicial exceptions.
Step 2A- Prong 2: Integrated into a practical Application: No, this judicial exception is not integrated into a practical application. In particular, the claim recites an additional limitations that “obtaining, through a communication interface communicatively coupling a task scheduler and a hardware processor, a plurality of task sets for execution by a hardware accelerator, wherein each of the plurality of tasks sets comprises a plurality of first tasks;” and “obtaining, from one of the plurality of execution queues stored in the storage medium of the task scheduler, a target task requiring data processing by the hardware accelerator” which is insignificant pre-solution data gathering (see MPEP § 2106.05(g)). In addition, “hardware accelerator”, “task scheduler” and “wherein the dependency relationship indicates an execution sequence of the first tasks in the one of the plurality of task sets, wherein the first tasks in the one of the plurality of task sets comprise the target task, wherein for each of the first tasks in the one of the plurality of task sets, the dependency relationship comprises a first task identifier identifying the first task, an entry event description describing a first event required to trigger the first task, and a related event description describing a second event that is triggered after the first task is completed, wherein the entry event description comprises a second task identifier identifying a second task to be completed before the first task is triggered, wherein the related event description comprises a third task identifier identifying a third task to be executed after the first task is completed, and wherein the first task, the second task, and the third task require data processing by the hardware accelerator” are directed to Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (see MPEP 2106.05(f)). Further, “executing, by the hardware accelerator, the target task to obtain output data” which is merely applying the judicial exception or abstract idea (See MPEP 2106.05(f)). The claim does not providing any details on how that “executing” will be occur. And the limitation of “storing a plurality of execution queues corresponding to the hardware accelerator to a storage medium of the task scheduler, wherein each of the plurality of execution queues corresponds to one of the plurality of task sets”; and “storing, by the hardware accelerator, the output data to a memory device” which is insignificant extra-solution activity and merely data storing (see MPEP § 2106.05(g)). The combination of these additional elements is no more than mere instructions to apply the exception using a generic computer component (MPEP 2106.05(f)). Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they not impose any meaningful limits on practicing the abstract idea. Therefore, the claim is directed to the abstract idea.
Step 2B: Claim provides an Inventive Concept: No. The additional elements “hardware accelerator”, “task scheduler” and “wherein the dependency relationship indicates an execution sequence of the first tasks in the one of the plurality of task sets, wherein the first tasks in the one of the plurality of task sets comprise the target task, wherein for each of the first tasks in the one of the plurality of task sets, the dependency relationship comprises a first task identifier identifying the first task, an entry event description describing a first event required to trigger the first task, and a related event description describing a second event that is triggered after the first task is completed, wherein the entry event description comprises a second task identifier identifying a second task to be completed before the first task is triggered, wherein the related event description comprises a third task identifier identifying a third task to be executed after the first task is completed, and wherein the first task, the second task, and the third task require data processing by the hardware accelerator are directed to Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (see MPEP 2106.05(f))). In addition, the limitation of “executing, by the hardware accelerator, the target task to obtain output data” which is merely applying the judicial exception or abstract idea (See MPEP 2106.05(f)). Further, the limitation of “storing a plurality of execution queues corresponding to the hardware accelerator to a storage medium of the task scheduler, wherein each of the plurality of execution queues corresponds to one of the plurality of task sets” and “storing, by the hardware accelerator, the output data to a memory device” which is insignificant extra-solution activity and merely data storing (see MPEP § 2106.05(g)), and the limitation “obtaining, through a communication interface communicatively coupling a task scheduler and a hardware processor, a plurality of task sets for execution by a hardware accelerator, wherein each of the plurality of tasks sets comprises a plurality of first tasks;” and “obtaining, from one of the plurality of execution queues stored in the storage medium of the task scheduler, a target task requiring data processing by the hardware accelerator” which is insignificant pre-solution data gathering (see MPEP § 2106.05(g)) and they are well understood, routine, conventional activity (see MPEP § 2106.05(d)). Courts have identified “receiving and transmitting data, storing and retrieving information” as well understood, routine, conventional and mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (see MPEP 2106.05(f))). These additional elements and combination of the elements does not amount to significant more than the exception itself or provide an inventive concept in Step 2B.
Under the 2019 PEG, a conclusion that an additional element is insignificant extra-solution activity in Step 2A should be re-evaluated in Step 2B. Here, the “obtaining” and “storing” steps were considered to be extra-solution activity in Step 2A as insignificant pre-solution data gathering and merely data storing which are well understood, routine, conventional activity in the field. The “obtaining” step is for the purpose of “communication” and “gathering” data and these can be reached on one of court case (Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) see MPEP § 2106.05(d) II). Additionally, the “storing” can be reached on one of court case (Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93; see MPEP §2106.05(d)(II) iv.). Accordingly, a conclusion that the obtaining and storing are well understood, routine, conventional activity is supported under Berkheimer options 2.
For these reasons, there is no inventive concept in the claim, and thus the claim is ineligible.
Independent claims 9 and 14 are rejected for the same reason as claim 1 above. In addition, independent claims 9 and 14 further recites “A task scheduler”, “comprising: a memory configured to store instructions; and a processor coupled to the memory and configured to execute the instructions to”. These additional elements are directed to generic computing components/Functions (MPEP § 2106.05(b) merely applying the abstract idea (MPEP § 2106.05(f)).
With respect to the dependent claim 2, the claim elaborates that wherein scheduling the hardware accelerator comprises scheduling the hardware accelerator to execute the target task according to the execution sequence (“scheduling the hardware accelerator to execute” as being treated as part of abstract idea and is analogous to Mental processes, such that concept can be performed in the human mind).
With respect to the dependent claim 4, the claim elaborates that storing an identifier of the target task in the one of the plurality of execution queues, and wherein after scheduling the hardware accelerator, the method further comprises: receiving an indication message from the hardware accelerator, wherein the indication message indicates that the hardware accelerator has executed the target task; and deleting, in response to the receiving the indication message, the identifier from the one of the plurality of execution queues (“storing” which is insignificant extra-solution activity and merely data storing (see MPEP § 2106.05(g)). “receiving an indication message” which is insignificant pre-solution data gathering (see MPEP § 2106.05(g)). In addition, “deleting, in response to the receiving… the identifier from the one of the plurality of execution queues” which is insignificant extra-solution activity (see MPEP § 2106.05(g) data manipulating) which is well understood, routine, conventional and this can be reached on LiVecchi (US Pub. 2001/0018701 A1), [0094] “Techniques for removing entries from queues, and placing entries on queues, are well known in the art”. Accordingly, a conclusion that the deleting is well understood, routine, conventional activity is supported under Berkheimer options 3).
With respect to the dependent claim 5, the claim elaborates that storing data obtained after executing the first tasks, wherein the first tasks form a scheduled task (“storing” which is insignificant extra-solution activity and merely data storing (see MPEP § 2106.05(g)) and which is well understood, routine, conventional and this can be reached on one of court case (Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93; see MPEP §2106.05(d)(II) iv.). Accordingly, a conclusion that the storing is well understood, routine, conventional activity is supported under Berkheimer options 2).
With respect to the dependent claim 6, the claim elaborates that obtaining from a terminal device using a camera device installed on the terminal device, data that forms the plurality of task sets (“obtaining…data” which is insignificant pre-solution data gathering (see MPEP § 2106.05(g)). In addition, the claims as a whole is a Mental Processes that can be performed in the human mind (including an observation, evaluation, judgment, opinion)).
With respect to the dependent claim 7, the claim elaborates that wherein storing the data comprises storing feedback data from an artificial intelligence (AI) module, and wherein the Al module belongs to the hardware accelerator (“storing feedback data” which is insignificant extra-solution activity and merely data storing (see MPEP § 2106.05(g)) and which is well understood, routine, conventional and this can be reached on one of court case (Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93; see MPEP §2106.05(d)(II) iv.). Accordingly, a conclusion that the storing is well understood, routine, conventional activity is supported under Berkheimer options 2. In addition, “wherein the Al module belongs to the hardware accelerator” are directed to Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (see MPEP 2106.05(f)) and an attempt to generally link the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
With respect to the dependent claim 8, the claim elaborates that wherein the feedback data comprises: first data to sense a lane line or a stop line; second data to sense a safety area; and third data to sense an obstacle. (“wherein the feedback data comprises: first data to sense a lane line or a stop line; second data to sense a safety area; and third data to sense an obstacle” are directed to Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (see MPEP 2106.05(f)) and an attempt to generally link the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
With respect to the dependent claim 10, the claim elaborates that wherein the task scheduler comprises the plurality of execution queues, wherein the one of the plurality of execution queues stores an identifier of the target task, wherein the hardware accelerator is further configured to execute the target task by using the identifier to execute the target task, and wherein the hardware(“wherein the task scheduler comprises the plurality of execution queues, wherein the one of the plurality of execution queues stores an identifier of the target task” and “wherein the hardware accelerator is further configured to execute the target task by using the identifier to execute… wherein the hardware Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (see MPEP 2106.05(f)) and an attempt to generally link the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)). In addition, “wherein the hardware accelerator is further configured to execute the target task” does not necessary mean that the target task is actually executed, it just indicated that the hardware accelerator is able to execute the target task).
Dependent claims 11 and 13 recite the same features as applied to claims 5 and 7 respectively above, therefore they are also rejected under the same rationale.
With respect to the dependent claim 12, the claim elaborates that wherein the output data is from a terminal device using a camera device installed on the terminal device (“output data is from a terminal device” which is insignificant pre-solution data gathering (see MPEP § 2106.05(g)). In addition, the claims as a whole is a Mental Processes that can be performed in the human mind (including an observation, evaluation, judgment, opinion)).
Dependent claims 15, 17-18 and 19-20 recite the same features as applied to claims 2, 4-5 and 7-8 respectively above, therefore they are also rejected under the same rationale.
With respect to the dependent claim 16, the claim elaborates that wherein the hardware accelerator corresponds to the one of the plurality of execution queues, and wherein an identifier of the target task is stored in the one of the plurality of execution queues (these limitations are directed to Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (see MPEP 2106.05(f)) and an attempt to generally link the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h))).
With respect to the dependent claim 21, the claim elaborates that wherein after scheduling the hardware accelerator to execute the target task, the method further comprises instructing the hardware accelerator to store output data generated after executing the target task in the memory device, wherein the output data is directly accessible by a second hardware accelerator for executing a second associated task without copying the output data, wherein the second associated task is identified from the dependency relationship as requiring execution after the target task, and wherein the hardware accelerator and the second hardware accelerator communicate with the task scheduler via direct hardware access interfaces (“instructing the hardware accelerator to store output data” which is insignificant extra-solution activity and merely data storing (see MPEP § 2106.05(g)) and which is well understood, routine, conventional and this can be reached on one of court case (Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93; see MPEP §2106.05(d)(II) iv.). In addition, “wherein the output data is directly accessible by a second hardware accelerator for executing a second associated task without copying the output data, wherein the second associated task is identified from the dependency relationship as requiring execution after the target task, and wherein the hardware accelerator and the second hardware accelerator communicate with the task scheduler via direct hardware access interfaces” are directed to Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (see MPEP 2106.05(f)) and an attempt to generally link the use of the judicial exception to a particular technological environment or field of use (MPEP 2106.05(h)).
Claim Rejections - 35 USC § 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-2 and 4-21 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
As per claims 1, 9 and 14 (line# refers to claim 1):
Lines 16-17, it recites “the first task” lacks antecedence basis. It is uncertain if this term intent to refer to “one of the first tasks” as cited in line 11 or any task within the “plurality of task sets” as cited in line 3 or just any task that is identified as “first task”. For examining purpose, examiner will interpret the first task as any task.
As per claim 21:
Line 2, it recites “output data”. However, prior to this phrase at line 27 at claim 1, it recites “output data”. Thus, it is unclear whether the second recitation of “output data” is the same or different from the first recitation of “output data”. If they are the same, the or said should be used.
As per claims 2, 4-8, 10-13 and 15-21:
They are method, control system and task scheduler claims that depend from rejected claims and do not resolve the deficiencies thereof and are therefore rejected for the same reasons as above.
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5, 9, 11, 14-16, 18 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US Pub. 2020/0257560 A1) in view of Krishnamurthy et al. (US Pub. 2009/0217275 A1) and further in view of Balle et al. (US Pub. 2018/0150299 A1), LaRock et al. (US Pub. 2018/0293098 A1), KOBORI (US Pub. 2017/0147411 A1) and Hundley (US Patent. 7,925,863 B2).
Balle, LaRock, KOBORI and Hundley were cited in the previous Office Action.
As per claim 1, Wang teaches the invention substantially as claimed including A method comprising:
obtaining, through a communication interface communicatively coupling a task scheduler and a hardware processor, a plurality of task sets for execution, wherein each of the plurality of tasks sets comprises a plurality of first tasks (Wang, Fig. 4, 411 (as communication interface, 400 (as task scheduler), 401 (as hardware processor), 407 (as plurality of task sets), 403 (as hardware accelerator); Fig. 5C, 507 (as a plurality of task sets), 504 queue (as each of the plurality of tasks sets include plurality of first tasks); [0018] lines 1-7, a method in a multiprocessor system for managing the distribution of instructions from a plurality of instruction streams to a plurality of processing devices is provided. The plurality of processing devices include a plurality of central processing units (CPUs) and a plurality of accelerator devices. The method includes: receiving the plurality of instruction streams, wherein each instruction stream including a plurality of requested computations; [0068] lines 1-8, The example dispatcher 402 (as communication interface) is configured to receive multiple instruction streams, each instruction stream including a plurality of requested computations for processing data (e.g., perception data such as vision data) from a data source (e.g., a perception data source such as a camera, lidar, radar). The example dispatcher 402 is further configured to partition each instruction stream into a plurality of partitions based on a device);
storing a plurality of execution queues to a storage medium of the task scheduler, wherein each of the plurality of execution queues corresponds to one of the plurality of task sets (Wang, Fig. 4, 400 (as task scheduler), 404 queues; ; [0004] The plurality of scheduling queues are arranged in memory; Fig. 5C, each queue 504 corresponds to one of the plurality of task sets);
obtaining, from one of the plurality of execution queues stored in the storage medium of the task scheduler, a target task requiring data processing by the hardware accelerator (Wang, Fig. 5C, queue 504 with task A1_2 and A1_1 that corresponding to 509 accl 1 (As include task task); Fig. 7B, 712 with task obtained to be assigned to 716 (accelerator); [0066] A different algorithm may be used to process each instruction stream and may require different devices that are suitable for different types of computations; [0082] lines 1-14, FIG. 7B is a block diagram depicting another example environment 710 associated with an instruction stream manager. The example environment 710 includes a plurality of accelerator queues 712, a plurality of accelerator schedulers 714, and a plurality of accelerators 716. Each of the example accelerator schedulers 704 is assigned to a specific scheduling queue 712 and a specific accelerator 716 or type of accelerator that shares the same scheduling policy. Each example accelerator scheduler 714 is configured to schedule accelerator computations 711 to its associated accelerator 716 based on priority, release time, and deadline. Each example accelerator scheduler 714 is configured to schedule accelerator computations 711 from different streams to its associated accelerator 716 for execution in ascending order of their dispatch);
executing, by the hardware accelerator, the target task to obtain output data (Wang, Fig. 7B, task from queue 712 is executed by the accelerator 716 (see left portion of Fig); [0082] lines 12-16, Each example accelerator scheduler 714 is configured to schedule accelerator computations 711 from different streams to its associated accelerator 716 for execution in ascending order of their dispatch when the start of execution is not dependent on the completion of a precedent CPU task; also see Fig. 5B stream processing, the output of A1_1 of stream 1 processing will be obtained once complete the execution of the A1_1 and send to C2_1 as the input (i.e., dependency)).
Wang fails to specifically teach the obtained plurality of task sets for execution by a hardware accelerator and plurality of execution queues corresponding to the hardware accelerator.
However, Krishnamurthy teaches the obtained plurality of task sets for execution by a hardware accelerator and plurality of execution queues corresponding to the hardware accelerator (Krishnamurthy, Fig. 2, 201 accelerator has different partitions; Fig. 3, 300 queue 0-N (as plurality of execution queues); [0031] lines 3-4, a plurality of virtual input queues 300 may be included for a given accelerator; [0031] lines 17-30, Queue 0 (see 304) in FIG. 3 can support partition 0 on FIG. 2, Queue 0 (see 303) can support partition 1 on FIG. 2 and so on… As each task of a particular queue is completed, a next task included within the queue may be processed. In this manner, tasks assigned to any partition of an accelerator may be organized (as each queue has plurality of first tasks, and all queue together as plurality of task sets)).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Wang with Krishnamurthy because Krishnamurthy’s teaching of a plurality of virtual input queues may be included for a given accelerator for processing the plurality of task sets would have provided Wang’s system with the advantage and capability to allow the system to easily organizing the tasks assigned to a given accelerator in order to improving the system performance and increase accelerator throughput (see [0031] “increase accelerator throughput”).
Wang and Krishnamurthy fail to specifically teach identifying, by the task scheduler and based on a dependency relationship, one of the first tasks in one of the plurality of task sets associated with the target task, wherein the dependency relationship indicates an execution sequence of the first tasks in the one of the plurality of task set, wherein the first tasks in the one of the plurality of task sets comprise the target task,
However, Balle teaches identifying, by the task scheduler and based on a dependency relationship, one of the first tasks in one of the plurality of task sets associated with the target task, wherein the dependency relationship indicates an execution sequence of the first tasks in the one of the plurality of task set, wherein the first tasks in the one of the plurality of task sets comprise the target task, (Balle, [0067] lines 15-24, if the job analyzer 1406 determines that the output of the one task (e.g., task B) depends on the output of the first task (e.g., uses the final output of task A as an input), the job analyzer 1406 determines that the order of operations of those tasks is important to achieve a correct output; therefore, the task A (as determining, based on a dependency relationship, one of the first tasks (i.e., task A) that associated with the target task, (i.e., task B)) should be executed prior to the execution of task B. As discussed below, the job analysis is used to schedule the tasks across one or more accelerator devices 1222 for efficient execution of the requested job; also see [0076] lines 5-10, identify the tasks that can be executed in parallel to operate on the same data set…and the tasks (as one of the first tasks in one of the plurality of task sets that need to be executed in sequence) that are to be executed in sequence because of their dependency on the final output of other tasks [Examiner noted: identifying, based on a dependency relationship, one of the first tasks (i.e., task A) that associated with the target task, (i.e., task B) should be executed first, wherein the dependency relationship indicates an execution sequence of first tasks in a task set (i.e., task A and task B (as task set), and wherein the first tasks comprise the target task)]);
wherein the first task, the second task, and the third task require data processing by the hardware accelerator (Balle, [0071] lines 2-4, dividing a requested job to be accelerated into multiple tasks (as include first task, the second task, and the third task) to be executed on one or more accelerator devices);
scheduling, to execute the target task (Balle, [0069] lines 23-26, analyzing the data dependencies of the tasks identified by the job analyzer 1406, the task scheduler 1408 is configured to schedule the tasks to maximize the parallelization of the tasks and to minimize the execution time of the job (as to scheduling to execute the target tasks).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Wang and Krishnamurthy with Balle because Balle’s teaching of scheduling the tasks for execution on the accelerator based on the task dependency relationship would have provided Wang and Krishnamurthy’s system with the advantage and capability to schedule the tasks across one or more accelerator devices for efficient execution of the requested job which improving the system performance and efficiency (see Balle [0067] “schedule the tasks across one or more accelerator devices 1222 for efficient execution of the requested job”).
Wang, Krishnamurthy and Balle fails to explicitly teach wherein for each of the first tasks in the one of the plurality of task set, the dependency relationship comprises a first task identifier identifying the first task, an entry event description describing a first event required to trigger the first task, and a related event description describing a second event that is triggered after the first task is completed and scheduling, in response to the one of the first tasks being executed and based on the dependency relationship indicating that the target task is to be executed after the one of the first tasks is executed, the hardware accelerator to execute the target task.
However, LaRock teaches wherein for each of the first tasks in the one of the plurality of task set, the dependency relationship comprises a first task identifier identifying the first task, an entry event description describing a first event required to trigger the first task, and a related event description describing a second event that is triggered after the first task is completed (LaRock, [0017] lines 6-9, the computing device 101 may facilitate triggering, managing, and/or controlling computing tasks based on events and/or time factors; [0023] lines 1-8, The task registry 161 may be used to receive and/or store task information…The task registry 161 may comprise, for example, a registry table used to identify and/or define tasks and to store parameters for tasks; [0024] lines 2-3, The dependent task registry 163 may be used to receive and/or store dependent task information; [0031] lines 3-28, the computing device 101 may receive task information from a server 121 or server 131 (e.g., in an automated process) or may receive task information from a user device 151…Task information may comprise, for example, a unique identifier for a task, a description for the task, an indication of whether the task is time-based (e.g., triggered by time) or event-based (e.g., triggered by other the execution of other task(s)), a scheduled time for executing the task, a due out time for the task, event trigger dependencies for the task (e.g., which tasks are to be executed, whether initiated or completed, prior to execution of the current task), and/or other information relating to a task (as including describing a first event required to trigger the task, and a related event description describing a second event that is triggered after the task is completed (i.e., dependencies, event trigger dependencies). As will be described in further detail below, after task information is updated or generated, the task management computing device 101 may store, such as in the task registry 161 and/or the dependent task registry 163, the task information in association with the task (e.g., via the unique identifier for the task). In some aspects, entries in a task registry 161 table or dependent task registry 163 table may be used to store values for each piece of task information; also see Fig. 4, 430 Task trigger other tasks? (as triggered after the task is completed);
scheduling, in response to the one of the first tasks being executed and based on the dependency relationship indicating that the target task is to be executed after the one of the first tasks is executed, to execute the target task. (LaRock, Fig. 4, 424, 430 task triggers other tasks, YES to 432 trigger other tasks, 402 trigger by another task and 422 execute task; [0004] lines 18-25, The computing device may determine whether the plurality of dependent computing tasks has been executed. If the plurality of dependent computing tasks has been executed, the computing device may determine one or more nodes for executing the first computing task and cause transmission of the first computing task from the task queue to the one or more nodes for executing the first computing task; also see [0031] lines 3-28 as cited above for task information related task dependency).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Wang, Krishnamurthy and Balle with LaRock because LaRock’s teaching of executing the target task (i.e., first computing task) when the dependent tasks has completed execution based on the dependency information would have provided Wang, Krishnamurthy and Balle’s system with the advantage and capability to allow the system to ensuring the data dependencies between tasks during the execution in order to improving the system performance and efficiency (see LaRock [0002] “more efficient and accurate way of executing computing tasks, such as sequential execution of tasks”).
Wang, Krishnamurthy, Balle and LaRock fail to explicitly teach wherein the entry event description comprises a second task identifier identifying a second task to be completed before the first task is triggered, wherein the related event description comprises a third task identifier identifying a third task to be executed after the first task is completed.
However, KOBORI teaches wherein the entry event description comprises a second task identifier identifying a second task to be completed before the first task is triggered, wherein the related event description comprises a third task identifier identifying a third task to be executed after the first task is completed (KOBORI, Fig. 3, 301 task identifier, previous-task dependency information, 303 next-task dependency information; Fig. 4 and Fig. 5, 502, 301, task B, 302 task A; Fig. 8, S805; [0100] lines 1-8, A task command as described above also includes task dependency information that specifies another task having a dependency in terms of execution order with a task (the “task A” or “task B” in this case), which is specified to be executed, by the task command. Specifically, task dependency information includes previous-task dependency information 302 and next-task dependency information 303, as exemplified in FIG. 3; [0101] lines 1-7, The previous-task dependency information 302 represents whether a dependency exists between a task specified in a command and another task to be executed before that task. The next-task dependency information represents whether a dependency exists between a task specified in a command and another task to be executed after that task).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Wang, Krishnamurthy, Balle and LaRock with KOBORI because KOBORI’s teaching of providing a task dependency information which including different entries to describing the each tasks dependency information would have provided Wang, Krishnamurthy, Balle and LaRock’s system with the advantage and capability to allow the system to easily identifying which specific tasks should be executed prior and after for the target task during the task scheduling in order to improving the task scheduling efficiency and system performance (see KOBORI, [0020] “control execution of tasks so that the respective processing blocks can operate efficiently”).
Wang, Krishnamurthy, Balle, LaRock and KOBORI fail to specifically teach when scheduling the target tasks, it is scheduling the hardware accelerator to execute, and storing, by the hardware accelerator, the output data to a memory device.
However, Hundley teaches when scheduling the target tasks, it is scheduling the hardware accelerator to execute (Hundley, Col 18, lines 34-46, Claim 10, scheduling an operation of the first hardware accelerator and scheduling an operation of the second hardware accelerator, including originally generating headers initiating respective operations independently of the computing device, wherein the first hardware accelerator is configured to, after the operation of the first hardware accelerator is completed, i) store output data of the first hardware accelerator in the memory on the accelerator card assembly, and ii) send a synchronization message to the second hardware accelerator to perform the operation of the second hardware accelerator), and
storing, by the hardware accelerator, the output data to a memory device (Hundley, Fig. 3, 330A to 330n HW accelerators, 340 memory, 314 data; Col 17, lines 44-60, a playlist indicating operations to be performed by the first and second accelerators from the computing device, wherein the task management unit i) processes the received playlist and initiates the decompression operation and the virus detection based, in part, on the received playlist, and ii) operates, including initiating the decompression operation and the virus detection operation, independently of the computing device, and wherein the first accelerator is configured to, after the first accelerator operation is completed, i) store output data of the first accelerator in the memory on the accelerator card assembly, and ii) send a synchronization message to the second accelerator to perform the second accelerator operation, wherein output data from the first accelerator operation is used as input data for the second accelerator operation).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Wang, Krishnamurthy, Balle, LaRock and KOBORI with Hundley because Hundley’s teaching of storing the output of task after execution and allowing the other accelerator to using the stored output data as input to processing subsequence tasks would have provided Wang, Krishnamurthy, Balle, LaRock and KOBORI’s system with the advantage and capability to allow each hardware accelerator passing its output data to the next hardware accelerator in succession without an intervening trip across the I/O bus, and without any hardware/software synchronization which improving the processing speed and system efficiency (see Hundley, Col 6, lines 56-59 and Col 7, lines 5-6, “FIG. 3 provides a more bandwidth and memory efficient acceleration device”).
As per claim 2, Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley teach the invention according to claim 1 above. Balle further teaches wherein scheduling comprises scheduling to execute the target task according to the execution sequence (Balle, [0069] lines 17-26, the task scheduler 1408 schedules the tasks on one or more accelerator devices 1222 such that the decryption task is first executed, followed by the execution of the decompression task. As such, the task scheduler 1408 is configured to examine the characteristics of the tasks determined by the job analyzer 1406, to efficiently schedule the tasks on one or more accelerator devices 1222. By analyzing the data dependencies of the tasks identified by the job analyzer 1406, the task scheduler 1408 is configured to schedule the tasks to maximize the parallelization of the tasks and to minimize the execution time of the job). In addition, Hundley teaches scheduling the hardware accelerator to execute (Hundley, Col 18, lines 34-46, Claim 10, scheduling an operation of the first hardware accelerator and scheduling an operation of the second hardware accelerator, including originally generating headers initiating respective operations independently of the computing device, wherein the first hardware accelerator is configured to, after the operation of the first hardware accelerator is completed, i) store output data of the first hardware accelerator in the memory on the accelerator card assembly, and ii) send a synchronization message to the second hardware accelerator to perform the operation of the second hardware accelerator).
As per claim 5, Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley teach the invention according to claim 1 above. In addition, Hundley teaches storing data obtained after executing the first tasks, wherein the first tasks form a scheduled task (Hundley, Fig. 3, data 314, 310A, 312 were stored at memory (as data obtained after executing the tasks); Col 6, lines 51-57, FIG. 3 illustrates a computing system 300 including numbered arrows indicating data flow paths between a computing system 320 and a circuit card assembly 325. The system of FIG. 3 is advantageously enabled to execute a succession of operations by multiple independent hardware accelerators 300, with each hardware accelerator 330 passing its output data to the next hardware accelerator 330; Col 17, lines 44-60, a playlist indicating operations to be performed by the first and second accelerators from the computing device, wherein the task management unit i) processes the received playlist and initiates the decompression operation and the virus detection based, in part, on the received playlist, and ii) operates, including initiating the decompression operation and the virus detection operation, independently of the computing device, and wherein the first accelerator is configured to, after the first accelerator operation is completed, i) store output data of the first accelerator in the memory on the accelerator card assembly, and ii) send a synchronization message to the second accelerator to perform the second accelerator operation, wherein output data from the first accelerator operation is used as input data for the second accelerator operation (as first tasks performed by each accelerator as tasks form a scheduled task (i.e., playlist)).
As per claim 9, it is a control system claim of claim 1 above. Therefore, it is rejected for the same reason as claim 1 above. In addition, Balle further teaches A control system comprising: A task scheduler comprising: a memory configured to store instructions; and one or more processors coupled to the memory and configured to execute the instructions to cause the task scheduler to (Balle, Fig. 12, 1220 micro-orchestrator logic unit (as task scheduler); Fig. 13, 1312 CPU, 1314 memory, 1220; [0069] lines 2-5, the task scheduler 1408 may schedule those independent tasks on one or more accelerator devices 1222 on one or more accelerator sleds 1202 to be executed in parallel or at different times) and the hardware accelerator coupled to the task scheduler and configured to execute the target task to obtain output data (Balle, Fig, 12, 1202a, 1220 associated with 1222 accelerators; [0069] lines 23-26, analyzing the data dependencies of the tasks identified by the job analyzer 1406, the task scheduler 1408 is configured to schedule the tasks to maximize the parallelization of the tasks and to minimize the execution time of the job (as to scheduling to execute the target tasks; [0069] lines 9-11, he task scheduler 1408 schedules the dependent tasks to be sequentially executed in a correct order to achieve a correct output; [0106] lines 7-8, executing one or more of the tasks on the one or more accelerator devices; also see [0077] the accelerator devices 1222 may communicate with one another via the shared virtual memory 1282 to combine the outputs of the tasks to obtain the output of the job).
As per claim 11, it is a control system claim of claim 5 above. Therefore, it is rejected for the same reason as claim 5 above.
As per claim 14, it is a task scheduler claim of claim 1 above. Therefore, it is rejected for the same reason as claim 1 above. In addition, Balle further teaches A task scheduler, comprising a memory configured to store instructions; and a processor coupled to the memory and configured to execute the instructions to (Balle, Fig. 12, 1220 micro-orchestrator logic unit (as task scheduler); Fig. 13, 1312 CPU, 1314 memory, 1220; [0021] lines 2-5, The disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable…and executed by one or more processors; [0069] lines 2-5, the task scheduler 1408 may schedule those independent tasks on one or more accelerator devices 1222 on one or more accelerator sleds 1202 to be executed in parallel or at different times).
As per claim 15, it is a task scheduler claim of claim 2 above. Therefore, it is rejected for the same reason as claim 2 above.
As per claim 16, Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley teach the invention according to claim 14 above. Wang teaches wherein the hardware accelerator corresponds to the one of the plurality of execution queues (Wang, Fig. 4, 400 (as task scheduler), 404 queues; ; [0004] The plurality of scheduling queues are arranged in memory; Fig. 5C, each queue 504 corresponds to one of the plurality of task sets); [0082] lines 1-14, FIG. 7B is a block diagram depicting another example environment 710 associated with an instruction stream manager. The example environment 710 includes a plurality of accelerator queues 712, a plurality of accelerator schedulers 714, and a plurality of accelerators 716. Each of the example accelerator schedulers 704 is assigned to a specific scheduling queue 712 and a specific accelerator 716). Krishnamurthy further teaches wherein an identifier of the target task is stored in the one of the plurality of execution queues (Krishnamurthy, Fig. 2, 201 accelerator has different partitions; Fig. 3, 300 queue 0-N (as plurality of execution queues); [0031] lines 3-4, a plurality of virtual input queues 300 may be included for a given accelerator; (as include hardware accelerator corresponds to the one of the plurality of execution queue); [0031] lines 17-30, Queue 0 (see 304) in FIG. 3 can support partition 0 on FIG. 2, Queue 0 (see 303) can support partition 1 on FIG. 2 and so on… As each task of a particular queue is completed, a next task included within the queue may be processed. In this manner, tasks assigned to any partition of an accelerator may be organized; [0031] Each queue (301-304) may queue descriptors that include fields for identifying individual tasks).
As per claim 18, it is a task scheduler claim of claim 5 above. Therefore, it is rejected for the same reason as claim 5 above.
As per claim 21, Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley teach the invention according to claim 1 above. LaRock further teaches wherein the second associated task is identified from the dependency relationship as requiring execution after the target task (LaRock, [0017] lines 6-9, the computing device 101 may facilitate triggering, managing, and/or controlling computing tasks based on events and/or time factors; [0023] lines 1-8, The task registry 161 may be used to receive and/or store task information…The task registry 161 may comprise, for example, a registry table used to identify and/or define tasks and to store parameters for tasks; [0024] lines 2-3, The dependent task registry 163 may be used to receive and/or store dependent task information; [0031] lines 3-28, the computing device 101 may receive task information from a server 121 or server 131 (e.g., in an automated process) or may receive task information from a user device 151…Task information may comprise, for example, a unique identifier for a task, a description for the task, an indication of whether the task is time-based (e.g., triggered by time) or event-based (e.g., triggered by other the execution of other task(s)), a scheduled time for executing the task, a due out time for the task, event trigger dependencies for the task (e.g., which tasks are to be executed, whether initiated or completed, prior to execution of the current task), and/or other information relating to a task. As will be described in further detail below, after task information is updated or generated, the task management computing device 101 may store, such as in the task registry 161 and/or the dependent task registry 163, the task information in association with the task (e.g., via the unique identifier for the task). In some aspects, entries in a task registry 161 table or dependent task registry 163 table may be used to store values for each piece of task information; also see Fig. 4, 430 Task trigger other tasks?).
In addition, Hundley further teaches wherein after scheduling the hardware accelerator to execute the target task, the method further comprises instructing the hardware accelerator to store output data generated after executing the target task in the memory device, wherein the output data is directly accessible by a second hardware accelerator for executing a second associated task without copying the output data (Hundley, Fig. 3, 330A HW accelerator obtaining the data 310A for processing and storing the output to the 312, then the HW accelerator 330B is directly accessing that data for processing; Col 7, lines 53-55, Thus, in the embodiment of FIG. 3, two steps of the process described in FIG. 2 (steps 4 and 5) are eliminated (as without copying); and
wherein the hardware accelerator and the second hardware accelerator communicate with the task scheduler via direct hardware access interfaces (Fig. 3, 355 and 350 (as task scheduler); Col 4, lines 34-38, The circuit card assembly 125 communicates with the computing device 120 via an I/O bus 132 having a finite bandwidth. The bandwidth of the I/O bus is represented by .beta..sub.bus and has units of bits per second. The interface 150 may be an AGP or PCI interface).
Claims 4 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley, as applied to claims 1 and 16 respectively above, and further in view of Johnson et al. (US Patent. 9,569,255 B1).
Johnson was cited in the previous Office Action.
As per claim 4, Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley teach the invention according to claim 1 above. Krishnamurthy further teaches storing an identifier of the target task in the one of the plurality of execution queues (Krishnamurthy, [0031] Each queue (301-304) may queue descriptors that include fields for identifying individual tasks). In addition, Hundley teaches scheduling the hardware accelerator (Hundley, Col 18, lines 34-46, Claim 10, scheduling an operation of the first hardware accelerator and scheduling an operation of the second hardware accelerator, including originally generating headers initiating respective operations independently of the computing device, wherein the first hardware accelerator is configured to, after the operation of the first hardware accelerator is completed, i) store output data of the first hardware accelerator in the memory on the accelerator card assembly, and ii) send a synchronization message to the second hardware accelerator to perform the operation of the second hardware accelerator).
Although Hundley teaches scheduling the hardware accelerator, Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley fail to specifically teach wherein after scheduling, the method further comprises: receiving an indication message from the hardware accelerator, wherein the indication message indicates that the hardware accelerator has executed the target task; and deleting, in response to the receiving the indication message, the identifier from the one of the plurality of execution queues.
However, Johnson teaches after scheduling, the method further comprises: receiving an indication message from the hardware accelerator, wherein the indication message indicates that the hardware accelerator has executed the target task; (Johnson, Col 3, lines 4-10, A work item object identifier may be generated and associated with the work item object, and the work item object identifier may be added to a work item queue. The work item queue may include a collection of ordered work item object identifiers, with each identifier corresponding to a respective work item object representative of a corresponding work item; Col 5, lines 9-14, provide the task object to a task execution engine configured to execute the task object. Execution of a task object may be described herein interchangeably as execution of a task corresponding to the task object. Upon completion of execution of the task object (as target task), the task execution engine may generate a task completion event. Further, an interface for the task execution engine may define functions that may be called upon completion of a task; Col 5, lines 26-27, the client application may receive the task completion event; also see Col 21m line 54, a Field-Programmable Gate Array (FPGA); (please note: hardware accelerator also taught by Balle) and
deleting, in response to the receiving the indication message, the identifier from the one of the plurality of execution queues (Johnson, Fig. 3A, 316 and 320 queues; Col 14, line 61- Col 15, line 6, the client application 302 may also provide a dequeue command 324 to the state machine manager 306. The dequeue command 324 may include as parameters a work item object representation of a work item for which a workflow execution has been completed as well as a work item object identifier corresponding to the work item object. The work item object may be specified as a serialized representation of a data object such as a JAVA™ object. In response to the dequeue command 324, the state machine manager 306 may perform a third set of one or more operations 326 to remove the work item object identifier from a work item queue 330 stored in the persistent data storage 312).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley with Johnson because Johnson’s teaching of removing the identifier of the task from the queue after receiving the task completion would have provided Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley’s system with the advantage and capability to allow the system to dynamically managing the execution queues by removing the entry if the task is completed in order to improving the resource utilization and system performance.
As per claim 17, it is a task scheduler claim of claim 4 above (all the limitation of claim 17 are included in the claim 4). Therefore, it is rejected for the same reason as claim 4 above.
Claims 6 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley, as applied to claims 5 and 9 respectively above, and further in view of Lee et al. (US Pub. 2020/0151903 A1).
Lee was cited in the previous Office Action.
As per claim 6, Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley teach the invention according to claim 5 above. Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley fail to specifically teach obtaining from a terminal device using a camera device installed on the terminal device, data that forms the plurality of task sets.
However, Lee teaches obtaining from a terminal device using a camera device installed on the terminal device, data that forms the plurality of task sets (Lee, Fig. 1D, 170 input video, 186; [0010] lines 9-16, receiving calibration data from a camera of a user device, the calibration data comprising a first reference point associated with the gaming environment, a second reference point associated with the gaming environment, and sensor data associated with the user device; computing a camera projection based on the first reference point, the second reference point, and the sensor data obtained from the user device; [0017] lines 1-2, the sensor data comprises a camera intrinsic matrix of the camera; also see [0075] lines 4-12, user computing entity 200 may optionally comprise a graphics processing unit 240 (GPU) for specialized image and video rendering tasks (as plurality of task sets), and/or an artificial intelligence (AI) accelerator 242, specialized for applications including artificial neural networks, machine vision, and machine learning. In some embodiments, processing unit 210 may be coupled with GPU 240 and/or AI accelerator 242 to distribute and coordinate processing tasks (as obtaining from a terminal device using a camera device installed on the terminal device, data (i.e., senser data) that forms the task sets (image and data that to be performed)).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley with Lee because Lee’s teaching of obtaining the data from the camera of the user device and allowing the GPU to processing would have provided Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley’s system with the advantage and capability to allow the system to processing the image and video data with the sensor data by the GPU device of the user terminal which improving the system performance and efficiency (see Lee, [0115] “improvements in computational efficiency”).
As per claim 12, Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley teach the invention according to claim 9 above. Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley fail to specifically teach wherein the output data is from a terminal device using a camera device installed on the terminal device.
However, Lee teaches wherein the output data is from a terminal device using a camera device installed on the terminal device (Lee, Fig. 1D, 170 input video, 186; [0010] lines 9-16, receiving calibration data from a camera of a user device, the calibration data comprising a first reference point associated with the gaming environment, a second reference point associated with the gaming environment, and sensor data associated with the user device; computing a camera projection based on the first reference point, the second reference point, and the sensor data obtained from the user device; [0017] lines 1-2, the sensor data comprises a camera intrinsic matrix of the camera; also see [0075] lines 4-12, user computing entity 200 may optionally comprise a graphics processing unit 240 (GPU) for specialized image and video rendering tasks, and/or an artificial intelligence (AI) accelerator 242, specialized for applications including artificial neural networks, machine vision, and machine learning. In some embodiments, processing unit 210 may be coupled with GPU 240 and/or AI accelerator 242 to distribute and coordinate processing tasks (as obtaining from a terminal device using a camera device installed on the terminal device, data (i.e., senser data) that forms the tasks (image and data that to be performed)).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley with Lee because Lee’s teaching of obtaining the data from the camera of the user device and allowing the GPU to processing would have provided Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley’s system with the advantage and capability to allow the system to processing the image and video data with the sensor data by the GPU device of the user terminal which improving the system performance and efficiency (see Lee, [0115] “improvements in computational efficiency”).
Claims 7, 13 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley, as applied to claims 5, 9 and 18 respectively above, and further in view of ANDO (US Pub. 2019/0346836 A1) and Shi et al. (US Pub. 2020/0050924 A1).
ANDO and Shi were cited in the previous Office Action.
As per claim 7, Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley teach the invention according to claim 5 above. Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley fail to specifically teach wherein storing the data comprises storing feedback data from an artificial intelligence (AI) module and wherein the Al module belongs to the hardware accelerator.
However, ANDO teaches wherein storing the data comprises storing feedback data from an artificial intelligence (AI) module (ANDO, Fig. 1, 1310 object, 1302 control AI; [0055] lines 1-7, The control AI 1302 may be implemented by a processor and a memory of the controller 1301, for example. The control AI 1302 receives input data from the controller 1301, generates output data (as feedback data) for controlling an operation or a state of the object 1310; [0157] lines 1-4, the output data storage apparatus 550 stores the data output from the first artificial intelligence module in a time period during which the first machine learning is executed; [0056] lines 4-7, the object 1310 may be a production apparatus (a robot or a safety apparatus, for example) that is installed in a production line, or a vehicle (as terminal device)).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley with ANDO because ANDO’s teaching of utilizing the AI model to generating the output feedback data to controlling the object/terminal/vehicle would have provided Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley’s system with the advantage and capability to allow the system to utilizing the AI model for managing the terminal device in order to improving the terminal device’s performance and efficiency.
Wang, Krishnamurthy, Balle, LaRock, KOBORI, Hundley and ANDO fail to specifically teach wherein the Al module belongs to the hardware accelerator.
However, Shi teaches wherein the Al module belongs to the hardware accelerator (Shi, [0045] lines 1-15, the artificial intelligence chip (AI chip) 106, also referred to as an AI accelerator or computing card, i.e., a module specially configured to process a large amount of computational tasks in artificial intelligence applications…the artificial intelligence chip 106 may use these data for model training and/or testing. For another example, the CPU may transmit acquired to-be-analyzed data to the artificial intelligence chip 106. In this case, the artificial intelligence chip 106 may input the to-be-analyzed data into a trained model, to use the model for analysis.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Wang, Krishnamurthy, Balle, LaRock, KOBORI, Hundley and ANDO with Shi because Shi’s teaching of utilizing the AI accelerator card for processing would have provided Wang, Krishnamurthy, Balle, LaRock, KOBORI, Hundley and ANDO’s system with the advantage and capability to allow the system to improving the training speed and processing efficiency for the artificial intelligence in order to improving the overall performance.
As per claim 13, it is a control system claim of claim 7 above. Therefore, it is rejected for the same reason as claim 7 above.
As per claim 19, it is a task scheduler claim of claim 7 above. Therefore, it is rejected for the same reason as claim 7 above.
Claims 8 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang, Krishnamurthy, Balle, LaRock, KOBORI, Hundley, ANDO and Shi, as applied to claims 7 and 19 respectively above, and further in view of Pham et al. (US Pub. 2021/0201145 A1), LIU et al. (US Pub. 2020/0391729 A1).
As per claim 8, Wang, Krishnamurthy, Balle, LaRock, KOBORI, Hundley, ANDO and Shi teach the invention according to claim 7 above. Wang, Krishnamurthy, Balle, LaRock, KOBORI, Hundley, ANDO and Shi fail to specifically teach wherein the feedback data comprises: first data to sense a lane line or a stop line; second data to sense a safety area; and third data to sense an obstacle.
However, Pham teaches wherein the feedback data comprises: first data to sense a lane line or a stop line and third data to sense an obstacle (Pham, [0003] This understanding may include information as to locations of objects, obstacles, lanes, and/or intersections in the environment with respect to various demarcations, such as lanes, road boundaries, intersection lines, and/or the like; [0046] an intersection structure may be defined as a set of line segments corresponding to lanes, crosswalks, entry-lines, exit-lines, bike lanes, etc., in the sensor data 102. The line segments may be generated as polylines, with a center of each polyline defined as the center for the corresponding line segment. Semantic information (e.g., classifications) may be generated for each of the images (and/or other sensor data representations) and/or for each one or more of the line segments and centers in the images represented by the sensor data 102 used for training the DNN(s) 104. The number of classifications, similar to described above, may correspond to the number and/or types of features that the DNN(s) 104 is trained to predict, or to the number of lanes and/or types of features in the respective image. Depending on the embodiment, the classifications may correspond to classifications or tags corresponding to the feature type, such as but not limited to, crosswalk, crosswalk entry, crosswalk exit, intersection entry, intersection exit, and/or bike lane; [0107] Cameras with a field of view that include portions of the environment in front of the vehicle 800 (e.g., front-facing cameras) may be used for surround view, to help identify forward facing paths and obstacles, as well aid in, with the help of one or more controllers 836 and/or control SoCs, providing information critical to generating an occupancy grid and/or determining the preferred vehicle paths.).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Wang, Krishnamurthy, Balle, LaRock, KOBORI, Hundley, ANDO and Shi with Pham because Pham’s teaching of detecting lanes and obstacle would have provided Wang, Krishnamurthy, Balle, LaRock, KOBORI, Hundley, ANDO and Shi’s system with the advantage and capability to allow the system to improving the driving safety for the autonomous vehicle (see Pham, [0004] “become critical to safe and effective autonomous and/or semi-autonomous driving” and [0134] “to enhance overall system safety”).
Wang, Krishnamurthy, Balle, LaRock, KOBORI, Hundley, ANDO, Shi and Pham fail to specifically teach second data to sense a safety area.
However, LIU teaches second data to sense a safety area (LIU, [0017] A safe driving area boundary is determined for the ADV based on perception data perceiving a driving environment surrounding the ADV. The motion trajectory boundary and the safe drivable area boundary are projected onto a map such as an HD map. A relative location of the ADV within the map relative to the motion trajectory and the safe drivable area boundary is determined).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Wang, Krishnamurthy, Balle, LaRock, KOBORI, Hundley, ANDO, Shi and Pham with LIU because LIU’s teaching of determining safety area would have provided Wang, Krishnamurthy, Balle, LaRock, KOBORI, Hundley, ANDO, Shi and Pham’s system with the advantage and capability to allow the system to identifying a safe area in order to perform a fail-safe action or a fail operational action based on the relative location of the ADV in view of the motion trajectory boundary and the safe drivable area boundary (see LIU Abstract).
As per claim 20, it is a task scheduler claim of claim 8 above. Therefore, it is rejected for the same reason as claim 8 above.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley, as applied to claim 9 above, and further in view of Bass et al. (US Pub. 2013/0152099 A1).
Bass was cited in the previous Office Action.
As per claim 10, Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley teach the invention according to claim 9 above. Wang teaches wherein the task scheduler comprises the plurality of execution queues and wherein the hardware accelerator corresponds to the one of the plurality of execution queues (Wang, Fig. 4, 400 (as task scheduler), 404 queues; ; [0004] The plurality of scheduling queues are arranged in memory; Fig. 5C, each queue 504 corresponds to one of the plurality of task sets); [0082] lines 1-14, FIG. 7B is a block diagram depicting another example environment 710 associated with an instruction stream manager. The example environment 710 includes a plurality of accelerator queues 712, a plurality of accelerator schedulers 714, and a plurality of accelerators 716. Each of the example accelerator schedulers 704 is assigned to a specific scheduling queue 712 and a specific accelerator 716). Krishnamurthy further teaches wherein the one of the plurality of execution queues stores an identifier of the target task (Krishnamurthy, Fig. 2, 201 accelerator has different partitions; Fig. 3, 300 queue 0-N (as plurality of execution queues); [0031] lines 3-4, a plurality of virtual input queues 300 may be included for a given accelerator; (as include hardware accelerator corresponds to the one of the plurality of execution queue); [0031] lines 17-30, Queue 0 (see 304) in FIG. 3 can support partition 0 on FIG. 2, Queue 0 (see 303) can support partition 1 on FIG. 2 and so on… As each task of a particular queue is completed, a next task included within the queue may be processed. In this manner, tasks assigned to any partition of an accelerator may be organized; [0031] Each queue (301-304) may queue descriptors that include fields for identifying individual tasks).
Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley fail to specifically teach wherein the hardware accelerator is further configured to execute the target task by using the identifier to execute the target task.
However, Bass teaches wherein the hardware accelerator is further configured to execute the target task by using the identifier to execute the target task (Bass, Fig. 1, 104, Q1, 105 Q2, 106 Qn, 107 hw acc eng type 1, 108 hw acc eng type 2, 109 hw acc eng type n (as execution queue corresponding to the hardware accelerator); Fig. 6, Q1, Q2, Q3; [0028] lines 1-4, A queue entry is made up of storage elements containing information pertaining to a job, such as identifiers connecting the job to a software process; [0040] lines 1-16, If the JobType matches a dedicated hardware accelerator for a specific Q, step 302 continues to step 303 which ascertains whether Q.Head is already allocated. If it is not, then the incoming job may be enqueued in this QE in step 307 and in this instance Q.Head =Q.Tail. If it is already allocated, then step 304 determines whether any unallocated, i.e., floating, QEs exist. If no floating entries are available, the job is rejected in step 309. If at least one unallocated QE exists, step 305 determines whether Q.Limit has been met; if it has then the job is rejected in step 309. If Q.Limit has not been met, then step 306 enqueues QE at the tail of Q. In boxes 306 and 307, the notation QE.JobInfo<-JobDescriptor means fields from the JobDescriptor the hardware accelerator requires to perform the job are copied from the JobDescriptor to the QE.JobInfo register. Such fields may comprise operation code, operand addresses, unique job identifier, job priority, etc (as using the identifier to execute the target task)).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to have combined the teaching of Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley with Bass because Bass’s teaching of providing the corresponding queue for hardware accelerator for processing jobs would have provided Wang, Krishnamurthy, Balle, LaRock, KOBORI and Hundley’s system with the advantage and capability to allow the system to efficiently managing the finite number of hardware accelerators for processing which ensuring fairness in allocating available processing acceleration resources (see Bass, [0010] “Efficient utilization of a finite number of hardware accelerators requires a queue management system to prioritize processing jobs and ensure fairness in allocating available processing acceleration resources”).
Response to Arguments
Applicant’s arguments with respect to claims 1-2 and 4-21 under 35 U.S.C § 103 rejection have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
In the remark applicant’s argue in substance:
(a) after a task scheduler schedules a hardware accelerator to execute a target task from an execution queue, the task scheduler further instructs the hardware accelerator to store data generated after the target task is executed. In this way, the data generated after the target task is executed may be directly invoked by another hardware accelerator when subsequently required, and does not need to be copied. This reduces a data processing amount, reduces time, and indirectly improves system performance. Thus, claims 1-2 and 4-20 are directed to a particular improvement in the capabilities of a computing device. Additionally, claims 1-2 and 4-20 are not directed to mathematical concepts, certain methods of organizing human activity, or mental processes.
(b) Claims 1-2 and 4-20 improve the performance of a computing device in scheduling a hardware accelerator and storing data. As such, claims 1-2 and 4-20 are directed to a practical application, and thus the Applicant respectfully requests that the 35 U.S.C. § 101 rejections of claims 1-2 and 4-20 be withdrawn.
Examiner respectfully disagreed with Applicant’s argument for the following reasons:
As to point (a), in response to applicant’s argument that “the task scheduler further instructs the hardware accelerator to store data generated after the target task is executed. In this way, the data generated after the target task is executed may be directly invoked by another hardware accelerator when subsequently required, and does not need to be copied. This reduces a data processing amount, reduces time, and indirectly improves system performance”. Examiner respectfully disagreed.
Examiner would like to point out that “the data generated after the target task is executed may be directly invoked by another hardware accelerator when subsequently required, and does not need to be copied” are NOT in the claim. It is unclear how that last limitation of “storing” the output data will cause “the data generated after the target task is executed may be directly invoked by another hardware accelerator when subsequently required, and does not need to be copied” happened? That is, the claim does not providing any details on what happened after storing the output? How that subsequence hardware accelerator is actually executing by using the stored data directly without copying? Therefore, Applicant’s argument has not been found to be persuasive.
As to point (b), in response to applicant’s argument that “Claims 1-2 and 4-20 improve the performance of a computing device in scheduling a hardware accelerator and storing data”. Examiner respectfully disagreed.
MPEP 2106.05(a) discloses that “It is important to note, the judicial exception alone cannot provide the improvement. The improvement can be provided by one or more additional elements. See the discussion of Diamond v. Diehr, 450 U.S. 175, 187 and 191-92, 209 USPQ 1, 10 (1981)) in subsection II, below. In addition, the improvement can be provided by the additional element(s) in combination with the recited judicial exception”. Here, the claim providing the additional limitations including “obtaining” (which is insignificant pre-solution data gathering (see MPEP § 2106.05(g)) and “storing” (insignificant extra-solution activity and merely data storing (see MPEP § 2106.05(g)), and they are well understood, routine, conventional activity (see MPEP § 2106.05(d)). Courts have identified “receiving and transmitting data, storing and retrieving information” as well understood, routine, conventional and mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (see MPEP 2106.05(f))).
In addition, the claim further recites “hardware accelerator”, “task scheduler” and “wherein the dependency relationship indicates an execution sequence of the first tasks in the one of the plurality of task sets, wherein the first tasks in the one of the plurality of task sets comprise the target task, wherein for each of the first tasks in the one of the plurality of task sets, the dependency relationship comprises a first task identifier identifying the first task, an entry event description describing a first event required to trigger the first task, and a related event description describing a second event that is triggered after the first task is completed, wherein the entry event description comprises a second task identifier identifying a second task to be completed before the first task is triggered, wherein the related event description comprises a third task identifier identifying a third task to be executed after the first task is completed, and wherein the first task, the second task, and the third task require data processing by the hardware accelerator” are directed to Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea (see MPEP 2106.05(f)). Further, “executing, by the hardware accelerator, the target task to obtain output data” which is merely applying the judicial exception or abstract idea (See MPEP 2106.05(f)) (i.e., executing based on previous “identifying”). The claim does not providing any details what so ever on how the claimed function will occur. Please see 101 rejection above.
For the reasons above, Applicant’s argument has not been found to be persuasive, and therefore the rejections are maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ZUJIA XU/Examiner, Art Unit 2195
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