Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-2, 5, 7-10, 12-20, 23-29, and 32-36 are currently amended. No new claims have been added. No claims have been canceled. Claims 1-36 are pending for examination.
Response to Arguments
Applicant’s arguments, see pgs.8-11 , filed 6/8/2026, with respect to the rejection of claims 1, 10, 19, and 28 under 35 USC 102(a)(2) have been fully considered and are persuasive. Therefore, the rejection in view of Herbert has been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of Choquette (US 20230315655 A1).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 10, 11, 19, 20, 28, and 29 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Choquette (US 20230315655 A1)
As per claim 1, Choquette discloses:
One or more processors, comprising: circuitry to respond to a call to an application programming interface (API) to perform a kernel on an accelerator using one or more block clusters each comprising two or more groups of blocks of threads (“Each GPC includes a plurality of streaming multiprocessors (SM) that are each a massively parallel processor including a plurality of processor cores”, 0062 ; “As FIG. 4 shows, a CGA is a grid of clusters of thread blocks or CTAs organized as an array. Such CGAs provide co-scheduling, e.g., control over where clusters of CTAs are placed/executed in the GPU,”, 0066 ; “Hierarchical grouping of threads such as cooperating thread arrays (CTA) and cooperating group arrays (CGA) according to some embodiments are described in more detail in U.S. Application No. 17/691,621“, 0213 ; “The application may include an API call that is routed to the device driver for the PPU 1000. The device driver interprets the API call and performs various operations to respond to the API call… the device driver may perform operations, at least in part, by launching operations on the PPU 1000 utilizing an input/output interface between the CPU and the PPU 1000.”, 0242 ; “Various programs may be executed within the PPU 1000 in order to implement the various stages of the processing for the application program. For example, the device driver may launch a kernel on the PPU 1000 to perform one stage of processing on one SM 1140 (or multiple SMs 1140)”, 0243 ; Examiner Note: a cooperating group array (CGA) equates to a block cluster)
wherein to respond to the call, the circuitry at least:
schedules the two or more groups of blocks of threads to be performed in parallel by the accelerator, wherein each group of the two or more groups of blocks of threads is performed by a plurality of accelerator threads. (“As FIG. 4 shows, a CGA is a grid of clusters of thread blocks or CTAs organized as an array. Such CGAs provide co-scheduling, e.g., control over where clusters of CTAs are placed/executed in the GPU,”, 0066 ; “The PPU 1000 is a latency hiding architecture designed to process many threads in parallel.”, 0185 ; “ The scheduler unit 1020 manages the execution of a plurality of tasks on the one or more GPCs 1050.”, 0192 ; Examiner Note: graphics processing cores (GPCs) equate to accelerator threads)
As per claim 2, Choquette fully discloses the limitations of claim 1.
Furthermore, Choquette discloses:
To respond to the call to the API, the circuitry at least: generates the kernel to comprise multiple partitions of blocks of threads of a grid, the one or more block clusters being in at least one of the partitions. (“Various programs may be executed within the PPU 1000 in order to implement the various stages of the processing for the application program. For example, the device driver may launch a kernel on the PPU 1000 to perform one stage of processing on one SM 1140 (or multiple SMs 1140).”, 0243 ; “As FIG. 4 shows, a CGA is a grid of clusters of thread blocks or CTAs organized as an array. Such CGAs provide co-scheduling, e.g., control over where clusters of CTAs are placed/executed in the GPU,”, 0066; “Now, using the concurrent execution and additional shared memory supported by hardware, it is possible to directly share data between threads of one CTA and threads of another CTA - enabling dependencies across CTAs that can bridge hardware (e.g., cross-SM) partitions.”, 0070)
As per claim 10, it is a computer-implemented method claim with substantially the same limitations as claim 1, and as such it is rejected for substantially the same reasons.
As per claim 11, it is a computer-implemented method claim with substantially the same limitations as claim 2, and therefore it is rejected for substantially the same reasons.
As per claim 19, Choquette discloses:
A computer system comprising: one or more processors and memory storing executable instructions that, when performed by the one or more processors, are to: (“Each GPC includes a plurality of streaming multiprocessors (SM) that are each a massively parallel processor including a plurality of processor cores”, 0062 ; “Computer programs, or computer control logic algorithms, may be stored in the main memory 1340 and/or the secondary storage. Such computer programs, when executed, enable the system 1365 to perform various functions.”, 0240)
respond to a call to an application programming interface (API) to perform a kernel on an accelerator using one or more block clusters each comprising two or more groups of blocks of threads (“As FIG. 4 shows, a CGA is a grid of clusters of thread blocks or CTAs organized as an array. Such CGAs provide co-scheduling, e.g., control over where clusters of CTAs are placed/executed in the GPU,”, 0066 ; “Hierarchical grouping of threads such as cooperating thread arrays (CTA) and cooperating group arrays (CGA) according to some embodiments are described in more detail in U.S. Application No. 17/691,621“, 0213 ; “The application may include an API call that is routed to the device driver for the PPU 1000. The device driver interprets the API call and performs various operations to respond to the API call… the device driver may perform operations, at least in part, by launching operations on the PPU 1000 utilizing an input/output interface between the CPU and the PPU 1000.”, 0242 ; “Various programs may be executed within the PPU 1000 in order to implement the various stages of the processing for the application program. For example, the device driver may launch a kernel on the PPU 1000 to perform one stage of processing on one SM 1140 (or multiple SMs 1140)”, 0243 ; Examiner Note: a cooperating group array (CGA) equates to a block cluster)
wherein to respond to the call, the circuitry at least:
schedules the two or more groups of blocks of threads to be performed in parallel by the accelerator, wherein each group of the two or more groups of blocks of threads is performed by a plurality of accelerator threads. (“As FIG. 4 shows, a CGA is a grid of clusters of thread blocks or CTAs organized as an array. Such CGAs provide co-scheduling, e.g., control over where clusters of CTAs are placed/executed in the GPU,”, 0066 ; “The PPU 1000 is a latency hiding architecture designed to process many threads in parallel.”, 0185 ; “ The scheduler unit 1020 manages the execution of a plurality of tasks on the one or more GPCs 1050.”, 0192 ; Examiner Note: graphics processing cores (GPCs) equate to accelerator threads)
As per claim 20, it is a computer system claim with substantially the same limitations as claim 2, provided by the computer system of claim 19, and therefore it is rejected for substantially the same reasons.
As per claim 28, it is a non-transitory machine readable medium (see Choquette, [0240]) claim with substantially the same limitations as claim 1, and as such it is rejected for substantially the same reasons.
As per claim 29, it is a machine-readable medium claim with substantially the same limitations as claim 2, provided by the machine-readable medium of claim 28, and therefore it is rejected for substantially the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3- 4, 12- 13, 21-22, and 30-31 are rejected under 35 U.S.C. 103 as being unpatentable over Choquette (US 20230315655 A1) in view of Perelygin (US 11080111 B1).
As per claim 3, Choquette fully discloses the limitations of claim 1, but does not explicitly disclose the API being called during compilation of a program to comprise the kernel.
However, Perelygin discloses:
the API is to be called during compiling of a program to comprise the kernel. (“In at least one embodiment, source code 602 is compiled into a kernel 606 by a compiler 604. In at least one embodiment, a compiler 604 is a set of software instructions that, when executed, take as input one or more source code files 602 and translate said source code files 602 into executable code such as a kernel 606. In at least one embodiment, a compiler 604 links in supporting libraries implementing additional functionality such as parallel computing functionality provided by an API, such as CUDA or other parallel computing libraries described herein, during compilation of a kernel 606.”, 0077)
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the performance of a kernel by an API call causing of two or more groups of thread blocks to be scheduled in parallel of Choquette (0066) with the method of Perelygin (0077) in order to provide a system capable of calling an API during compilation of a program from source code, thereby allowing for the system to place the API calls sooner and consequently arrive at the compiled kernel running threads in parallel in a shorter amount of time.
As per claim 4, Choquette fully discloses the limitations of claim 1, but does not disclose the API being called during compilation of a kernel from source code.
However, Perelygin discloses:
the API is to be called during compilation of the kernel from source code. (Perelygin (US 11080111 B1) “In at least one embodiment, source code 602 is compiled into a kernel 606 by a compiler 604. In at least one embodiment, a compiler 604 is a set of software instructions that, when executed, take as input one or more source code files 602 and translate said source code files 602 into executable code such as a kernel 606. In at least one embodiment, a compiler 604 links in supporting libraries implementing additional functionality such as parallel computing functionality provided by an API, such as CUDA or other parallel computing libraries described herein, during compilation of a kernel 606.”, 0077)
As per claim 12, it is a computer-implemented method claim with substantially the same limitations as claim 3, and therefore it is rejected for substantially the same reasons.
As per claim 13, it is a computer-implemented method claim with substantially the same limitations as claim 4, and therefore it is rejected for substantially the same reasons.
As per claim 21, it is a computer system claim with substantially the same limitations as claim 3, provided by the computer system of claim 19, and therefore it is rejected for substantially the same reasons.
As per claim 22, it is a computer system claim with substantially the same limitations as claim 4, provided by the computer system of claim 19, and therefore it is rejected for substantially the same reasons.
As per claim 30, it is a machine-readable medium claim with substantially the same limitations as claim 3, provided by the machine-readable medium of claim 28, and therefore it is rejected for substantially the same reasons.
As per claim 31, it is a machine-readable medium claim with substantially the same limitations as claim 4, provided by the machine-readable medium of claim 28, and therefore it is rejected for substantially the same reasons.
Claims 5, 14, 23, and 32 are rejected under 35 U.S.C. 103 as being unpatentable over Choquette (US 20230315655 A1) in view of Reed (US 20230350661 A1).
As per claim 5, Choquette fully discloses the limitations of claim 1, but does not disclose an API call causing a scheduling policy to be set.
However, Reed discloses:
To respond to the call, the circuitry at least:
sets a scheduling policy (“Additionally or alternatively, the operator also defines in the initial API call 301 or another API call a set of push schedule rules and subscriber exclusion rules that control when and to whom the dependency-aware rules engine 300 may push upgrades”, 0041 ; Examiner Note: a set of schedule rules equates to a scheduling policy)
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the performance of a kernel by an API call causing of two or more groups of thread blocks to be scheduled in parallel of Choquette (0066) with the API call to set a scheduling policy of Reed (0041) in order to provide an improved system which allows the operator to define a schedule remotely (Reed, [0021]).
As per claim 14, it is a computer-implemented method claim with substantially the same limitations as claim 5, and therefore it is rejected for substantially the same reasons.
As per claim 23, it is a computer system claim with substantially the same limitations as claim 5, provided by the computer system of claim 19, and therefore it is rejected for substantially the same reasons.
As per claim 32, it is a machine-readable medium claim with substantially the same limitations as claim 5, provided by the machine-readable medium of claim 28, and therefore it is rejected for substantially the same reasons.
Claims 6, 15, 24, and 33 are rejected under 35 U.S.C. 103 as being unpatentable over Choquette (US 20230315655 A1) in view of Kini (US 20230185706 A1).
As per claim 6, Choquette fully discloses the limitations of claim 1, but does not explicitly disclose the circuitry launching the kernel.
However, Kini discloses:
Circuitry is further to launch the kernel. (“In at least one embodiment, control thread 204 performs an API to launch a kernel, using systems and methods such as those described herein”, 0081 )
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the performance of a kernel by an API call causing of two or more groups of thread blocks to be scheduled in parallel of Choquette (0066) with the method of Kini (0081) in order to provide an API capable of both generating and launching a kernel- thereby increasing the efficiency of the computing system.
As per claim 15, it is a computer-implemented method claim with substantially the same limitations as claim 6, and therefore it is rejected for substantially the same reasons.
As per claim 24, it is a computer system claim with substantially the same limitations as claim 6, provided by the computer system of claim 19, and therefore it is rejected for substantially the same reasons.
As per claim 33, it is a machine-readable medium claim with substantially the same limitations as claim 6, provided by the machine-readable medium of claim 28, and therefore it is rejected for substantially the same reasons.
Claims 7, 16, 25, and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Choquette (US 20230315655 A1) in view of Powers (US 20160371081 A1).
As per claim 7, Choquette fully discloses the limitations of claim 1, but does not disclose the API causing the kernel to be performed by an accelerator.
However, Powers discloses:
To respond to the call to the API, the circuitry at least:
causes the kernel to be performed by an accelerator ( “On runtime computing system 12, the host software may use a DASH API to execute computational kernels, almost as if it were calling a regular function.”, 0026 ; “For example, end user 15 can select processing units 12 (e.g., off-the-shelf components, such as GPU's, FPGA's, CPU's) that meet particular operational and environmental requirements, confident in the knowledge that execution of software 10, and particularly source code 8, will utilize the capabilities of the various hardware resources during execution of application source code 6 and computational source code 8 on runtime computing system 12.”, 0021 ; Examiner Note: a GPU equates to an accelerator)
It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the performance of a kernel by an API call causing of two or more groups of thread blocks to be scheduled in parallel of Choquette (0066) with the method of Powers (0081) in order to provide an API capable of both generating a GPU kernel, and causing the GPU kernel to be performed, thereby increasing the efficiency of CPU – GPU interaction, and leading to the kernel being performed on the GPU sooner than if a different API had to be called to cause the kernel to be performed.
As per claim 16, it is a computer-implemented method claim with substantially the same limitations as claim 7, and therefore it is rejected for substantially the same reasons.
As per claim 25, it is a computer system claim with substantially the same limitations as claim 7, provided by the computer system of claim 19, and therefore it is rejected for substantially the same reasons.
As per claim 34, it is a machine-readable medium claim with substantially the same limitations as claim 7, provided by the machine-readable medium of claim 28, and therefore it is rejected for substantially the same reasons.
Claims 8, 17, 26, and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Choquette (US 20230315655 A1) in view of Munshi (CN 102099789 A) [published: 2011-06-15, translation: PE2E].
As per claim 8, Choquette fully discloses the limitations of claim 1, but does not disclose the API call setting a dimension of the group of threads.
However, Munshi discloses:
To respond to the call to the API, the circuitry at least:
sets one or more dimensions of the two or more groups of blocks of threads. (“API request may include multi-dimensional value as the global thread number of the array N integers (G1A2,..., Gn). integer N is data parallel task-related dimension. processing 800 processing logic capable of counting the number of integer multidimensional value of the group to determine the dimension. in response to the API request, processing logic may process 800 according to a product of N integers G1 * G2 *-* Gn, determining the total number of thread of executable code is performed between the multiple calculating units.”, 0075)
Furthermore, Choquette discloses:
two or more groups of blocks of threads. (“As FIG. 4 shows, a CGA is a grid of clusters of thread blocks or CTAs organized as an array. Such CGAs provide co-scheduling, e.g., control over where clusters of CTAs are placed/executed in the GPU,”, 0066 ; “The PPU 1000 is a latency hiding architecture designed to process many threads in parallel.”, 0185)
The system of Choquette in view of Munshi would be capable of setting the dimensions of two or more groups of blocks of threads. It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the performance of a kernel by an API call causing of two or more groups of thread blocks to be scheduled in parallel of Choquette (0066) with the method of Munshi (0075) in order to provide an API which is capable of setting the dimensions of the group of blocks being processed, thereby providing the API with increased control over the kernel’s execution, and ensuring that the dimensions of the group of blocks are appropriate for the kernel in an efficient manner.
As per claim 17, it is a computer-implemented method claim with substantially the same limitations as claim 8, and therefore it is rejected for substantially the same reasons.
As per claim 26, it is a computer system claim with substantially the same limitations as claim 8, provided by the computer system of claim 19, and therefore it is rejected for substantially the same reasons.
As per claim 35, it is a machine-readable medium claim with substantially the same limitations as claim 8, provided by the machine-readable medium of claim 28, and therefore it is rejected for substantially the same reasons.
Claims 9, 18, 27, and 36 are rejected under 35 U.S.C. 103 as being unpatentable over Choquette (US 20230315655 A1) in view of Yang (CN 107357661 A) [published: 2017-11-17, translation: PE2E].
As per claim 9, Choquette fully discloses the limitations of claim 1, but does not disclose the API indicating a maximum number of blocks per group of blocks.
However, Yang discloses:
To respond to the call to the API, the circuitry at least:
indicates a maximum number of blocks per group of blocks of threads (“In the step (3), according to the kernel functions of task, and task block size TaskBlockSizei, calculate The active threads number of blocks that can be accommodated on one GPU SM, what the process can be provided by CUDA CudaOccupancyMaxActiveBlocksPerMultiprocessorAPI can accommodate to calculate on each SM or CapSM Maximum activity thread number of blocks MaxActivePBlocki”, Par.34, contents of the invention)
The system of Choquette in view of Yang would be capable of indicating the maximum number of blocks per group in the API call which indicates number of threads and compute instances. It would have been obvious to one of ordinary skill in the art, before the effective filing date, to combine the performance of a kernel by an API call causing of two or more groups of thread blocks to be scheduled in parallel of Choquette (0066) with the method of Yang (Par.34, contents of the invention) in order to provide an API which is capable of indicating a maximum number of blocks of threads per group, thereby preventing the kernel from ever attempting to process a group with an incompatibly large number of blocks in a group- avoiding the potential errors associated with an excessively large group of blocks.
As per claim 18, it is a computer-implemented method claim with substantially the same limitations as claim 9, and therefore it is rejected for substantially the same reasons.
As per claim 27, it is a computer system claim with substantially the same limitations as claim 9, provided by the computer system of claim 19, and therefore it is rejected for substantially the same reasons.
As per claim 36, it is a machine-readable medium claim with substantially the same limitations as claim 9, provided by the machine-readable medium of claim 28, and therefore it is rejected for substantially the same reasons.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Slesarenko (US 20200394202 A1) – discloses an apparatus for extracting data from a database. Comprises a data extraction kernel on the native-side, and an API which is used to write database data to a buffer.
Fei (US 20230281748 A1) – discloses a method comprising building up a mapping between particles and background grid blocks; sorting the particles to a level of granularity; transferring momenta and masses of the particles to grid nodes on the background grid blocks to compute forces on the grid nodes; updating velocities and resolving collisions from the computed forces on the grid nodes; and applying the updated velocities back to the particles from the grid nodes and advecting the particles
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROSS MICHAEL VINCENT whose telephone number is (703)756-1408. The examiner can normally be reached Mon-Fri 8:30AM-5:30PM.
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/R.M.V./
Examiner, Art Unit 2196
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196
