DETAILED ACTION
Claims 1-25 are pending.
The office acknowledges the following papers:
Claims and remarks filed on 3/2/2026.
Withdrawn objections and rejections
The specification objections have been withdrawn due to amendment.
New Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-25 are rejected under 35 U.S.C. 103 as being unpatentable over Huntley et al. (U.S. 2016/0191525), in view of Official Notice.
As per claim 1:
Huntley disclosed an apparatus comprising:
decoder circuitry to decode an instance of a single instruction (Huntley: Figures 1-2 elements 110, 114, 200, 233-234, and 238, paragraphs 20, 27-28, and 30)(The processor includes SLDT, STR, and LSL instructions, which are decoded and executed by the processor.), the instance of the single instruction to include at least one field for an opcode (Huntley: Figures 1-2 elements 110, 114, 200, 233-234, and 238, paragraphs 20, 27-28, and 30)(The instruction format includes an opcode.), one or more fields to identify a source operand which is to store a Load Segment Limit (LSL) selector value, and one or more fields to identify a destination register operand (Huntley: Figure 2 elements 212, 216, 224, 233-234, and 238, paragraphs 20, 27-28, and 30)(The broadest reasonable interpretation of LSL selector value is a pointer to a segment or segment descriptor that defines the segment (see paragraph 39). The SLDT, STR, and LSL instructions reference memory/source registers to copy segment selectors/limits (i.e. LSL selector value) to a destination register.), wherein the opcode is to indicate that execution circuitry is to, when the single instruction has been enabled by a setting of a bit in a control register, write a LSL value stored in the control register to the destination operand when the LSL selector value of the source register operand matches a LSL selector value stored in the control register (Huntley: Figure 2 elements 220 and 260, paragraphs 24 and 32-33)(The broadest reasonable interpretation of the contingent limitation is that only the structure for performing the function is required to read upon the contingent limitation, regardless of whether or not the function condition occurs. Huntley includes control registers (i.e. structure for performing the function). Additionally, Huntley includes enable storage registers for a global enable bit for enabling supervisor mode protection.), and set a flag in a flags register (Huntley: Figure 2 elements 212-220, 224, and 260, paragraphs 12, 29, and 33)(The broadest reasonable interpretation of the contingent limitation is that only the structure for performing the function is required to read upon the contingent limitation, regardless of whether or not the function condition occurs. Huntley disclosed setting/clearing flags and setting/clearing enable bits, but doesn’t explicitly recite flag registers for storing such bits. Official notice is given that flag registers can be used within control and status registers for the advantage of compactly providing additional processor controls. Thus, it would have been obvious to one of ordinary skill in the art to implement flag registers (i.e. structure for performing the function) in Huntley to store such bits.); and
execution circuitry to execute the decoded instance of the single instruction according to the opcode (Huntley: Figure 2 element 240, paragraph 25).
As per claim 2:
Huntley disclosed the apparatus of claim 1, wherein the opcode is OF 03H (Huntley: Figures 1-2 elements 110, 114, 200, 233-234, and 238, paragraphs 20, 27-28, and 30)(The instruction format includes an opcode. Huntley doesn’t give an indication of the number of bits within an opcode field. It would have been obvious to one of ordinary skill in the art that the number of opcode field bits can match the opcode bits required for “OF 03H” for the advantage of implementing more instructions within the instruction set. Additionally, it would have been obvious to one of ordinary skill in the art that any given instruction can be given any opcode field bit value that is supported by the ISA. Thus, it would have been obvious to one of ordinary skill in the art to assign the “OF 03H” opcode value to one of the SLDT, STR, or LSL instructions.).
As per claim 3:
Huntley disclosed the apparatus of claim 1, wherein the source operand is register (Huntley: Figure 2 elements 214-216, 224, 233-234, and 238, paragraphs 20, 27-28, and 30)(The broadest reasonable interpretation of LSL selector value is a pointer to a segment or segment descriptor that defines the segment (see paragraph 39). The SLDT, STR, and LSL instructions reference memory/source registers to copy segment selectors/limits (i.e. LSL selector value) to a destination register.).
As per claim 4:
Huntley disclosed the apparatus of claim 1, wherein the source operand is memory location (Huntley: Figure 2 elements 214-216, 224, 233-234, and 238, paragraphs 20, 27-28, and 30)(The broadest reasonable interpretation of LSL selector value is a pointer to a segment or segment descriptor that defines the segment (see paragraph 39). The SLDT, STR, and LSL instructions reference memory/source registers to copy segment selectors/limits (i.e. LSL selector value) to a destination register.).
As per claim 5:
Huntley disclosed the apparatus of claim 1, wherein the flag is a zero flag (Huntley: Figure 2 elements 212-220, 224, and 260, paragraphs 12, 29, and 33)(The broadest reasonable interpretation of the contingent limitation is that only the structure for performing the function is required to read upon the contingent limitation, regardless of whether or not the function condition occurs. In view of the above official notice, Huntley includes flag registers (i.e. structure for performing the function) in Huntley to store such bits.).
As per claim 6:
Huntley disclosed the apparatus of claim 1, wherein the single instruction is to be deprecated in a first mode and not deprecated in a second mode (Huntley: Figure 2 elements 233-234 and 238, paragraphs 27-28, 30, and 33)(The global enable bit being set allows for execution of SLDT, STR, and LSL instructions in a supervisor mode and not executing the SLDT, STR, and LSL instructions below a ring 0 mode.).
As per claim 7:
Huntley disclosed the apparatus of claim 1, wherein when the LSL selector values to not match, the execution circuitry is to generate an undefined fault (Huntley: Figure 2 element 240, paragraph 25)(The broadest reasonable interpretation of the contingent limitation is that only the structure for performing the function is required to read upon the contingent limitation, regardless of whether or not the function condition occurs. Huntley includes an execution unit (i.e. structure for performing the function).).
As per claim 8:
Huntley disclosed the apparatus of claim 1, wherein when the LSL selector values to not match, the execution circuitry is to perform a legacy LSL operation (Huntley: Figure 2 element 240, paragraph 25)(The broadest reasonable interpretation of the contingent limitation is that only the structure for performing the function is required to read upon the contingent limitation, regardless of whether or not the function condition occurs. Huntley includes an execution unit (i.e. structure for performing the function).).
As per claim 9:
Huntley disclosed the apparatus of claim 1, wherein the control register is a model specific register (MSR) (Huntley: Figure 2 elements 212-220, 224, and 260, paragraphs 24 and 32)(Official notice is given that control and status registers can be implemented as MSRs for the advantage of implementing ISA specific controls. Thus, it would have been obvious to one of ordinary skill in the art to implement MSRs in Huntley.).
As per claim 10:
Huntley disclosed the apparatus of claim 1, wherein the opcode for the instance of the single instruction is different than an opcode for a legacy variant of the instance of the single instruction (Huntley: Figures 1-2 elements 110, 114, 200, 233-234, and 238, paragraphs 20, 27-28, and 30)(The instruction format includes an opcode. Official notice is given that legacy instructions have different opcodes than newly added instructions for the advantage of providing newer functionality to a processor. Thus, it would have been obvious to one of ordinary skill in the art that the SLDT, STR, and LSL instructions would have different opcodes than a legacy variant.).
As per claim 11:
Claim 11 essentially recites the same limitations of claim 1. Claim 11 additionally recites the following limitations:
memory to store an instance of a single instruction (Huntley: Figure 1 elements 112 and 120, paragraphs 15-16 and 19).
As per claim 12:
The additional limitation(s) of claim 12 basically recite the additional limitation(s) of claim 2. Therefore, claim 12 is rejected for the same reason(s) as claim 2.
As per claim 13:
The additional limitation(s) of claim 13 basically recite the additional limitation(s) of claim 3. Therefore, claim 13 is rejected for the same reason(s) as claim 3.
As per claim 14:
The additional limitation(s) of claim 14 basically recite the additional limitation(s) of claim 4. Therefore, claim 14 is rejected for the same reason(s) as claim 4.
As per claim 15:
The additional limitation(s) of claim 15 basically recite the additional limitation(s) of claim 5. Therefore, claim 15 is rejected for the same reason(s) as claim 5.
As per claim 16:
The additional limitation(s) of claim 16 basically recite the additional limitation(s) of claim 6. Therefore, claim 16 is rejected for the same reason(s) as claim 6.
As per claim 17:
The additional limitation(s) of claim 17 basically recite the additional limitation(s) of claim 7. Therefore, claim 17 is rejected for the same reason(s) as claim 7.
As per claim 18:
The additional limitation(s) of claim 18 basically recite the additional limitation(s) of claim 8. Therefore, claim 18 is rejected for the same reason(s) as claim 8.
As per claim 19:
The additional limitation(s) of claim 19 basically recite the additional limitation(s) of claim 9. Therefore, claim 19 is rejected for the same reason(s) as claim 9.
As per claim 20:
The additional limitation(s) of claim 20 basically recite the additional limitation(s) of claim 10. Therefore, claim 20 is rejected for the same reason(s) as claim 10.
As per claim 21:
Claim 21 essentially recites the same limitations of claim 1. Therefore, claim 21 is rejected for the same reasons as claim 1.
As per claim 22:
The additional limitation(s) of claim 22 basically recite the additional limitation(s) of claim 3. Therefore, claim 22 is rejected for the same reason(s) as claim 3.
As per claim 23:
The additional limitation(s) of claim 23 basically recite the additional limitation(s) of claim 4. Therefore, claim 23 is rejected for the same reason(s) as claim 4.
As per claim 24:
The additional limitation(s) of claim 24 basically recite the additional limitation(s) of claim 5. Therefore, claim 24 is rejected for the same reason(s) as claim 5.
As per claim 25:
The additional limitation(s) of claim 25 basically recite the additional limitation(s) of claim 6. Therefore, claim 25 is rejected for the same reason(s) as claim 6.
Response to Arguments
The arguments presented by Applicant in the response, received on 3/2/2026 are not considered persuasive.
Applicant argues for claims 1, 11, and 21:
“For example, Huntley, as cited, does not appear to describe "decoder circuitry to decode an instance of a single instruction, the instance of the single instruction to include at least one field for an opcode, one or more fields to identify a source operand which is to store a Load Segment Limit (LSL) selector value, and one or more fields to identify a destination register operand, wherein the opcode is to indicate that execution circuitry is to, when the single instruction has been enabled by a setting of a bit in a control register, write a LSL value stored in the control register to the destination operand when the LSL selector value of the source register operand matches a LSL selector value stored in the control register, and set a flag in a flags register." The Office has put forth a novel interpretation of claim with respect to a "contingent limitation" as the Office Action appears to be interpreting MPEP 2111 in a unique manner. The "contingent limitations" portion of this MPEP section is attempting to interpret Ex parte Schulhauser. The relevant portion of this PTAB opinion is as follows:
…
In Ex parte Schulhauser the claim used a means plus function limitation which is not present in the claim. Regardless, what the PTAB was noting is that the BRI is that a structure must be present in the art (and in the specification because of the use of means plus function), but not that the BRI does not include the function (which would, of course, be at odds with how the Patent Office, courts, etc. historically treat means plus function limitations).
Even with interesting interpretation, the claim language is "... wherein the opcode is to indicate that execution circuitry is to, when the single instruction has been enabled by a setting of a bit in a control register, write a LSL value stored in the control register to the destination operand when the LSL selector value of the first source register operand matches a LSL selector value stored in the control register." The Office Action asserts that the BRI for execution circuitry are control registers (the language used in the rejection is "i.e. structure for performing the function"). Applicant does not understand how a control register equates to execution circuitry to a PHOSITA. However, if the Office has evidence that this a proper interpretation, Applicant requests this evidence.”
This argument is not found to be persuasive for the following reason. The training slides the examiner has received mentions Ex parte Schulhauser including both process and product claims, where the product claims included “means for” language. The remaining slides of the training material for contingent limitations shows examples of product claims excluding means for language, yet still applying the same contingent limitation BRI.
In the instant application’s instance, claims 1 and 11 are product claims that includes contingent limitations (e.g. when the single instruction …, when the LSL selector value …) for which the BRI still requires the structure for performing the function whether or not the condition occurs. In this instance, the BRI requires control registers for instances when the single instruction hasn’t been enabled and when the LSL selector values in the source and control register don’t match. Huntley reads upon the BRI of these limitations by the inclusion of control registers within figure 2.
In the instant application’s instance, claim 21 is a process claim that includes contingent limitations (e.g. when the single instruction …, when the LSL selector value …) for which the BRI requires only those steps that must be performed and doesn’t include steps that are not required to be performed because the condition precedent is not met. In this instance, the BRI doesn’t require the contingent limitation steps when the condition isn’t met.
Thus, Huntley still reads upon the claimed limitations.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACOB PETRANEK/Primary Examiner, Art Unit 2183
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