DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/20/2026 has been entered. Claims 1-20 remain pending in this application.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-9 and 11-20 are rejected under 35 U.S.C. 101 because the claimed invention recites a judicial exception, is directed to that judicial exception, an abstract idea, as it has not been integrated into a practical application, and the claims do not recite significantly more than the judicial exception.
Step 1: Claims 1-9 are directed to a method and fall within the statutory category of processes; Claims 11-19 are direct to a hardware accelerator and fall within the statutory category of machines; Claim 20 is directed to a computer-readable medium and falls within the statutory category of articles of manufacture. Therefore, “Are the claims directed to a process, machine, manufacture, or composition of matter?” Yes.
Step 2A Prong 1: Claims 1, 11, and 20 have limitations of “scheduling, by a scheduler, divisions of the resources to the respective virtual functions based on the measured total of execution time of each respective virtual function” and “allocating the divisions of the resources to the respective virtual functions according to the schedule.” These aforementioned limitations are a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, can be performed by the mind. For example, a person can think and observe, judge and evaluate where resources should be assigned based on execution time.
Therefore, “Are the claims directed to a law of nature, a natural phenomenon, or an abstract idea?” Yes, claims 1, 11, and 20 recite abstract ideas.
Step 2A Prong 2: In claims 1, 11, and 20, the judicial exception is not integrated into a practical application. In particular, claims 1, 11, and 20 recite the following additional elements – “at least one processor” and “a scheduler.” Claims 11 and 20 also recite “a non-transitory computer-readable medium.” These aforementioned additional limitations generally link the use of the judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)) and do not integrate the judicial exception into a practical application. Additionally, claims 1, 11, and 20 recite “measuring, for virtual functions, a total of execution time of each respective virtual function, wherein during the measured total of execution time, each respective virtual function uses at least some resources from a hardware accelerator” and “receiving a plurality of submissions from the respective virtual functions requesting the at least some resources from the hardware accelerator” which are merely data gathering, a category of insignificant extra-solution activity (see MPEP § 2106.05(g)) and do not integrate the judicial exception into a practical application and will be further addressed as well-understood, routine, and conventional below.
Therefore, “Do the claims recite additional elements that integrate the judicial exception into a practical application?” No, these additional elements do not integrate the abstract idea into a practical application.
Step 2B: Claims 1, 11, and 20 do not include elements, alone or in combination, that are sufficient to amount to significantly more than the judicial exception. As discussed above in Step 2A Prong 2, the additional elements generally link the use of the judicial exception to a particular technological environment or field of use, which do not amount to significantly more than the abstract idea. Furthermore, the insignificant extra-solution activity is well-understood, routine, and conventional (see MPEP § 2106.05(d)(II)). “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: i. Receiving or transmitting data over a network. ii. Performing repetitive calculations.” In the case of the instant application, measuring a total execution time for a virtual function, by a generic computing component, is merely a data gathering step similar to performing repetitive calculations which the courts have identified as well-understood, routine, and conventional. Furthermore, receiving a plurality of submissions from virtual functions, by a generic computing component, is merely a data gathering step similar to receiving data over a network which the courts have identified as well-understood, routine, and conventional.
Therefore, “Do the claims recite additional elements that amount to significantly more than the judicial exception?” No, these additional elements, alone or in combination, do not amount to significantly more than the judicial exception.
Therefore, claims 1, 11, and 20 do not recite patent eligible subject matter under 35 U.S.C. § 101.
As per claims 2 and 12, they recite an additional element of “scheduling a first submission from a first virtual function based on the first virtual function having a lowest total actual execution time slice among the respective virtual functions.” This aforementioned limitation generally links the use of the judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)) and does not integrate the judicial exception into a practical application. Claims 2 and 12 do not recite any additional elements. Thus, the claims fail Step 2A Prong 2 and do not integrate the judicial exception into a practical application as well as fail Step 2B and do not amount to significantly more.
Therefore, claims 2 and 12 do not recite patent eligible subject matter under 35 U.S.C. § 101.
As per claims 3 and 13, they recite an additional element of “scheduling a first submission from a first virtual function based on both the first virtual function having a smallest actual incremental time slice and a remainder of the virtual functions having the same measured total of execution time.” This aforementioned limitation generally links the use of the judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)) and does not integrate the judicial exception into a practical application. Claims 3 and 13 do not recite any additional elements. Thus, the claims fail Step 2A Prong 2 and do not integrate the judicial exception into a practical application as well as fail Step 2B and do not amount to significantly more.
Therefore, claims 3 and 13 do not recite patent eligible subject matter under 35 U.S.C. § 101.
As per claims 4 and 14, they recite an additional element of “scheduling a first submission from a first virtual function based on both the first virtual function having been scheduled first and based on a remainder of the virtual functions having the same measured total of execution time and having the same detected incremental time slice.” This aforementioned limitation generally links the use of the judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)) and does not integrate the judicial exception into a practical application. Claims 4 and 14 do not recite any additional elements. Thus, the claims fail Step 2A Prong 2 and do not integrate the judicial exception into a practical application as well as fail Step 2B and do not amount to significantly more.
Therefore, claims 4 and 14 do not recite patent eligible subject matter under 35 U.S.C. § 101.
As per claims 5 and 15, they recite an additional element of “wherein an actual incremental time slice for a first virtual function is ascertained by a hardware or firmware component” which is merely data gathering, a category of insignificant extra-solution activity (see MPEP § 2106.05(g)) and does not integrate the judicial exception into a practical application and is further well-understood, routine, and conventional. “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: iii. Electronic recordkeeping.” In the case of the instant application, ascertaining an actual incremental time slice is merely a data gathering step similar to electronic recordkeeping which the courts have identified as well-understood, routine, and conventional. Claims 5 and 15 do not recite any additional elements. Thus, the claims fail Step 2A Prong 2 and do not integrate the judicial exception into a practical application as well as fail Step 2B and do not amount to significantly more.
Therefore, claims 5 and 15 do not recite patent eligible subject matter under 35 U.S.C. § 101.
As per claims 6 and 16, they recite an additional element of “wherein the hardware or firmware component reports the actual incremental time slice to the scheduler” which is merely data gathering, a category of insignificant extra-solution activity (see MPEP § 2106.05(g)) and does not integrate the judicial exception into a practical application and is further well-understood, routine, and conventional. “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: iii. Electronic recordkeeping.” In the case of the instant application, reporting an actual incremental time slice is merely a data gathering step similar to electronic recordkeeping which the courts have identified as well-understood, routine, and conventional. Claims 6 and 16 do not recite any additional elements. Thus, the claims fail Step 2A Prong 2 and do not integrate the judicial exception into a practical application as well as fail Step 2B and do not amount to significantly more.
Therefore, claims 6 and 16 do not recite patent eligible subject matter under 35 U.S.C. § 101.
As per claims 7 and 17, they recite an additional element of “wherein the actual incremental time slice for the first virtual function deviates from a designated incremental time slice that was previously assigned to the first virtual function.” This aforementioned limitation generally links the use of the judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)) and does not integrate the judicial exception into a practical application. Claims 7 and 17 do not recite any additional elements. Thus, the claims fail Step 2A Prong 2 and do not integrate the judicial exception into a practical application as well as fail Step 2B and do not amount to significantly more.
Therefore, claims 7 and 17 do not recite patent eligible subject matter under 35 U.S.C. § 101.
As per claims 8 and 18, they recite an additional element of “wherein the actual incremental time slice deviating from the designated incremental time slice causes the hardware accelerator to idle.” This aforementioned limitation generally links the use of the judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)) and does not integrate the judicial exception into a practical application. Claims 8 and 18 do not recite any additional elements. Thus, the claims fail Step 2A Prong 2 and do not integrate the judicial exception into a practical application as well as fail Step 2B and do not amount to significantly more.
Therefore, claims 8 and 18 do not recite patent eligible subject matter under 35 U.S.C. § 101.
As per claims 9 and 19, they recite an additional element of “wherein the scheduler schedules a frequency of granting a division of the resources to a first virtual function based on a size of a respective submission from the first virtual function.” This aforementioned limitation generally links the use of the judicial exception to a particular technological environment or field of use (see MPEP § 2106.05(h)) and does not integrate the judicial exception into a practical application. Claims 9 and 19 do not recite any additional elements. Thus, the claims fail Step 2A Prong 2 and do not integrate the judicial exception into a practical application as well as fail Step 2B and do not amount to significantly more.
Therefore, claims 9 and 19 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 11, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (US Patent No. 10,459,751 B2 hereinafter Jiang) in view of Haghighat et al. (US Pub. No. 2021/0263779 A1 hereinafter Haghighat).
As per claim 1, Jiang teaches a computer-implemented method for scheduling virtual functions (see Abstract), at least a portion of the method being performed by a computing device comprising at least one processor (Col. 3 & 4, lines 63-67 & 1-16, “As described above, physical functions and virtual functions are addressing parameters in PCIe, where transactions made across PCIe specify or are intended for a particular virtual function and/or physical function and the processor 102 or APD 116 responds accordingly (note, some ways of addressing over PCIe do not explicitly specify a virtual function or physical function; for example, transactions over PCIe can be routed by memory address instead of explicitly by function, where the devices implicitly understand which function is associated with a particular memory address). The processor 102 directs transactions for a particular VM to the appropriate virtual function of the APD 116 via a memory mapping mechanism.”), the method comprising: receiving a plurality of submissions from the respective virtual functions requesting at least some resources from the hardware accelerator (Col. 3, lines 4-49, “The processor 102 is configured to support a virtualizations scheme in which multiple virtual machines execute on the processor 102. Each virtual machine (“VM”) “appears” to software executing in that VM as a completely “real” hardware computer system, but in reality comprises a virtualized computing environment that may be sharing the device 100 with other virtual machines. Virtualization may be supported fully in software, partially in hardware and partially in software, or fully in hardware. The APD 116 supports virtualization, meaning that the APD 116 can be shared among multiple virtual machines executing on the processor 102, with each VM “believing” that the VM has full ownership of a real hardware APD 116. For virtualization, VMs take turns executing on the processor 102…The APD 116 supports virtualization by allowing time-based sharing of the APD 116 between the virtual machines. On the APD 116, the host VM 202 is mapped to a physical function 208 and guest VMs 204 are mapped to virtual functions 210.” See also Fig. 2.), scheduling, by a scheduler, divisions of the resources to the respective virtual functions based on an execution time of each respective virtual function (Col. 4, lines 17-46, “Sharing the APD 116 among the different virtual machines is accomplished by time-dividing the operations of the APD 116 amongst the different virtual machines. A virtualization scheduler 212 performs this task, scheduling different virtual machines for operation by switching between work for the different virtual machines as the execution time assigned to the virtual machines elapse…In other words, this disclosure may use terminology such as “the virtual function performs a task,” (or physical function) or “an operation is performed on of for a virtual function,” (or physical function) and this terminology should be read to mean that the APD 116 performs that task for the time-slice assigned to the VM associated with that particular virtual or physical function, or on behalf of the VM associated with that virtual or physical function.” Col. 6 & 7, lines 57-67 & 1-3, “The virtualization scheduler 212 manages time-sharing of the APD 116 among the different virtual machines. In each time-slice, the virtualization scheduler 212 permits work for the virtual machine associated with that time-slice to proceed in the APD 116.) and allocating the divisions of the resources to the respective virtual functions according to the schedule (Col. 7, lines 4-23, “Virtualization on the APD 116 works as follows. The virtualization scheduler 212 manages time-slices on the APD 116 for the VMs (both the host VM 202 and the guest VMS 204) that share the APD 116. The virtualization scheduler 212 tracks the time-slices, stopping work on the APD 116 when a time-slice for a particular VM has expired and starting work for the VM having the next time-slice. Thus, the virtualization scheduler 212 switches between different VMs that have work to be executed on the APD 116. To begin work for a particular time-slice associated with a particular VM, the virtualization scheduler 212 selects a virtual function associated with that VM to run and causes the command processor 213 to begin running for that VM.”).
Although Jiang teaches scheduling resources for use by virtual functions based on execution time, Jiang fails to teach measuring an execution time for each respective virtual function and scheduling based on the measured execution time.
However, Haghighat teaches measuring, for virtual functions, a total of execution time of each respective virtual function (¶ [0150], “The environment in which a Function's code is executed is referred to as a container. The container may be any isolated-execution entity such as a process, a Docker or Kubernetes container, a virtual machine, etc.” ¶ [0411], “In some embodiments, historical information such as that gathered from various telemetry sources (e.g. timers that timed previous function executions), may be used to estimate the execution time for each function, which may help to inform scheduling of future invocations of the functions.” ¶ [0668], “The orchestrator 2443 receives a function and decides how to route it to be executed. In some embodiments, when a function gets executed, information may be collected about behavior of the function (e.g., cache misses, timing to execute, etc.) by the orchestrator 2443. Some embodiments may use many counters to collect program information, and/or the function may be instrumented to collect data (e.g., and/or a timer may be used to collect information).”), wherein during the measured total of execution time, each respective virtual function uses at least some resources from a hardware accelerator (¶ [0155], “In the illustrated example, one or more central processing units (CPUs) 308a-308n (e.g., host processor) uses a FaaS executor 310 to execute a first set of functions 312, one or more accelerators 314a-314n (e.g., fixed-functionality hardware logic) executes a second set of functions 316, one or more field programmable gate arrays (FPGAs) 318a-318n executes a third set of functions 320 and one or more graphics processing units (GPUs) 318a-318n executes a fourth set of functions 326. Accordingly, the illustrated FaaS server configuration 300 is powered by specialized silicon, including GPUs 322a-322n, FPGAs 318a-318n, and specialized accelerators 314a-314n.”) and scheduling respective virtual functions based on the measured total of execution time (¶ [0472], “The orchestrator 1704 may determine the resource requirement based on available measures of dynamic utilization of resources. In some embodiments, historical information such as that gathered from various telemetry sources, e.g. from timers, function or debug logs, and performance monitors, may be used to estimate the execution time and/or resource requirements for each function, which may then be used to inform scheduling of future invocations of functions.”).
Jiang and Haghighat are considered to be analogous to the claimed invention because they are in the same field of task scheduling and resource allocation. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the scheduling method of Jiang with the well-known technique of allocating resources based on measured total execution time as taught by Haghighat to arrive at the claimed invention. This modification would have been reasonable under MPEP § 2143 as both references schedule tasks on resources taking into account task execution times.
As per claim 11, it is a machine claim comprising similar limitations to claim 1, so it is rejected for similar reasons. Furthermore, Jiang teaches a physical processor (Col. 3 & 4, lines 63-67 & 1-16, “As described above, physical functions and virtual functions are addressing parameters in PCIe, where transactions made across PCIe specify or are intended for a particular virtual function and/or physical function and the processor 102 or APD 116 responds accordingly (note, some ways of addressing over PCIe do not explicitly specify a virtual function or physical function; for example, transactions over PCIe can be routed by memory address instead of explicitly by function, where the devices implicitly understand which function is associated with a particular memory address). The processor 102 directs transactions for a particular VM to the appropriate virtual function of the APD 116 via a memory mapping mechanism.”), a non-transitory computer-readable memory storing instructions (Col. 12, lines 32-42, “The methods or flow charts provided herein can be implemented in a computer program, software, or firmware incorporated in a non-transitory computer-readable storage medium for execution by a general purpose computer or a processor.”), and resources of a hardware accelerator (Col. 1, lines 36-52, “The virtualized device includes a hardware accelerator and a microcontroller that executes firmware. The virtualized device is virtualized in that the virtualized device performs work for different virtual functions (with different virtual functions associated with different virtual machines), each function getting a “time-slice” during which work is performed for that function.).
As per claim 20, it is a product claim comprising similar limitations to claim 1, so it is rejected for similar reasons. Jiang also teaches a non-transitory computer-readable medium comprising one or more computer-executable instructions (Col. 12, lines 32-42, “The methods or flow charts provided herein can be implemented in a computer program, software, or firmware incorporated in a non-transitory computer-readable storage medium for execution by a general purpose computer or a processor.”).
Claim(s) 2 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang and Haghighat as applied to claims 1 and 11 above, and further in view of Booman et al. (US Pub. No. 2016/0092275 A1 hereinafter Booman).
As per claim 2, Jiang and Haghighat teach the method of claim 1. Jiang teaches scheduling a first submission from a first virtual function (Col. 7, lines 4-12, “Virtualization on the APD 116 works as follows. The virtualization scheduler 212 manages time-slices on the APD 116 for the VMs (both the host VM 202 and the guest VMS 204) that share the APD 116. The virtualization scheduler 212 tracks the time-slices, stopping work on the APD 116 when a time-slice for a particular VM has expired and starting work for the VM having the next time-slice.”).
Jiang and Haghighat fail to teach scheduling a first submission based on the first submission having the lowest execution time among the plurality of submissions.
However, Booman teaches scheduling a first submission based on the first submission having a lowest total execution time slice among the respective submissions (¶ [0025], “In embodiments, the system could utilize a shortest job first (SJF) protocol where the system executes jobs based on the execution-time parameter for each job. For example, the system operating under the SJF protocol can receive a set of jobs and begin executing those jobs in order of ascending of the execution-time parameter for those jobs.”).
Jiang, Haghighat, and Booman are all considered to be analogous to the claimed invention because they are all in the same field of task scheduling. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the virtual function scheduling method of Jiang and Haghighat with the shortest job first protocol of Booman to arrive at the claimed invention. The motivation to modify Jiang and Haghighat with the teachings of Booman is that employing a shortest job first protocol avoids the potential for critical jobs with a short execution time having to wait behind jobs with long execution times before being able to process.
As per claim 12, it is a machine claim comprising similar limitations to claim 2, so it is rejected for similar reasons.
Claim(s) 3-4 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang and Haghighat as applied to claims 1 and 11 above, in view of Booman and further in view of Lee et al. (US Pub. No. 2023/0071976 A1 hereinafter Lee).
As per claim 3, Jiang and Haghighat teach the method of claim 1. Jiang teaches scheduling a first submission from a first virtual function (Col. 7, lines 4-12, “Virtualization on the APD 116 works as follows. The virtualization scheduler 212 manages time-slices on the APD 116 for the VMs (both the host VM 202 and the guest VMS 204) that share the APD 116. The virtualization scheduler 212 tracks the time-slices, stopping work on the APD 116 when a time-slice for a particular VM has expired and starting work for the VM having the next time-slice.”). Haghighat teaches measured total execution time (¶ [0411], “In some embodiments, historical information such as that gathered from various telemetry sources (e.g. timers that timed previous function executions), may be used to estimate the execution time for each function, which may help to inform scheduling of future invocations of the functions.” ¶ [0668], “The orchestrator 2443 receives a function and decides how to route it to be executed. In some embodiments, when a function gets executed, information may be collected about behavior of the function (e.g., cache misses, timing to execute, etc.) by the orchestrator 2443. Some embodiments may use many counters to collect program information, and/or the function may be instrumented to collect data (e.g., and/or a timer may be used to collect information).”).
Jiang and Haghighat fail to teach scheduling a first virtual function based on the first virtual function having a smallest actual time slice and the remaining virtual functions having the same total actual execution time.
However, Booman teaches based on both the first submission having a smallest actual incremental time slice and a remainder of the submissions having the same total execution time (¶ [0029], “Some users could adopt an opinion that preferences are satisfied by a system that executes jobs based on the execution-time parameter, i.e. using the SJF protocol as described herein. For example, when many of the jobs are small jobs, executing jobs according to the execution-time parameter could quickly finish execution those small jobs so that they do not need to wait for longer jobs to be finished.”).
Jiang, Haghighat, and Booman are all considered to be analogous to the claimed invention because they are all in the same field of task scheduling. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the virtual function scheduling method of Jiang and Haghighat with the shortest job first protocol of Booman to arrive at the claimed invention. The motivation to modify Jiang and Haghighat with the teachings of Booman is that employing a shortest job first protocol avoids the potential for critical jobs with a short execution time having to wait behind jobs with long execution times before being able to process.
Jiang, Haghighat, and Booman do not explicitly teach taking into account incremental time slice when scheduling virtual functions.
However, Lee teaches incremental time slices (¶ [0044], “When the virtual functions 202, 204 and 206 of the virtual network function application 200 are actually executed on a virtual platform 400, the monitoring unit 10 monitors and collects actual value of each performance indicator of each of the virtual functions 202, 204 and 206. For the actual value of the execution time T_02 of the virtual function 202, the minimum is 55 µs, the mean is 103 µs, and the maximum is 205 µs. For the actual value of the execution time T_04 of the virtual function 204, the minimum is 27 µs, the mean is 49 µs, and the maximum is 130 µs. For the actual value of the execution time T_06 of the virtual function 206, the minimum is 110 µs, the mean is 135 µs, and the maximum is 270 µs.” The smallest incremental time slice could be calculated several ways. For example, it could be the difference between the minimum execution time and the maximum execution time.; see also 0057-0063).
Jiang, Haghighat, Booman, and Lee are all considered to be analogous to the claimed invention because they are all in the same field of task scheduling. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method for scheduling virtual functions of Jiang, Haghighat, and Booman with the incremental time slice data of Lee to arrive at the claimed invention. The motivation to modify Jiang, Haghighat, and Booman with the teachings of Lee is that scheduling virtual functions based on the smallest incremental time slice avoids pending virtual functions being stuck behind an executing virtual function that is taking abnormally long.
As per claim 4, Jiang and Haghighat teach the method of claim 1. Jiang teaches scheduling a first submission from a first virtual function (Col. 7, lines 4-12, “Virtualization on the APD 116 works as follows. The virtualization scheduler 212 manages time-slices on the APD 116 for the VMs (both the host VM 202 and the guest VMS 204) that share the APD 116. The virtualization scheduler 212 tracks the time-slices, stopping work on the APD 116 when a time-slice for a particular VM has expired and starting work for the VM having the next time-slice.”). Haghighat teaches measured total execution time (¶ [0411], “In some embodiments, historical information such as that gathered from various telemetry sources (e.g. timers that timed previous function executions), may be used to estimate the execution time for each function, which may help to inform scheduling of future invocations of the functions.” ¶ [0668], “The orchestrator 2443 receives a function and decides how to route it to be executed. In some embodiments, when a function gets executed, information may be collected about behavior of the function (e.g., cache misses, timing to execute, etc.) by the orchestrator 2443. Some embodiments may use many counters to collect program information, and/or the function may be instrumented to collect data (e.g., and/or a timer may be used to collect information).”). Booman teaches based on the first submission being scheduled first (¶ [0024], “In embodiments, the system could utilize a first-in-first-out (FIFO) protocol where the system executes jobs in order based on a queue-time parameter, which represents how long each job has been waiting to be executed.”) and based on a remainder of the submissions having the same total execution time and having the same detected incremental time slice (¶ [0026], “In certain embodiments, the system could utilize a relative latency (RL) protocol where the system executes jobs based on a ratio of the queue-time parameter to the execution-time parameter for each job.” ¶ [0031], “Some users could adopt an opinion that preferences are satisfied by a system that executes jobs based on the RL protocol as described herein. For example, jobs in the system have a number of large jobs and small jobs, the RL protocol can strike a balance between the FIFO protocol and SJF protocol by accounting for both queue-time and execution-time in the scheduling of jobs.”). Lee teaches incremental time slices (¶ [0044], “When the virtual functions 202, 204 and 206 of the virtual network function application 200 are actually executed on a virtual platform 400, the monitoring unit 10 monitors and collects actual value of each performance indicator of each of the virtual functions 202, 204 and 206. For the actual value of the execution time T_02 of the virtual function 202, the minimum is 55 µs, the mean is 103 µs, and the maximum is 205 µs. For the actual value of the execution time T_04 of the virtual function 204, the minimum is 27 µs, the mean is 49 µs, and the maximum is 130 µs. For the actual value of the execution time T_06 of the virtual function 206, the minimum is 110 µs, the mean is 135 µs, and the maximum is 270 µs.” The smallest incremental time slice could be calculated several ways. For example, it could be the difference between the minimum execution time and the maximum execution time.; see also 0057-0063).
See claim 3 for the motivation to combine.
As per claim 13, it is a machine claim comprising similar limitations to claim 3, so it is rejected for similar reasons.
As per claim 14, it is a machine claim comprising similar limitations to claim 4, so it is rejected for similar reasons.
Claim(s) 5-7, 10, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang and Haghighat as applied to claims 1 and 11 above, and further in view of Lee.
As per claim 5, Jiang and Haghighat teach the method of claim 1.
Jiang and Haghighat fail to teach an incremental time slice for a virtual function being ascertained by a hardware or firmware component.
However, Lee teaches wherein an actual incremental time slice for a first virtual function is ascertained by a hardware or firmware component (¶ [0044], “When the virtual functions 202, 204 and 206 of the virtual network function application 200 are actually executed on a virtual platform 400, the monitoring unit 10 monitors and collects actual value of each performance indicator of each of the virtual functions 202, 204 and 206. For the actual value of the execution time T_02 of the virtual function 202, the minimum is 55 µs, the mean is 103 µs, and the maximum is 205 µs. For the actual value of the execution time T_04 of the virtual function 204, the minimum is 27 µs, the mean is 49 µs, and the maximum is 130 µs. For the actual value of the execution time T_06 of the virtual function 206, the minimum is 110 µs, the mean is 135 µs, and the maximum is 270 µs.”).
Jiang, Haghighat, and Lee are all considered to be analogous to the claimed invention because they are all in the same field of task scheduling. Therefore, it would have been obvious to one of ordinary skill the art before the effective filing date of the claimed invention to modify the method for scheduling virtual functions of Jiang and Haghighat with the incremental time slice recording functionality of Lee to arrive at the claimed invention. The motivation to modify Jiang and Haghighat with the teachings of Lee is that recording the execution times of various virtual functions allows the system to dynamically reschedule the virtual functions based on the recorded execution times or reconfigure the resources allocated to the virtual functions based on the recorded execution times.
As per claim 6, Jiang, Haghighat, and Lee teach the method of claim 5. Jiang teaches the scheduler (Col. 7, lines 4-23, “The virtualization scheduler 212 manages time-slices on the APD 116 for the VMs (both the host VM 202 and the guest VMS 204) that share the APD 116. The virtualization scheduler 212 tracks the time-slices, stopping work on the APD 116 when a time-slice for a particular VM has expired and starting work for the VM having the next time-slice.”). Lee teaches wherein the hardware or firmware component reports the actual incremental time slice to a performance analysis unit and a resource adjusting unit (¶ [0047]-[0048], “To summarize, the monitoring unit 104 may monitor and record actual value of each performance indicator (such as “execution time”, “queue length”, “execution frequency”, or “error rate”) of each of the virtual functions 202, 204 and 206 of the virtual network function application 200 (target virtual network function application)…the performance analysis unit 106 may compare actual value of each performance indicator of each of the virtual functions 202, 204 and 206 of the virtual network function application 200 and actual value of each performance indicator of each physical resource and/or each virtual resource on the virtual platform 400 with associated expected value and/or threshold value…Then, the resource adjusting unit 108 may adjust service of the virtual network function application 200 or the virtual functions 202, 204 and 206, adjust the virtual resources allocated to the virtual network function application 200 and/or other virtual network function applications 230 and 260, or expand the physical resources on the virtual platform 400.”; see also 0057-0063).
As per claim 7, Jiang, Haghighat, and Lee teach the method of claim 5, Lee teaches wherein the actual incremental time slice for the first virtual function deviates from a designated incremental time slice that was previously assigned to the first virtual function (¶ [0060], “Refer to FIG. 7. In step 614 of the present embodiment 700, based on the comparison result between the actual value of each performance indicator and the expected value and/or threshold value which shows that the actual value of the performance indicator “execution time” is far greater than the expected value (referring to Table 5: the mean and maximum of the actual values of execution time T_04 of the virtual function 204 that is, 238 us and 2530 us respectively, are far greater than the mean and maximum of the expected values of the execution time T_04, that is, 50 us and 150 us, as listed in Table 1)…; see also 0057-0063).
As per claim 10, Jiang and Haghighat teach the method of claim 1. Jiang teaches the scheduler (Col. 7, lines 4-23, “The virtualization scheduler 212 manages time-slices on the APD 116 for the VMs (both the host VM 202 and the guest VMS 204) that share the APD 116. The virtualization scheduler 212 tracks the time-slices, stopping work on the APD 116 when a time-slice for a particular VM has expired and starting work for the VM having the next time-slice.”). Haghighat teaches measured total execution time (¶ [0411], “In some embodiments, historical information such as that gathered from various telemetry sources (e.g. timers that timed previous function executions), may be used to estimate the execution time for each function, which may help to inform scheduling of future invocations of the functions.” ¶ [0668], “The orchestrator 2443 receives a function and decides how to route it to be executed. In some embodiments, when a function gets executed, information may be collected about behavior of the function (e.g., cache misses, timing to execute, etc.) by the orchestrator 2443. Some embodiments may use many counters to collect program information, and/or the function may be instrumented to collect data (e.g., and/or a timer may be used to collect information).”).
Jiang and Haghighat fail to teach updating the total actual execution time for each virtual function until a condition is met.
However, Lee teaches iteratively execute, during a cycle of the hardware accelerator, a function that updates the measured total of execution time of each respective virtual function (¶ [0044], “When the virtual functions 202, 204 and 206 of the virtual network function application 200 are actually executed on a virtual platform 400, the monitoring unit 10 monitors and collects actual value of each performance indicator of each of the virtual functions 202, 204 and 206.”) until a condition is met (¶ [0060], “Refer to FIG. 7. In step 614 of the present embodiment 700, based on the comparison result between the actual value of each performance indicator and the expected value and/or threshold value which shows that the actual value of the performance indicator “execution time” is far greater than the expected value (referring to Table 5: the mean and maximum of the actual values of execution time T_04 of the virtual function 204 that is, 238 µs and 2530 µs respectively, are far greater than the mean and maximum of the expected values of the execution time T_04, that is, 50 µs and 150 µs, as listed in Table 1), the performance analysis unit 106 determines that the virtual function 204 has abnormalities, and the virtual function 204 is located as the bottleneck which deteriorates system performance.” ; see also 0057-0063)
Jiang, Haghighat, and Lee are all considered to be analogous to the claimed invention because they are all in the same field of task scheduling. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the scheduler of Jiang and Haghighat to perform the monitoring unit functionalities of Lee to arrive at the claimed invention. The motivation to modify Jiang and Haghighat with the teachings of Lee is that recording the execution times of the virtual functions allows the system to dynamically reschedule the virtual functions based on the recorded execution times or reconfigure the resources allocated to the virtual functions based on the recorded execution times.
As per claim 15, it is a machine claim comprising similar limitations to claim 5, so it is rejected for similar reasons.
As per claim 16, it is a machine claim comprising similar limitations to claim 6, so it is rejected for similar reasons.
As per claim 17, it is a machine claim comprising similar limitations to claim 7, so it is rejected for similar reasons.
Claim(s) 8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang, Haghighat, and Lee as applied to claims 7 and 17 above, and further in view of Fahrig et al. (US Pub. No. 2011/0099551 A1 hereinafter Fahrig).
As per claim 8, Jiang, Haghighat, and Lee teach the method of claim 7.
Jiang, Haghighat, and Lee fail to teach the hardware accelerator going idle if the time slice deviates.
However, Fahrig teaches wherein the actual incremental time slice deviating from the designated incremental time slice causes the hardware accelerator to idle (¶ [0063]-[0064], “While VP1 has acquired a lock on both LP1 and LP2, the scheduler may perform the back-end method for de-scheduling VP1 from LP2 after it has acquired a lock and has entered a spin wait. Initially, the back-end method calls for the scheduler to identify that VP1 has acquired a lock on LP2, and that LP2 is executing a thread issued by VP1 upon acquiring the lock. In further accordance with the back-end method, the scheduler may inspect LP2 to determine a duration of a spin wait. This spin-wait duration may be compared against a time threshold. In one instance, the time threshold represents a predefined number of the nonproductive loops (e.g., 4095 cycles) performed consecutively by the logical processor. In another instance, the time threshold is based on a predefined, static period of time. In yet another instance, the time threshold is dynamically tuned based on recorded behavior of the virtual processors, such as the pattern explained above. When the scheduler determines that the spin-wait duration does not meet the time threshold, it may allow the LP2 to continue attempting to execute the thread issued by VP1 at time slice 720. In contrast, when the scheduler determines that the spin-wait duration on LP2 exceeds the time threshold, VP1 is de-scheduled from LP2 for a predetermined time frame. In this way, the scheduler notices that no useful work is being performed on LP2 at the present time and allows other ready threads to be scheduled on the LP2 to improve overall system throughput.”).
Jiang, Haghighat, Lee, and Fahrig are considered to be analogous to the claimed invention because they are in the same field of task scheduling. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the scheduling method of Jiang, Haghighat, and Lee with the forced idling functionality of Fahrig to arrive at the claimed invention. The motivation to modify Jiang, Haghighat, and Lee with the teachings of Fahrig is that causing the hardware accelerator to idle if time slice deviation occurs improves overall system throughout as hardware resources are not wasted doing unnecessary work.
As per claim 18, it is a machine claim comprising similar limitation to claim 8, so it is rejected for similar reasons.
Claim(s) 9 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang and Haghighat as applied to claims 1 and 11 above, and further in view of Fahrig.
As per claim 9, Jiang and Haghighat teach the method of claim 1.
Jiang and Haghighat fail to teach allocating resources to virtual functions based on a size of the input of the virtual function.
However, Fahrig also teaches wherein the scheduler schedules a frequency of granting a division of the resources to a first virtual function based on a size of a respective submission from the first virtual function (¶ [0055], “When the scheduler determines that the LP3 is executing the critical section of code, the scheduler may grant VP1 a first time-slice extension 630 in order to facilitate LP3 completing the critical section before de-scheduling VP1. In an exemplary embodiment, the first time-slice extension 630 allocates LP3 to VP1 for a reduced duration of time in comparison to the predetermined duration of time associated with the initial time slice 620. By way of example, the initial time slice 620 may have a predetermined duration of 10 ms, while the time-slice extension 630 may have reduced duration of 100 mu.s. By reducing the duration of the time-slice extension 630, inequities between virtual processors attempting to access a particular logical processor are diminished. However, a length of the reduced duration of time associated with the time-slice extension 630 may be adjusted based upon a priority level attached to the thread, or based on a number of virtual processors within a virtual machine that are supported by a particular logical processor.”).
Jiang, Haghighat, and Fahrig are all considered to be analogous to the claimed invention because they are all in the same field of task scheduling and resource allocation. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the scheduling method of Jiang and Haghighat with the well-known technique of allocating resources based on submission size as taught by Haghighat to arrive at the claimed invention. This modification would have been reasonable under MPEP § 2143 as all references schedule tasks on resources taking into account task characteristics (e.g., task size or task execution time).
As per claim 19, it is a machine claim comprising similar limitations to claim 9, so it is rejected for similar reasons.
Response to Arguments
Applicant's arguments filed 2/20/2026 in regards to the 35 U.S.C. § 101 rejection have been fully considered but they are not persuasive. See 101 rejection above for reasons the claimed invention does not recite patent eligible subject matter. Applicant’s arguments in regards to the 35 U.S.C. § 103 rejection of claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant has amended the claims with new limitations that change the scope of the claimed invention. Therefore, the amended claims necessitate new rejections, as addressed above. The amended claims are not allowable over prior art cited previously along with an additional reference, necessitated by amendment, for reason indicated above.
Conclusion
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/J.D.E./Examiner, Art Unit 2199
/LEWIS A BULLOCK JR/Supervisory Patent Examiner, Art Unit 2199