Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings were received on August 13, 2025. These drawings are acceptable.
Specification
The abstract of the disclosure is objected to because the examiner is unclear which item number refers to the second reference input and to the third input. The Abstract states that the third input is 322, but the Specification paragraphs 0026 and 0029 state that the second reference input is 322. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Objections
The claims are objected to because they include reference characters which are not enclosed within parentheses.
Reference characters corresponding to elements recited in the detailed description of the drawings and used in conjunction with the recitation of the same element or group of elements in the claims should be enclosed within parentheses so as to avoid confusion with other numbers or characters which may appear in the claims. See MPEP § 608.01(m).
Claim 9 is objected to because of the following informalities: the end of the claim is missing a period. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6, 9, 10, 15 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the third input" in line 8. There is insufficient antecedent basis for this limitation in the claim.
Claim 1 recites "...the third input coupled to the second reference input and ..." in lines 8-9. As the abstract states that 322 is the third input and the specification paragraphs 0026 and 0029 state that 322 is the second reference input. The examiner is unclear how each input is called out as 322, as it appears that 322 is coupled to itself.
Claim 1 recites “…first reference input Vref1,…” in lines 14-15. Per specification paragraphs 0026-0027, the first reference input is 320, not Vref1. The examiner is unclear how the second input (388) of the second stage integrator (108) is coupled to first reference input (320).
Regarding Claim 6, as defined in Claim 1, the second feedback path is the output of the second stage integrator (392) coupled to the first input of the second stage integrator (386), which comprises a third feedback capacitor (C3) and a switch (Srst). The examiner is unclear how the second feedback capacitor (C2) is included in the second feedback path.
Claim 9 recites the limitation "the first reference" in line 12. There is insufficient antecedent basis for this limitation in the claim.
Regarding Claim 15 (lines 5-7), these lines are discussing the "plurality of first stage integrators" which the examiner assumes to be 106(1,1) and 106(2,1), then discusses "each first stage integrator", to state that, "…a second input coupled to the first reference input…". The second input in 106(1,1) is 326 which is coupled to the first reference input 320, but second input in 106(2,1) is 362 which is not coupled to the first reference input 320 but instead coupled to the third reference input 364. The examiner interprets, in light of the specification and the drawing, a second input is coupled to the first reference voltage (Vref1), not the first reference input.
Regarding Claim 15 (line 11), per specification paragraphs 0026-0027, the first reference input is 320. The examiner is unclear how the second input (388) of the second stage integrator (108) is coupled to first reference input (320).
Regarding Claims 2-6, 10, and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being depended on claims 1, 9, and 15, respectively.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 9-10 & 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Kalthoff et al. (WO 9845798), in view of Yuuji et al. (JP S58125177 A), hereinafter Kalthoff, in view of Yuuji.
Regarding Claim 1, as best understood, Kalthoff teaches a circuit (Fig. 3) having a plurality of circuit inputs (non-inverting and inverting of amplifiers 7-1 and 7-2), at least one of the plurality of circuit inputs adapted to receive an input current (Iin1), the circuit having a first reference input (17-1) adapted to receive a first reference voltage (gnd) and having a second reference input (input node at Vref) adapted to receive a second reference voltage (Vref), the circuit comprising: a plurality of first stage integrators (1 including 7-1, 7-3, 10-1, 10-3, 13-1, 13-3, Cint1, Cint3), each of the plurality of first stage integrators including a first input (inverting of 7-1 and 7-3), a second input (non-inverting of 7-1 and 7-3, and an output (output of 7-1 and 7-3), the first input of each of the plurality of first stage integrators coupled to a different one of the circuit inputs (node at 4 and 5 through switches 13-1 and 13-3, respectively), the third input (Kalthoff, Fig. 3, input Vref) coupled to the second reference input and the output of each of the plurality of first stage integrators coupled to the first input of such first stage integrator by a first feedback path (output of 7-1 through 10-1 and Cint1 to inverting of 7-1) for such first stage integrator. Kalthoff teaches all of the elements of the current invention as stated above except a second stage integrator including a first input, a second input and an output, the first input of the second stage integrator coupled to each of the first inputs of the plurality of first stage integrators, the second input of the second stage integrator coupled to the first reference input Vref1, and the output of the second stage integrator coupled to the first input of the second stage integrator by a second feedback path; wherein the second feedback path comprises: a switch SRST having a first terminal and a second terminal; and a third feedback capacitor having a first terminal and a second terminal wherein the first terminal of the switch SRST is coupled to the first terminal of the third feedback capacitor C3, and the second terminal of the switch SRST is coupled to the second terminal of the third feedback capacitor C3.
However, Yuuji teaches a second stage integrator (Fig. 3 including 36, 37, 38) including a first input (inverting of 36), a second input (non-inverting of 36) and an output (output of 36), the first input of the second stage integrator coupled to each of the first inputs of the plurality of first stage integrators (inverting of amplifier 30-1 and inverting of amplifier 31-2), the second input of the second stage integrator coupled to the first reference input Vref1 (gnd), and the output of the second stage integrator coupled to the first input of the second stage integrator by a second feedback path (output of 36 through 37 to inverting of 36); wherein the second feedback path comprises: a switch (38) having a first terminal (terminal of 38 connected to the inverting of 36) and a second terminal (terminal of 38 connected to the output of 36); and a third feedback capacitor (37) having a first terminal (terminal of 37 connected to the inverting of 36) and a second terminal (terminal of 37 connected to the output of 36) wherein the first terminal of the switch is coupled to the first terminal of the third feedback capacitor, and the second terminal of the switch is coupled to the second terminal of the third feedback capacitor.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kalthoff (Fig. 3, between item 1 & item 21) by incorporating the second stage integrator as taught by Yuuji (Fig. 3), for the purpose of refining the output voltage.
Regarding Claim 2, Kalthoff, in view of Yuuji , teaches the circuit of claim 1, further comprising a plurality of transfer switches (Yuuji, Fig. 3, 33-1 & 33-2), each of the plurality of transfer switches including a first terminal (Yuuji, Fig. 3, 33-1 terminal connected to inverting of amplifier 30-1 and 33-2 terminal connected to inverting of amplifier 31-2) and a second terminal (Yuuji, Fig. 3, 33-1 & 33-2 terminals connected to inverting of amplifier 36), the first terminal of each of the plurality of transfer switches coupled to a different one of the first inputs of the plurality of first stage integrators (Yuuji, Fig. 3, first terminal of 33-1 & 33-2 connected to the inverting of amplifiers 30-1 & 31.2, respectively) and the second terminal of each of the plurality of transfer switches coupled to the first input of the second stage integrator.
Regarding Claim 3, Kalthoff, in view of Yuuji , teaches the circuit of claim 1, wherein the first feedback path comprises: a first switch (Kalthoff, Fig. 3, 10-1) including a first terminal coupled to the output of the first stage integrator (Kalthoff, Fig. 3, terminal of 10-1 connected to the output of 7-1) and including a second terminal (Kalthoff, Fig. 3, terminal of 10-1 connected to Cint1); and a first feedback capacitor C1 (Kalthoff, Fig. 3, Cint1) including a first terminal coupled to the first input of the first stage integrator (Kalthoff, Fig. 3, terminal of Cint1 connected to inverting of 7-1) and a second terminal coupled to the second terminal of the first switch (Kalthoff, Fig. 3, terminal of Cint1 connected to terminal of 10-1).
Regarding Claim 4, Kalthoff, in view of Yuuji, teaches the circuit of claim 3, wherein each of the plurality of first stage integrators further comprises a second switch (Kalthoff, Fig. 3, transfer switches 13-1 & 13-3) including a first terminal coupled to the second terminal of the first feedback capacitor C1 (Kalthoff, Fig. 3, terminal of 13-1 connected to Cint1 & terminal of 13-3 connected to Cint3) of such first stage integrator and a second terminal adapted to receive the second reference voltage (Kalthoff, Fig. 3, terminal of 13-1 connected to Vref & terminal of 13-3 connected to Vref).
Regarding Claim 5, Kalthoff, in view of Yuuji , teaches the circuit of claim 1, wherein each of the plurality of first stage integrators further comprises a transfer switch (Yuuji, Fig. 3, 33-1 & 33-2) including a first terminal coupled to the first input of such first stage integrator (Yuuji, Fig. 3, terminals of 33-1 & 33-2 connected to the inverting of amplifiers 30-1 & 31-2, respectively) and a second terminal coupled to the first input of the second stage integrator (Yuuji, Fig. 3, terminals of 33-1 & 33-2 connected to inverting of amplifier 36).
Regarding Claim 6, as best understood, Kalthoff, in view of Yuuji , teaches the circuit of claim 1, wherein the second feedback path includes a second feedback capacitor C2 (Yuuji, Fig. 3, 37) including a first terminal coupled to the first input of the second stage integrator (Yuuji, Fig. 3, terminal of 37 connected to the inverting of 36) and a second terminal coupled to the output of the second stage integrator (Yuuji, Fig. 3, terminal of 37 connected to the output of 36).
Regarding Claim 9, as best understood, Kalthoff teaches a circuit (Figure 3 with timing diagram Figure 4; CA1 (switch 10-1) is high initially with CDSA (switch 13-1)) having a circuit input (4) adapted to receive an input current (Iint1), the circuit having a first reference input (17-1) adapted to receive a first reference voltage (gnd) and having a second reference input (input node at Vref) adapted to receive a second reference voltage (Vref), the circuit comprising: a first stage integrator (1 including 7-1, 10-1, 13-1, Cint1) including a first input (inverting of 7-1) coupled to the circuit input, a second input (non-inverting of 7-1) coupled to the first reference input, and an output (output of 7-1) coupled to the first input of the first stage integrator via a first feedback path (output of 7-1 through 10-1 and Cint1 to inverting of 7-1); a transfer switch (6-2) including a first terminal (terminal connected to node 4) coupled to the first input of the first stage integrator and including a second terminal (terminal connected to the inverting of 7-2); and a second stage integrator (7-2) including a first input (inverting of 7-2) coupled to the second terminal of the transfer switch, a second input (non-inverting of 7-2) coupled to the first reference input, and an output (output of 7-2) coupled to the first input of the second stage integrator by a third feedback path (output of 7-2 through 10-2 and Cint2 to inverting of 7-2). Kalthoff teaches all of the elements of the current invention as stated above except wherein the third feedback path comprises: a switch SRST having a first terminal and a second terminal; and a third feedback capacitor having a first terminal and a second terminal wherein the first terminal of the switch SRST is coupled to the first terminal of the third feedback capacitor C3, and the second terminal of the switch SRST is coupled to the second terminal of the third feedback capacitor C3.
However, Yuuji teaches wherein the third feedback path (Fig. 3) comprises: a switch (38) having a first terminal (terminal of 38 connected to the inverting of 36) and a second terminal (terminal of 38 connected to the output of 36); and a third feedback capacitor (37) having a first terminal (terminal of 37 connected to the inverting of 36) and a second terminal (terminal of 37 connected to the output of 36) wherein the first terminal of the switch is coupled to the first terminal of the third feedback capacitor, and the second terminal of the switch is coupled to the second terminal of the third feedback capacitor.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kalthoff (Fig. 3, between item 1 & item 21) by incorporating the second stage integrator as taught by Yuuji (Fig. 3), for the purpose of refining the output voltage.
Regarding Claim 10, Kalthoff, in view of Yuuji , teaches the circuit of claim 9, wherein the first feedback path comprises: a first switch (Kalthoff, Fig. 3, 10-1) including a first terminal coupled to the output of the first stage integrator (Kalthoff, Fig. 3, terminal of 10-1 connected to the output of 10-1) and including a second terminal (Kalthoff, Fig. 3, terminal of 10-1 connected to Cint1); and a first feedback capacitor (Kalthoff, Fig. 3, Cint1) including a first terminal coupled to the first input of the first stage integrator (Kalthoff, Fig. 3, terminal of Cint1 connected to the inverting of 7-1) and a second terminal coupled to the second terminal of the first switch (Kalthoff, Fig. 3, terminal of Cint1 connected to the terminal of 10-1).
Regarding Claim 15, as best understood, Kalthoff teaches a circuit (Fig. 3) having a plurality of circuit inputs (non-inverting and inverting of amplifiers 7-1 and 7-2), at least one of the plurality of circuit inputs adapted to receive an input current (Iin1), the circuit having a first reference input (17-1) adapted to receive a first reference voltage (gnd) and having a second reference input (input node at Vref) adapted to receive a second reference voltage (Vref), the circuit comprising: a plurality of first stage integrators (1 including 7-1, 7-3, 10-1, 10-3, 13-1, 13-3, Cint1, Cint3), wherein each first stage integrator of the plurality of first stage integrators includes a first input (inverting of 7-1 & 7-3) coupled to a different one of the circuit inputs (node at 4 and 5 through switches 13-1 and 13-3, respectively), a second input (non-inverting of 7-1 & 7-3) coupled to the first reference input, and an output (output of 7-1 and 7-3) coupled to the first input of such first stage integrator by a first feedback path (output of 7-1 through 10-1 and Cint1 to the inverting of 7-1). Kalthoff teaches all of the elements of the current invention as stated above except a second stage integrator including a first input coupled to the first inputs of each of the plurality of first stage integrators, a second input coupled to the first reference input, and an output coupled to the first input of the second stage integrator by a second feedback path; wherein the second feedback path comprises: a switch SRST having a first terminal and a second terminal; and a third feedback capacitor having a first terminal and a second terminal wherein the first terminal of the switch SRST is coupled to the first terminal of the third feedback capacitor C3, and the second terminal of the switch SRST is coupled to the second terminal of the third feedback capacitor C3.
However, Yuuji teaches a second stage integrator (Fig. 3 including 36, 37, 38) including a first input (inverting of 36) coupled to the first inputs of each of the plurality of first stage integrators (inverting of amplifier 30-1 and inverting of amplifier 31-2), a second input (non-inverting of 36) coupled to the first reference input, and an output (output of 36) coupled to the first input of the second stage integrator by a second feedback path (output of 36 through 37 to inverting of 36); wherein the second feedback path comprises: a switch (38) having a first terminal (terminal of 38 connected to the inverting of 36) and a second terminal (terminal of 38 connected to the output of 36); and a third feedback capacitor (37) having a first terminal (terminal of 37 connected to the inverting of 36) and a second terminal (terminal of 37 connected to the output of 36) wherein the first terminal of the switch is coupled to the first terminal of the third feedback capacitor, and the second terminal of the switch is coupled to the second terminal of the third feedback capacitor.
It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kalthoff (Fig. 3, between item 1 & item 21) by incorporating the second stage integrator as taught by Yuuji (Fig. 3), for the purpose of refining the output voltage.
Regarding Claim 16, Kalthoff, in view of Yuuji , teaches the circuit of claim 15, wherein each of the plurality of first stage integrators further comprises a transfer switch (Kalthoff, Fig. 3, 6-2 & 6-4) including a first terminal coupled to the first input of such first stage integrator (Kalthoff, Fig. 3, terminal of 6-2 & 6-4 connected to the inverting of 7-1 & 7-3, respectively) and a second terminal coupled to the first input of the second stage integrator (Kalthoff, Fig. 3, terminal of 6-2 & 6-4 connected to the inverting of 7-2 & 7-4, respectively).
Response to Arguments
Applicant's arguments filed August 13, 2025 have been fully considered but they are not persuasive.
Regarding claims 1, 9 and 15, applicant argues that neither Kalthoff nor Yuuji either in combination or individually teach "a second feedback path with a switch having a first terminal and a second terminal and a capacitor having a first terminal and a second terminal wherein the first terminal of the switch SRST is coupled to the first terminal of the capacitor, and the second terminal of the switch is coupled to the second terminal of the third feedback capacitor C3". Examiner respectfully disagrees.
However, Yuuji (Fig. 3) discloses wherein the second/third feedback paths comprises: a switch (38) having a first terminal (terminal of 38 connected to the inverting of 36) and a second terminal (terminal of 38 connected to the output of 36); and a third feedback capacitor (37) having a first terminal (terminal of 37 connected to the inverting of 36) and a second terminal (terminal of 37 connected to the output of 36) wherein the first terminal of the switch is coupled to the first terminal of the third feedback capacitor, and the second terminal of the switch is coupled to the second terminal of the third feedback capacitor.
Therefore, Kalthoff, in view of Yuuji, still reads on the claims and the rejection stands.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Amit Bhatia whose telephone number is (571) 272-4410. The examiner can normally be reached Monday-Friday 8:30am-4:30pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lincoln Donovan can be reached at (571) 272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Amit R Bhatia/Examiner, Art Unit 2842
/LINCOLN D DONOVAN/Supervisory Patent Examiner, Art Unit 2842