Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 7, 2026 has been entered.
Status of Claims
Claims 1 and 3-20 are currently pending in this application in response to the amendment and remarks filed on 01/07/2026. Claims 1 and 8 are currently amended and claim 2 is canceled.
Response to Applicant’s Remarks
With respect to 35 U.S.C. §102 rejection:
Applicant’s amendments and remarks filed on January 7, 2026 have been fully considered and are persuasive. Upon further consideration, see a new ground(s) of rejection as follows.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3, 6-8, 10-12, and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Sood et al. (US 2016/0118988-A1) in view of Aradhyula et al. (US 2020/0278652).
With respect to claims 1 and 8, Sood teaches of an input/output ("I/O") module for a system (IC device of fig.1), the I/O module comprising:
a plurality of channel circuits (configurable logic element CLEs 109 with I/O modules 102, 116, and/or 118, figs.1-2); and
an electronic processor (control circuit 104, fig.1) communicatively coupled to each channel circuit via a dedicated hardware communication channel (control circuit 104 coupled to each CLEs via a dedicated circuit connection as shown in fig.1), wherein each channel circuit is electrically isolated from one another (each CLEs are isolated from one another via individual power control block 202 as disclosed in fig.1 and [0024]), the electronic processor configured to control a power state for at least one channel circuit included in the plurality of channel circuits (control the power-up or power-down state of each CLEs via a global control signal, fig.2 and [0024]) by generating and transmitting a control signal to the at least one channel circuit via a corresponding dedicated hardware communication channel communicatively coupling the electronic processor to the at least one channel circuit (Each power control block 202 of each CLEs receive the global control signal and each of the control block 202 send the control signal to each CLEs via individual signal line 208, to enable a staggered power-up or power-down of the CLEs, fig.2 and [0024], each CLEs having a dedicated signal line 208 coupling to the control circuit 104, figs.1-2).
With respect to claims 1 and 8, Sood does not appear to teach that the plurality of channel circuits are for interfacing with industrial control equipment of an industrial system.
However, it is known by Aradhyula et al. (US 2020/0278652) to also teach of a system for providing remote channel reset for an input/output (“I/O”) module of industrial system (I/O module 104 of industrial process control and automation system 100, fig.1 and fig.3), the system and the I/O module (fig.1 and fig.3) comprising: a plurality of channel circuits (first I/O circuitry 302 and second I/O circuitry 304 of I/O module 104, fig.3 and [0049]) for interfacing with industrial control equipment of an industrial system (to drive different electrical signals to multiple [equipment] devices 102a-102b, [0049], of industrial process control and automation system 100, fig.1).
Because Aradhyula’s teaching is also directed to input/output ("I/O") module for a system (Aradhyula: I/O module 104 of industrial process control and automation system 100, fig.1 and fig.3; Sood: IC device of fig.1), it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teaching of the I/O module for interfacing with industrial control equipment of an industrial system as taught by Aradhyula with the I/O module as taught by Sood for the purpose of communicating with the field devices over various I/O channels (Aradhyula: [0016]).
With respect to claims 3 and 12, Sood and Aradhyula combined teaches wherein the electronic processor is configured to control the power state of the at least one channel circuit by disabling power to the at least one channel circuit, wherein the at least one channel circuit is unused by the industrial system (Sood: Each power control block 202 of each CLEs receive the global control signal and each of the control block 202 send the control signal to each CLEs via individual signal line 208, to enable a staggered power-up or power-down of the CLEs, fig.2 and [0024], each CLEs having a dedicated signal line 208 coupling to the control circuit 104, figs.1-2); Aradhyula: Outputs from the comparators 320 can be provided to the DAC 318 and used to control the driving of the gates of the switches 306 and 308….the comparators 320 to be used to detect excessive voltages or currents being generated by the I/O circuitry 302 or 304 and to shut down the driving of the associated switch 306 or 308, [0048]).
With respect to claims 6 and 10, Sood and Aradhyula combined teaches wherein the electronic processor is configured to control the power state for the at least one channel circuit in response to receiving a remote request from a user device (Sood: a user-generated signal, such as a user control signal that may be generated by a circuit of the CLE for example, is provided in addition to the global control signal [0025]; Aradhyula: user…to configure DI and AI channels associated with a single I/O terminal of an I/O module…the I/O module 104 receiving information indicating that the user…are going to couple DI and AI field devices 102, 102a-102b to the same electrical conductor 114 coupled to an I/O terminal 205 of an I/O module 104, [0063]).
With respect to claim 7, Sood and Aradhyula combined teaches wherein the electronic processor is configured to control the power state for the at least one channel circuit in response to receiving a request automatically initiated by a ladder logic program associated with the I/O module (Sood: Complex Programmable Logic Device (CPLD). A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to that used in a Programmable Logic Array (PLA) or a Programmable Array Logic (PAL) device [0036]; Aradhyula: programmable logic controllers 106 associated with the I/O module 104…to control the aspects of the industrial process, fig. 3 and [0025]; the module controller 310 receiving a digital/analog value to be output to a field device from a controller 106… to activate or deactivate the switch 308 to achieve the desired digital/analog state and communicate a digital/analog output value, [0070 and 0077]).
With respect to claim 11, Sood and Aradhyula combined teaches wherein the electronic processor is configured to control the power state for the at least one channel circuit in response to receiving a request automatically initiated by an external logic program (Sood: communication signals external to the integrated circuit device {of fig.1} by way of an I/O port 116. Other I/O ports may be coupled to circuits of the integrated circuit device, such as I/O port 118 that is coupled to the control circuit 104 [0023]; Aradhyula: programmable logic controllers 106 is external to the I/O modules 104 to control the aspects of the industrial process, [0025, 0070, 0077]).
With respect to claim 15, Sood teaches a method for providing remote channel reset for input/output ("I/O") modules (IC device of fig.1), the method comprising:
providing a multichannel I/O module, the multichannel I/O module including a first channel circuit and a second channel circuit (IC device of fig.1 provided with multiple configurable logic element CLEs 109 with I/O modules 102, 116, and/or 118, figs.1-2), wherein the first channel circuit is controlled independently from the second channel circuit (each CLEs are independently controlled via individual power control block 202 as disclosed in fig.1 and [0024]), wherein the first channel circuit is electrically isolated from the second channel circuit (each CLEs are isolated from one another via individual power control block 202 as disclosed in fig.1 and [0024]); and
controlling, with an electronic processor communicatively coupled to the first channel circuit and the second channel circuit (control circuit 104 coupled to each CLEs via a dedicated circuit connection as shown in fig.1 and each CLEs are independently controlled via individual power control block 202 as disclosed in fig.1 and [0024]), a first power state associated with the first channel circuit via transmission of a first control signal using a first dedicated hardware communication channel communicatively coupling the electronic processor to the first channel circuit (Each power control block 202 of each CLEs receive the global control signal and each of the control block 202 send the control signal to each CLEs via individual signal line 208, to enable a staggered power-up or power-down of the CLEs, fig.2 and [0024], each CLEs having a dedicated signal line 208 coupling to the control circuit 104, figs.1-2), wherein the first dedicated hardware communication channel electrically isolates the first channel circuit from the second channel circuit (each individual signal line 208 of each CLEs isolates the CLEs from one another as shown in fig.2).
With respect to claim 15, Sood does not appear to teach that the multichannel I/O module for implementation with an industrial system.
However, it is known by Aradhyula et al. (US 2020/0278652) to also teach of a system for providing remote channel reset for an input/output (“I/O”) module of industrial system (I/O module 104 of industrial process control and automation system 100, fig.1 and fig.3), the system and the I/O module (fig.1 and fig.3) comprising: a plurality of channel circuits (first I/O circuitry 302 and second I/O circuitry 304 of I/O module 104, fig.3 and [0049]) for interfacing with industrial control equipment of an industrial system (to drive different electrical signals to multiple [equipment] devices 102a-102b, [0049], of industrial process control and automation system 100, fig.1).
Because Aradhyula’s teaching is also directed to input/output ("I/O") module for a system (Aradhyula: I/O module 104 of industrial process control and automation system 100, fig.1 and fig.3; Sood: IC device of fig.1), it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teaching of the I/O module for interfacing with industrial control equipment of an industrial system as taught by Aradhyula with the I/O module as taught by Sood for the purpose of communicating with the field devices over various I/O channels (Aradhyula: [0016]).
With respect to claim 16, Sood and Aradhyula combined teaches further comprising: controlling, with the electronic processor, a second power state of the second channel circuit via transmission of a second control signal using a second dedicated hardware communication channel communicatively coupling the electrical processor to the second channel circuit, wherein the first dedicated hardware communication channel is different from the second dedicated hardware communication channel (Each power control block 202 of each CLEs receive the global control signal and each of the control block 202 send the control signal to each CLEs via individual signal line 208, to enable a staggered power-up or power-down of the CLEs, fig.2 and [0024], each CLEs having a dedicated signal line 208 coupling to the control circuit 104, figs.1-2; Aradhyula: the module controller 310…coupled to control gates of the switches 306 and 308 in order to control the activation and deactivation of the switches 306 and 308…therefore separately provide drive signals to the control gates of the switches 306 and 308 in order to control whether the electrical currents I.sub.1 and I.sub.2 are generated, [0046]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4-5, 9, 13, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sood et al. (US 2016/0118988-A1) in view of Aradhyula et al. (US 2020/0278652) in view of Park Ho Kyun (KR 10-1940811-B1).
With respect to claims 4-5, 9, 13, and 17-20, Sood and Aradhyula combined teaches of performing a power reset cycle for the at least one channel circuit (Sood: a proper reset value of the registers that provide the default power-up state of the power gate 524 is loaded during the programming sequence [0032,0034,0043]) but does not appear to teach performing the power reset cycle to clear a fault in response to detecting a fault (a hardware fault and a software fault) associated with the at least one channel circuit.
However, it is known by Park to teach of a remote channel reset for I/O modules of industrial systems (Park: a system to power reset each of multiple channels connected via a communication means, abstract and fig.1) wherein the power reset system can be implemented with conventional system having at least a plurality of channel circuits (Park: conventional system with module group 20, fig.2) for interfacing with industrial control equipment of an industrial system (Park: each of module group 1-N interfaces with equipment 500, fig.2 and p.5) and with an electronic processor (Park: conventional microprocessor 12 of controlling apparatus 10, fig.2) communicatively coupled to each channel circuit (Park: coupled to the module group 20, fig.2) via a dedicated hardware communication channel (Park: via RS-232 communication port to communication means RS-232 #1-2, fig.1 and p.7-8). Particularly, Park teaches the limitation “performing the power reset cycle to clear a fault in response to detecting a fault (a hardware fault and a software fault) associated with the at least one channel circuit” (Park: CPU, fig.1 and p.9; automatically recover a malfunction of the remote monitoring control device due to a failure occurring in a certain module of the equipment connected to the remote monitoring control device, p.2; power supply for resetting the power of each channel connected to the communication means when there is no response from the communication means, p.8; CPU performs power reset control to recover the fault when the predetermined time passes after the power-off, p.9; identifying the fault caused by faulty module constituting the equipment repairs or exchanges the fault, p.5; identifying the fault caused by malfunction of the remote monitoring and control apparatus itself, p.5).
Because Park is also directed to a I/O module for industrial systems (Park: fig.2; Aradhyula: fig.1; Sood: figs.1-2), it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teaching of remote channel reset for I/O modules of industrial systems as taught by Park with the control I/O module system as taught by Sood and Aradhyula combined for the purpose of automatically recover a malfunction of the remote monitoring control device due to a failure occurring in a certain module of the equipment connected to the remote monitoring control device (Park: p.2).
Conclusion
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/HIEN D KHUU/Primary Examiner, Art Unit 2116 January 20, 2026