CTNF 17/955,634 CTNF 82548 DETAILED ACTION 1. Claims 1-20 are pending in the application. Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia 2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 3. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA 4. Claim(s) 1-5,10-14 and 19-20 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Indelicato et al (hereafter Indelicato) (US Pub. 2020/0210146) . Indelicato was cited in the IDS filed 01/30/2024 5. As to claim 1, Indelicato discloses a processing unit (abstract) comprising: a plurality of adders to add first and second X bit binary portion values of a first Y bit binary value and a second Y bit binary value to generate first carry bits, with Y being a multiple of X ([0027] and figs 4a-4c providing a sum using the adders, using sum bits x and Y, generating carry out); and a plurality of carry bit generation circuits, coupled to the plurality of adders, respectively, to receive the first carry bits and generate second carry bits based on the first carry bits; wherein the second carry bits are used to add the first and second X bit binary portions of the first and second Y bit binary values, respectively ([0026]-[0028] and [0031]-[0032] receiving carry bits and used to generate further C2, CC3, CC4, etc via summation.). 6. As to claims 2 and 15, Indelicato discloses wherein the plurality of carry bit generation circuits is configured to receive the addition of the first and second X bit binary portions of the first Y bit binary value and the second Y bit binary value, respectively, and to generate the second carry bits based on the addition of the first and second X bit binary portions of the first and second Y bit binary values ([0026]-[0028] and [0031]-[0032]). 7. As to claims 3 and 16, Indelicato discloses wherein the first and second Y bit binary values are stored by at least one of a vector register, a memory operand, Double Data Rate (DDR) memory, Low-Power DDR (LPDDR), and Gen-Z (fig 1 and [0011]). 8. As to claim 4, Indelicato discloses wherein a new Instruction Set Architecture (ISA) instruction is added to an existing ISA instruction set to add the first and second X bit binary portions of the first and second Y bit binary values ([0011]-[0013]). 9. As to claims 5 and 17, Indelicato discloses wherein the plurality of carry bit generation circuits comprise: a plurality of AND logic gates, respectively, a plurality of 1-bit full adders, respectively (fig 4a- 4c AND logic 482 and 483, full adders 423B); and a plurality of XOR logic gates, respectively (fig 4a-4c XOR gates 484, 485); wherein the plurality of AND logic gates is configured to: receive the addition of the first and second X bit binary portions of the first and second Y bit binary values from the plurality of adders, respectively; and output binary values to the plurality of 1-bit full adders and the plurality of XOR logic gates, respectively (fig 4a-4c); the plurality of 1-bit full adders is configured to: receive the binary values output from the plurality of AND logic gates, the first carry bits from the plurality of adders, and binary values from neighboring 1-bit full adders; and output binary values (fig 4a-4c); and the plurality of XOR logic gates is configured to: receive the binary values output by the plurality of AND logic gates and the binary values output by the plurality of 1-bit full adders; and output the second carry bits to a vector register (fig 4a-4c). 10. As to claims 10 and 14, the claims are rejected for similar reasons as to claim 1 above. 11. As to claims 11-13 and 19, Indelicato discloses a vector register to store the additions of the first and second X bit binary portions of the first and second Y bit binary values, respectively; wherein plurality of adders is a first plurality of adders, the processing unit comprising: a second plurality of adders to add the first and second Y bit binary values from first and second vector registers, respectively; and wherein the plurality of adders add the first and second Y bit binary values from the first and second vector registers, respectively (fig. 4a-4c [0026]-[0028]). 12. As to claim 20, Indelicato discloses a processing unit comprising: a first vector register to store a first Y bit binary value comprising a plurality of first X bit binary portions, with Y being a multiple of X; a second vector register to store a second Y bit binary value comprising a plurality of second X bit binary portions ([0016] registers); a plurality of adders to add first and second X bit binary portion values of the first Y bit binary value and the second Y bit binary value to generate first carry bits ([0027] and figs 4a-4c providing a sum using the adders, using sum bits x and Y, generating carry out); and a plurality of carry bit generation circuits, coupled to the plurality of adders, respectively, to receive the first carry bits and generate second carry bits based on the first carry bits; wherein the plurality of adders use the second carry bits to add the first and second X bit binary portions of the first and second Y bit binary values, respectively ([0026]-[0028] and [0031]-[0032] receiving carry bits and used to generate further C2, CC3, CC4, etc via summation.) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 13. Claim s 6-9 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: The claims recite at least wherein the plurality of AND logic gates is configured to: receive the addition of the first and second X bit binary portions of the first and second Y bit binary values from the plurality of adders; and output binary values to the plurality of 1-bit Vector Carry Propagation (VCP) logic circuits, respectively; and the plurality of 1-bit VCP logic circuits is configured to: receive the binary values from the plurality of AND logic gates, the first carry bits from the plurality of adders, and the binary values output by neighboring ones of the plurality of 1-bit VCP logic circuits; output other binary values to other neighboring ones of the plurality of 1-bit VCP logic circuits; and output the second carry bits to a vector register. The closest prior art of record US Pub. 20200210146 teaches the processing unit as in the independent claims. However, the prior art of record does not teach or suggest at least wherein the plurality of AND logic gates is configured to: receive the addition of the first and second X bit binary portions of the first and second Y bit binary values from the plurality of adders; and output binary values to the plurality of 1-bit Vector Carry Propagation (VCP) logic circuits, respectively; and the plurality of 1-bit VCP logic circuits is configured to: receive the binary values from the plurality of AND logic gates, the first carry bits from the plurality of adders, and the binary values output by neighboring ones of the plurality of 1-bit VCP logic circuits; output other binary values to other neighboring ones of the plurality of 1-bit VCP logic circuits; and output the second carry bits to a vector register . Conclusion 07-96 AIA 14. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pat. 4,853,887 – related to a binary adder for calculating the sum of two operands, among which one of the operands has a fixed, known value. US Pub. 2012/0233234 – related to a system and method for executing a multiply-add operation in a multiply-add pipeline utilizing an unrounded result from a prior operation. US Pub. 2021/0073171 – related to configurable and reconfigurable computing circuitry, and more specifically to a configurable and reconfigurable arithmetic engine having electronic circuitry for arithmetic and logical computations. US Pub. 2021/0096818 – related to a multiplication accumulating device and a method thereof, and particularly relates to a simplified multiplication accumulating device and a method thereof. US Pat. 11,366,638 – related to arithmetic logic circuits, including floating point, multiply-and-accumulate circuits for high speed processors, including processors configured for efficient execution of training and inference. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL D YAARY whose telephone number is (571)270-1249. The examiner can normally be reached Mon-Fri 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571)272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL D. YAARY/ Primary Examiner, Art Unit 2151 Application/Control Number: 17/955,634 Page 2 Art Unit: 2151 Application/Control Number: 17/955,634 Page 3 Art Unit: 2151 Application/Control Number: 17/955,634 Page 4 Art Unit: 2151 Application/Control Number: 17/955,634 Page 5 Art Unit: 2151 Application/Control Number: 17/955,634 Page 6 Art Unit: 2151 Application/Control Number: 17/955,634 Page 7 Art Unit: 2151 Application/Control Number: 17/955,634 Page 8 Art Unit: 2151 Application/Control Number: 17/955,634 Page 9 Art Unit: 2151