DETAILED ACTION
This Office Action is in response to the Response to Restriction/Election Requirement filed 12 December 2025. Claims 1-21 are pending in this application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 2 and SubSpecies 2 in the reply filed on 12 December 2025 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14, 19 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 14, in the last line of the claim, the claim says, “wherein corresponding ones of the second NMOS and CMOS transistors comprise shared gate electrodes.” This should read “wherein corresponding ones of the second NMOS and PMOS transistors comprise shared gate electrodes.” The CMOS is the cell that the NMOS and PMOS transistors are part of.
Regarding Claim 19, in the last line of the claim, the claim says, “wherein corresponding ones of the second NMOS and CMOS transistors comprise shared gate electrodes.” This should read “wherein corresponding ones of the second NMOS and PMOS transistors comprise shared gate electrodes.” The CMOS is the cell that the NMOS and PMOS transistors are part of.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7, 11-12, 14-21 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Liaw et. al (US 2022/0231145 A1).
Regarding Claim 1, Liaw discloses (as shown in Fig. 2A-E, 3A-E) An apparatus ([0023] FIGS. 2A-2E, FIGS. 3A-3E, and FIGS. 4A-4E are fragmentary diagrammatic views of SRAM cell 300, SRAM cell 400…), comprising:
a first transistor cell ([0052] FIGS. 3A-3E illustrate detailed structures for SRAM cell 400) over a substrate ([0053] SRAM cell 400 includes a substrate 412), the first transistor cell (400) comprising:
a first transistor ([0054] pass-gate transistor PG-1 ) comprising a first gate electrode ([0054] For example, pass-gate transistor PG-1 … each includes a portion of fin structure 420A disposed over p-type well 416A and a respective gate structure 450A, … disposed over channel regions of the fin structure 420A) coupled to a first semiconductor body ([0054] fin structure 420A); ([0054] For example, pass-gate transistor PG-1 … each includes a portion of fin structure 420A disposed over p-type well 416A and a respective gate structure 450A, … disposed over channel regions of the fin structure 420A)
a second transistor ([0054] pull-up transistor PU-1) comprising a second gate electrode ([0054] pull-up transistor PU-1 includes a portion of fin structure 420B disposed over n-type well 414 and gate structure 450D disposed over a channel region of the fin structure 420B) coupled to a second semiconductor body ([0054] In furtherance of the example, pull-up transistor PU-1 includes a portion of fin structure 420B) substantially parallel to the first semiconductor body (420A); (See Fig, 3A, showing the fin structures 420A, 420B substantially parallel)
and a dielectric material ([0053] ILD layers 452, 454 (similar to ILD layers 352, 354 described above with reference to FIGS. 2A-2E)) ([0046] interlayer dielectric layer (ILD-1)) separating the first gate electrode (PG-1) from the second gate electrode (PU1), ([0046] MLI feature 356 includes one or more dielectric layers, such as an interlayer dielectric layer 352 (ILD-0) disposed over substrate 312, an interlayer dielectric layer (ILD-1) disposed over ILD layer 352) (See Fig 3B)
wherein the first (PG-1) and second transistors (PU-1) comprise a first shared source or drain coupled to the first (420A) and second (420B) semiconductor bodies; ([0021] A gate of pull-up transistor PU-1 interposes a source (electrically coupled with a power supply voltage (VDD)) and a first common drain (CD1)… A gate of pass-gate transistor PG-1 interposes a source (electrically coupled with a bit line BL) and a drain, which is electrically coupled with the first common drain)
and a second transistor cell ([0023] SRAM cell 300) over the substrate ([0025] Substrate 312 includes various doped regions configured according to design requirements of SRAM cell 300), the second transistor cell (300) comprising:
NOTE: SRAMs 300 and 400 are disclosed as being part of the same device ([0038] Therefore, incorporating a lanthanum dopant into the gate dielectrics of p-type transistors of a first SRAM cell (e.g., PU-2 and PU-1 of SRAM cell 300), but not p-type transistors of the same type of a second SRAM cell on the same memory chip (e.g., PU-2 and PU-1 of SRAM cell 400), can allow for SRAM cells having p-type transistors of the same type with different threshold voltages—thus achieving two sets of p-type transistors of the same type on the same memory chip, each optimized for different applications depending on design requirements for the SRAM cells.)
a third transistor ([0026] pull-down transistor PD-1) comprising a third semiconductor body ([0026] fin structure 320A); ([0026] pull-down transistor PD-1 includes the fin structure 320A)
and a fourth transistor ([0026] pull-up transistor PU-1) comprising a fourth semiconductor body ([0026] fin structure 320B) ([0026] pull-up transistor PU-1 includes a fin structure 320B) substantially parallel to the third semiconductor body (420A), ([0027] Base fins 321A-321D are oriented substantially parallel to one another along a y-direction)
wherein the third (PD-1) and fourth (PU-1) transistors comprise a second shared source or drain ([0021] first common drain (CD1)) coupled to the third (PD-1) and fourth (PU-1) semiconductor bodies, ([0021] A gate of pull-up transistor PU-1 interposes a source (electrically coupled with a power supply voltage (VDD)) and a first common drain (CD1), and a gate of pull-down transistor PD-1 interposes a source (electrically coupled with a power supply voltage (Vss)) and the first common drain.)
and wherein the third (PD-1) and fourth (PU-1) transistors comprise a contiguous third gate electrode coupled to the third (320A) and fourth (320B) semiconductor bodies. (See Fig 2B, showing the gate electrodes (330B, 330D) of the third (PD-1) and fourth (PU-1) transistors, respectively, are contiguous)
Regarding Claim 2, Liaw further discloses (as shown in Figs. 2A-E, 3A-E) wherein the first (PG-1) and third transistors (PD-1) comprise NMOS transistors ([0025] p-type doped regions 316A and 316B are each configured for an n-type MOS (NMOS) transistor) ([0054] PD-1, PD-2 are n-type transistors)
and the second (PU-1) and fourth (PU-1) transistors comprise PMOS transistors. ([0025] N-type doped region 314 is configured for a p-type metal-oxide-semiconductor (PMOS) transistor, such as a pull-up (PU) transistor) ([0054] Pull-up transistors PU-1, PU-2 are p-type transistors)
Regarding Claim 3, Liaw further discloses (as shown in Figs. 2A-E, 3A-E) wherein the fourth transistor (PU-1) is to operate at a lower threshold voltage than the second transistor (PU-1). ([0056] a threshold voltage of p-type transistors PU-1, PU-2 of SRAM cell 400 is different than a threshold voltage of p-type transistors PU-1, PU-2 of SRAM cell 300. In some embodiments, the threshold voltage difference between the n-type transistors of the same type or the p-type transistors of the same type is about 30 mV to about 120 mV. Configuring a specific SRAM cell (such as SRAM cell 300 or 400) with transistors having lower threshold voltages (compared to transistors of the same type of other SRAM cells on the same memory chip) provides the specific SRAM cell with transistors that can be turned on at a lower power.) ([0057] In some embodiments, a threshold voltage of the transistors of SRAM cell 300 is lower than a threshold voltage of the same type of transistors of SRAM cell 400)
Regarding Claim 4, Liaw further discloses (as shown in Figs. 2A-E, 3A-E) wherein the first transistor cell (400) comprises a plurality of first NMOS transistors ([0054] a pass-gate transistor PG-1, a pass-gate transistor PG-2) ([0054] pass-gate transistors PG-1, PG-2 are n-type transistors) comprising first NMOS gate electrodes ([0054] Gate structures 450A, 450B, 450E, 450F and/or epitaxial source/drain features 426A and 426D of pass-gate transistors PG-1, PG-2 and/or pull-down transistors PD-1, PD-2)
and a plurality of first PMOS transistors ([0054] a pull-up transistor PU-1, a pull-up transistor PU-2) ([0054] Pull-up transistors PU-1, PU-2 are p-type transistors) comprising first PMOS gate electrodes ([0054] Gate structures 450C and 450D and/or epitaxial source/drain features 426B and 426C of pull-up transistors PU-1, PU-2) separated from the first NMOS gate electrodes (450A, 450F) by the dielectric material, ([0046] MLI feature 356 includes one or more dielectric layers, such as an interlayer dielectric layer 352 (ILD-0) disposed over substrate 312, an interlayer dielectric layer (ILD-1) disposed over ILD layer 352) (See Fig 3B)
([0026] pull-down transistor PD-2) ([0026] PD-1, PD-2, PG-1, and PG-2 are configured as n-type transistors) and a plurality of second PMOS transistors ([0026] Pull-up transistors … PU-2) ([0026] PU-1 and PU-2 are configured as p-type transistors), wherein corresponding ones of the second NMOS (PD-1, PD-2) and CMOS transistors (PU-1, PU-2) comprise shared gate electrodes extending orthogonal to the third semiconductor body. (See Fig 2A-B, showing the shared gate electrodes between the pull-down transistors and the pull-up transistors)
Regarding Claim 5, Liaw further discloses (as shown in Figs. 2A-E, 3A-E) wherein the first transistor comprises a first channel region, ([0054] For example, pass-gate transistor PG-1 and pull-down transistor PD-1 each includes a portion of fin structure 420A) ([0028] Fin structures 320A-320D each further include multiple channel layers 322A-322D formed in the channel region over the base fins 321A-321D)
the second transistor comprises a second channel region ([0026] pass-gate transistor PG-1 includes a fin structure 320A),
the third transistor comprises a third channel region, ([0054] pull-up transistor PU-1 includes a portion of fin structure 420B)
and the fourth transistor comprises a fourth channel region, ([0026] pull-up transistor PU-1 includes a fin structure 320B)
and wherein the first and third channel regions comprise a first material composition ([0026] Fin structures 320A and 320D include p-type doped fins) ([0053] For example, SRAM cell 400 includes fin structures 420A-420D, each having base fins 421A-421D (similar to fin structures 320A-320D having base fins 321A-321D described above with reference to FIGS. 2A-2E) and channel layers 422A-422D (similar to fin structures 320A-320D having channel layers 322A-322D described above with reference to FIGS. 2A-2E))
and the second and fourth channel regions comprise a second material composition ([0026] fin structures 320B and 320C include n-type doped fins). ([0053] For example, SRAM cell 400 includes fin structures 420A-420D, each having base fins 421A-421D (similar to fin structures 320A-320D having base fins 321A-321D described above with reference to FIGS. 2A-2E) and channel layers 422A-422D (similar to fin structures 320A-320D having channel layers 322A-322D described above with reference to FIGS. 2A-2E))
Regarding Claim 6, Liaw further discloses (as shown in Figs. 2A-E, 3A-E) wherein the contiguous third gate electrode (330B, 330D) comprises a first region (330B) over the third semiconductor body (320A) and a second region (330D) over the fourth semiconductor body (320B), (See Fig. 2B)
the first region (330B) comprising a first work function metal adjacent the third semiconductor body (320A) and the second region (330D) comprising a second work function metal adjacent the fourth semiconductor body (320B). ([0040] In some embodiments, one or more of gate electrodes 330A, 330B, 330E, and 330F include an n-type work function metal with a work function of about 4.0 eV to about 4.6 eV. In some embodiments, one or both gate electrodes 330C and 330D include a p-type work function metal with a work function of about 4.5 eV to about 5 eV.)
Regarding Claim 7, Liaw further discloses (as shown in Figs. 2A-E, 3A-E) wherein the first (330B) and second (330D) region each comprises a common continuous fill metal over the first and second work function metals. ([0057] As described above with respect to FIGS. 2A-2E, the gate electrodes of the transistors of SRAM cell 300 may include a combination of p-type work function layer (such as a TiN layer), n-type work function layer (such as a TiAl layer), capping layer (such as a TaN layer), and metal fill layer (such as a W layer).)
Regarding Claim 11, Liaw discloses (as shown in Fig. 2A-E, 3A-E) An apparatus ([0023] FIGS. 2A-2E, FIGS. 3A-3E, and FIGS. 4A-4E are fragmentary diagrammatic views of SRAM cell 300, SRAM cell 400…), comprising:
first ([0052] FIGS. 3A-3E illustrate detailed structures for SRAM cell 400) and second ([0023] SRAM cell 300) CMOS cells over a substrate ([0053] SRAM cell 400 includes a substrate 412),
wherein the first CMOS (400) cell comprises:
a first NMOS transistor ([0054] pass-gate transistor PG-1 ) ([0054] PG-1, PG-2 are n-type transistors) comprising a first gate electrode ([0054] For example, pass-gate transistor PG-1 … each includes a portion of fin structure 420A disposed over p-type well 416A and a respective gate structure 450A, … disposed over channel regions of the fin structure 420A) coupled to a first semiconductor body([0054] fin structure 420A); ([0054] For example, pass-gate transistor PG-1 … each includes a portion of fin structure 420A disposed over p-type well 416A and a respective gate structure 450A, … disposed over channel regions of the fin structure 420A)
and a first PMOS transistor ([0054] pull-up transistor PU-1) ([0054] Pull-up transistors PU-1, PU-2 are p-type transistors) comprising a second gate electrode ([0054] pull-up transistor PU-1 includes a portion of fin structure 420B disposed over n-type well 414 and gate structure 450D disposed over a channel region of the fin structure 420B) coupled to a second semiconductor body ([0054] In furtherance of the example, pull-up transistor PU-1 includes a portion of fin structure 420B),
wherein a dielectric material ([0053] ILD layers 452, 454 (similar to ILD layers 352, 354 described above with reference to FIGS. 2A-2E)) ([0046] interlayer dielectric layer (ILD-1)) separates the first (450A) and second (450D) gate electrodes, ([0046] MLI feature 356 includes one or more dielectric layers, such as an interlayer dielectric layer 352 (ILD-0) disposed over substrate 312, an interlayer dielectric layer (ILD-1) disposed over ILD layer 352) (See Fig 3B)
and the first NMOS (PG-1) and PMOS (PU-1) transistors comprise a first shared source or drain coupled to the first (420A) and second (420B) semiconductor bodies; ([0021] A gate of pull-up transistor PU-1 interposes a source (electrically coupled with a power supply voltage (VDD)) and a first common drain (CD1)… A gate of pass-gate transistor PG-1 interposes a source (electrically coupled with a bit line BL) and a drain, which is electrically coupled with the first common drain)
and the second CMOS (300) cell comprises:
a second NMOS transistor ([0026] pull-down transistor PD-1) ([0026] while PD-1, PD-2, PG-1, and PG-2 are configured as n-type transistors) comprising a third semiconductor body ([0026] fin structure 320A); ([0026] pull-down transistor PD-1 includes the fin structure 320A)
and a second PMOS transistor ([0026] pull-up transistor PU-1) ([0054] Pull-up transistors PU-1, PU-2 are p-type transistors) comprising a fourth semiconductor body([0026] fin structure 320B) ([0026] pull-up transistor PU-1 includes a fin structure 320B),
wherein the second NMOS (PD-1) and PMOS (PU-1) transistors comprise a second shared source or drain ([0021] first common drain (CD1)) coupled to the third (320A) and fourth (320B) semiconductor bodies, ([0021] A gate of pull-up transistor PU-1 interposes a source (electrically coupled with a power supply voltage (VDD)) and a first common drain (CD1), and a gate of pull-down transistor PD-1 interposes a source (electrically coupled with a power supply voltage (Vss)) and the first common drain.)
and the second NMOS (PD-1) and PMOS (PU-1) transistors comprise a shared third gate electrode coupled to the third (320A) and fourth (320B) semiconductor bodies. (See Fig 2B, showing the gate electrodes (330B, 330D) of the third (PD-1) and fourth (PU-1) transistors, respectively, are contiguous)
Regarding Claim 12, Liaw further discloses (as shown in Figs. 2A-E, 3A-E) wherein the second PMOS transistor (PU-1 of 300) is to operate at a lower threshold voltage than the first PMOS transistor (PU-1 of 400). ([0056] a threshold voltage of p-type transistors PU-1, PU-2 of SRAM cell 400 is different than a threshold voltage of p-type transistors PU-1, PU-2 of SRAM cell 300. In some embodiments, the threshold voltage difference between the n-type transistors of the same type or the p-type transistors of the same type is about 30 mV to about 120 mV. Configuring a specific SRAM cell (such as SRAM cell 300 or 400) with transistors having lower threshold voltages (compared to transistors of the same type of other SRAM cells on the same memory chip) provides the specific SRAM cell with transistors that can be turned on at a lower power.) ([0057] In some embodiments, a threshold voltage of the transistors of SRAM cell 300 is lower than a threshold voltage of the same type of transistors of SRAM cell 400)
Regarding Claim 14, Liaw further discloses (as shown in Figs. 2A-E, 3A-E) wherein the first transistor cell (400) comprises a plurality of first NMOS transistors ([0054] a pass-gate transistor PG-1, a pass-gate transistor PG-2) ([0054] pass-gate transistors PG-1, PG-2 are n-type transistors) comprising first NMOS gate electrodes ([0054] Gate structures 450A, 450B, 450E, 450F and/or epitaxial source/drain features 426A and 426D of pass-gate transistors PG-1, PG-2 and/or pull-down transistors PD-1, PD-2)
and a plurality of first PMOS transistors ([0054] a pull-up transistor PU-1, a pull-up transistor PU-2) ([0054] Pull-up transistors PU-1, PU-2 are p-type transistors) comprising first PMOS gate electrodes ([0054] Gate structures 450C and 450D and/or epitaxial source/drain features 426B and 426C of pull-up transistors PU-1, PU-2) separated from the first NMOS gate electrodes (450A, 450F) by the dielectric material, ([0046] MLI feature 356 includes one or more dielectric layers, such as an interlayer dielectric layer 352 (ILD-0) disposed over substrate 312, an interlayer dielectric layer (ILD-1) disposed over ILD layer 352) (See Fig 3B)
and the second cell (300) comprises a plurality of second NMOS transistors ([0026] pull-down transistor PD-2) ([0026] PD-1, PD-2, PG-1, and PG-2 are configured as n-type transistors) and a plurality of second PMOS transistors ([0026] Pull-up transistors … PU-2) ([0026] PU-1 and PU-2 are configured as p-type transistors), wherein corresponding ones of the second NMOS (PD-1, PD-2) and CMOS transistors (PU-1, PU-2) comprise shared gate electrodes extending orthogonal to the third semiconductor body. (See Fig 2A-B, showing the shared gate electrodes between the pull-down transistors and the pull-up transistors)
Regarding Claim 15, Liaw further discloses (as shown in Figs. 2A-E, 3A-E) wherein the shared third gate electrode (330B, 330D) comprises a first region (330B) over the third semiconductor body (320A) and a second region (330D) over the fourth semiconductor body (320B), (See Fig. 2B)
the first region (330B) comprising a first work function metal adjacent the third semiconductor body (320A) and the second region (330D) comprising a second work function metal adjacent the fourth semiconductor body (320B). ([0040] In some embodiments, one or more of gate electrodes 330A, 330B, 330E, and 330F include an n-type work function metal with a work function of about 4.0 eV to about 4.6 eV. In some embodiments, one or both gate electrodes 330C and 330D include a p-type work function metal with a work function of about 4.5 eV to about 5 eV.)
wherein the first (330B) and second (330D) region each comprises a common continuous fill metal over the first and second work function metals. ([0057] As described above with respect to FIGS. 2A-2E, the gate electrodes of the transistors of SRAM cell 300 may include a combination of p-type work function layer (such as a TiN layer), n-type work function layer (such as a TiAl layer), capping layer (such as a TaN layer), and metal fill layer (such as a W layer).)
Regarding Claim 16, Liaw discloses (as shown in Figs. 2A-E, 3A-E) A system ([0068] SRAM chip 10), comprising:
an integrated circuit (IC) die comprising a first transistor cell and a second transistor cell, ([0068] Referring back to FIG. 1A, as described above, SRAM chip 10 may include two SRAM cells 300 and 400 which resemble each other with respect to features they include.)
wherein the first transistor cell ([0052] FIGS. 3A-3E illustrate detailed structures for SRAM cell 400) comprises:
a first transistor ([0054] pass-gate transistor PG-1 ) comprising a first gate electrode ([0054] For example, pass-gate transistor PG-1 … each includes a portion of fin structure 420A disposed over p-type well 416A and a respective gate structure 450A, … disposed over channel regions of the fin structure 420A) coupled to a first semiconductor body ([0054] fin structure 420A); ([0054] For example, pass-gate transistor PG-1 … each includes a portion of fin structure 420A disposed over p-type well 416A and a respective gate structure 450A, … disposed over channel regions of the fin structure 420A)
a second transistor ([0054] pull-up transistor PU-1) comprising a second gate electrode ([0054] pull-up transistor PU-1 includes a portion of fin structure 420B disposed over n-type well 414 and gate structure 450D disposed over a channel region of the fin structure 420B) coupled to a second semiconductor body ([0054] In furtherance of the example, pull-up transistor PU-1 includes a portion of fin structure 420B) substantially parallel to the first semiconductor body (420A); (See Fig, 3A, showing the fin structures 420A, 420B substantially parallel)
and a dielectric material ([0053] ILD layers 452, 454 (similar to ILD layers 352, 354 described above with reference to FIGS. 2A-2E)) ([0046] interlayer dielectric layer (ILD-1)) separating the first gate electrode (PG-1) from the second gate electrode (PU1), ([0046] MLI feature 356 includes one or more dielectric layers, such as an interlayer dielectric layer 352 (ILD-0) disposed over substrate 312, an interlayer dielectric layer (ILD-1) disposed over ILD layer 352) (See Fig 3B)
wherein the first (PG-1) and second transistors (PU-1) comprise a first shared source or drain coupled to the first (420A) and second (420B) semiconductor bodies; ([0021] A gate of pull-up transistor PU-1 interposes a source (electrically coupled with a power supply voltage (VDD)) and a first common drain (CD1)… A gate of pass-gate transistor PG-1 interposes a source (electrically coupled with a bit line BL) and a drain, which is electrically coupled with the first common drain)
and wherein the second transistor cell ([0023] SRAM cell 300) comprises:
a third transistor ([0026] pull-down transistor PD-1) comprising a third semiconductor body ([0026] fin structure 320A); ([0026] pull-down transistor PD-1 includes the fin structure 320A)
and a fourth transistor ([0026] pull-up transistor PU-1) comprising a fourth semiconductor body ([0026] fin structure 320B) ([0026] pull-up transistor PU-1 includes a fin structure 320B) substantially parallel to the third semiconductor body (420A), ([0027] Base fins 321A-321D are oriented substantially parallel to one another along a y-direction)
wherein the third (PD-1) and fourth (PU-1) transistors comprise a second shared source or drain ([0021] first common drain (CD1)) coupled to the third (PD-1) and fourth (PU-1) semiconductor bodies, ([0021] A gate of pull-up transistor PU-1 interposes a source (electrically coupled with a power supply voltage (VDD)) and a first common drain (CD1), and a gate of pull-down transistor PD-1 interposes a source (electrically coupled with a power supply voltage (Vss)) and the first common drain.)
and wherein the third (PD-1) and fourth (PU-1) transistors comprise a contiguous third gate electrode coupled to the third (320A) and fourth (320B) semiconductor bodies. (See Fig 2B, showing the gate electrodes (330B, 330D) of the third (PD-1) and fourth (PU-1) transistors, respectively, are contiguous)
and a power supply coupled to the IC die. ([0049] A source region of pull-up transistor PU-1 (formed by p-type epitaxial source/drain features 326B) is electrically connected to a power supply voltage VDD at a voltage node VDDN1 by device-level contact 360C)
Regarding Claim 17, Liaw further discloses (as shown in Figs. 2A-E, 3A-E) wherein the first (PG-1) and third transistors (PD-1) comprise NMOS transistors ([0025] p-type doped regions 316A and 316B are each configured for an n-type MOS (NMOS) transistor) ([0054] PD-1, PD-2 are n-type transistors)
and the second (PU-1) and fourth (PU-1) transistors comprise PMOS transistors. ([0025] N-type doped region 314 is configured for a p-type metal-oxide-semiconductor (PMOS) transistor, such as a pull-up (PU) transistor) ([0054] Pull-up transistors PU-1, PU-2 are p-type transistors)
Regarding Claim 18, Liaw further discloses (as shown in Figs. 2A-E, 3A-E) wherein the fourth transistor (PU-1) is to operate at a lower threshold voltage than the second transistor (PU-1). ([0056] a threshold voltage of p-type transistors PU-1, PU-2 of SRAM cell 400 is different than a threshold voltage of p-type transistors PU-1, PU-2 of SRAM cell 300. In some embodiments, the threshold voltage difference between the n-type transistors of the same type or the p-type transistors of the same type is about 30 mV to about 120 mV. Configuring a specific SRAM cell (such as SRAM cell 300 or 400) with transistors having lower threshold voltages (compared to transistors of the same type of other SRAM cells on the same memory chip) provides the specific SRAM cell with transistors that can be turned on at a lower power.) ([0057] In some embodiments, a threshold voltage of the transistors of SRAM cell 300 is lower than a threshold voltage of the same type of transistors of SRAM cell 400)
Regarding Claim 19, Liaw further discloses (as shown in Figs. 2A-E, 3A-E) wherein the first transistor cell (400) comprises a plurality of first NMOS transistors ([0054] a pass-gate transistor PG-1, a pass-gate transistor PG-2) ([0054] pass-gate transistors PG-1, PG-2 are n-type transistors) comprising first NMOS gate electrodes ([0054] Gate structures 450A, 450B, 450E, 450F and/or epitaxial source/drain features 426A and 426D of pass-gate transistors PG-1, PG-2 and/or pull-down transistors PD-1, PD-2)
and a plurality of first PMOS transistors ([0054] a pull-up transistor PU-1, a pull-up transistor PU-2) ([0054] Pull-up transistors PU-1, PU-2 are p-type transistors) comprising first PMOS gate electrodes ([0054] Gate structures 450C and 450D and/or epitaxial source/drain features 426B and 426C of pull-up transistors PU-1, PU-2) separated from the first NMOS gate electrodes (450A, 450F) by the dielectric material, ([0046] MLI feature 356 includes one or more dielectric layers, such as an interlayer dielectric layer 352 (ILD-0) disposed over substrate 312, an interlayer dielectric layer (ILD-1) disposed over ILD layer 352) (See Fig 3B)
and the second transistor cell (300) comprises a plurality of second NMOS transistors ([0026] pull-down transistor PD-2) ([0026] PD-1, PD-2, PG-1, and PG-2 are configured as n-type transistors) and a plurality of second PMOS transistors ([0026] Pull-up transistors … PU-2) ([0026] PU-1 and PU-2 are configured as p-type transistors), wherein corresponding ones of the second NMOS (PD-1, PD-2) and CMOS transistors (PU-1, PU-2) comprise shared gate electrodes extending orthogonal to the third semiconductor body. (See Fig 2A-B, showing the shared gate electrodes between the pull-down transistors and the pull-up transistors)
Regarding Claim 20, Liaw further discloses (as shown in Figs. 2A-E, 3A-E) wherein the first transistor comprises a first channel region, ([0054] For example, pass-gate transistor PG-1 and pull-down transistor PD-1 each includes a portion of fin structure 420A) ([0028] Fin structures 320A-320D each further include multiple channel layers 322A-322D formed in the channel region over the base fins 321A-321D)
the second transistor comprises a second channel region ([0026] pass-gate transistor PG-1 includes a fin structure 320A),
the third transistor comprises a third channel region, ([0054] pull-up transistor PU-1 includes a portion of fin structure 420B)
and the fourth transistor comprises a fourth channel region, ([0026] pull-up transistor PU-1 includes a fin structure 320B)
and wherein the first and third channel regions comprise a first material composition ([0026] Fin structures 320A and 320D include p-type doped fins) ([0053] For example, SRAM cell 400 includes fin structures 420A-420D, each having base fins 421A-421D (similar to fin structures 320A-320D having base fins 321A-321D described above with reference to FIGS. 2A-2E) and channel layers 422A-422D (similar to fin structures 320A-320D having channel layers 322A-322D described above with reference to FIGS. 2A-2E))
and the second and fourth channel regions comprise a second material composition ([0026] fin structures 320B and 320C include n-type doped fins). ([0053] For example, SRAM cell 400 includes fin structures 420A-420D, each having base fins 421A-421D (similar to fin structures 320A-320D having base fins 321A-321D described above with reference to FIGS. 2A-2E) and channel layers 422A-422D (similar to fin structures 320A-320D having channel layers 322A-322D described above with reference to FIGS. 2A-2E))
Regarding Claim 21, Liaw further discloses (as shown in Figs. 2A-E, 3A-E) wherein the contiguous third gate electrode (330B, 330D) comprises a first region (330B) over the third semiconductor body (320A) and a second region (330D) over the fourth semiconductor body (320B), (See Fig. 2B)
the first region (330B) comprising a first work function metal adjacent the third semiconductor body (320A) and the second region (330D) comprising a second work function metal adjacent the fourth semiconductor body (320B). ([0040] In some embodiments, one or more of gate electrodes 330A, 330B, 330E, and 330F include an n-type work function metal with a work function of about 4.0 eV to about 4.6 eV. In some embodiments, one or both gate electrodes 330C and 330D include a p-type work function metal with a work function of about 4.5 eV to about 5 eV.)
wherein the first (330B) and second (330D) region each comprises a common continuous fill metal over the first and second work function metals. ([0057] As described above with respect to FIGS. 2A-2E, the gate electrodes of the transistors of SRAM cell 300 may include a combination of p-type work function layer (such as a TiN layer), n-type work function layer (such as a TiAl layer), capping layer (such as a TaN layer), and metal fill layer (such as a W layer).)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liaw as applied to claim 12 above.
Regarding Claim 13, Liaw further discloses (as shown in Figs. 2A-E, 3A-E) wherein the first PMOS transistor is to operate at a threshold voltage of not more than 250 mV ([0038] p-type transistors PU-1 and/or PU-2 may have a threshold voltage of about 0.2 V to about 0.4 V)
and the second PMOS transistor is to operate at a threshold voltage of not more than 200 mV. ([0038] In some implementations, the threshold voltage difference of p-type transistors of SRAM cell 300 relative to p-type transistors of the same type of other SRAM cells on the same memory chip may be 30 mV to 120 mV.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have the threshold voltage of the second PMOS transistor (PU-1 of 300) to have a threshold voltage of not more than 200 mV. Liaw teaches that the threshold voltage is between 200 and 400 mV ([0038] p-type transistors PU-1 and/or PU-2 may have a threshold voltage of about 0.2 V to about 0.4 V) and this range overlaps with the claimed range at 200 mV.
It would also have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have the threshold voltage of the first PMOS transistor (PU-1 of 400) to have a threshold voltage of not more than 250 mV. Liaw teaches that the PMOS transistor of the SRAM 300 is between 30 and 120 mV below the threshold voltage of the SRAM 400 ([0038] In some implementations, the threshold voltage difference of p-type transistors of SRAM cell 300 relative to p-type transistors of the same type of other SRAM cells on the same memory chip may be 30 mV to 120 mV.) This range overlaps with the claimed range when the PMOS transistor of SRAM 300 is on the low end (For example if the PMOS of the SRAM 300 is 200 mV is 30 mV lower than the PMOS transistor of SRAM 300)
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (‘145) as applied to claim 1 above, and further in view of Liaw et. al (US 2023/0262951 A1).
Regarding Claim 8, Liaw (‘145) fails to disclose wherein the second transistor cell (300) further comprises a fifth transistor and a sixth transistor, wherein the fifth transistor shares a source or drain with the third transistor (PU-1) and the sixth transistor shares a source or drain with the fourth transistor (PG-1), and wherein the fifth and sixth transistors comprise a contiguous fourth gate electrode.
Liaw (‘951) discloses (as shown in Fig. 3) wherein the second transistor cell ([0027] dual cell 200) further comprises a fifth transistor ([0028] the second pull-up transistor (PU-12)) and a sixth transistor ([0028] a second pull-down transistor (PD-12)),
wherein the fifth transistor (PU-12) shares a source or drain with the third transistor ([0028] the first pull-up transistor (PU-11)) ([0030] Referring still to FIG. 3, the drain of the first pull-down transistor (PD-11) and the drain of the first pull-up transistor (PU-11) share the same source/drain contact that spans over the first fin 202, the second fin 204 and the third fin 206. This shared source/drain contact is electrically coupled to the shared gate structure of the second pull-down transistor (PD-12) and the second pull-up transistor (PU-12) by a local contact line extending along the Y direction.)
and the sixth transistor (PD-12) shares a source or drain with the fourth transistor ([0028] a first pull-down transistor (PD-11)), ([0030] Referring still to FIG. 3, the drain of the first pull-down transistor (PD-11) and the drain of the first pull-up transistor (PU-11) share the same source/drain contact that spans over the first fin 202, the second fin 204 and the third fin 206. This shared source/drain contact is electrically coupled to the shared gate structure of the second pull-down transistor (PD-12) and the second pull-up transistor (PU-12) by a local contact line extending along the Y direction.)
and wherein the fifth (PU-11) and sixth transistors (PD-12) comprise a contiguous fourth gate electrode. ([0030] the shared gate structure of the second pull-down transistor (PD-12) and the second pull-up transistor (PU-12))
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the teachings of Liaw (‘145) with Liaw (‘951). Liaw teaches that SRAM cells can contain multiple devices with shared source/drain structures in order to reduce cell dimensions. ([0019] Static Random Access Memory (SRAM) is commonly used in integrated circuits as it is featured with the ability to hold data without the need to refresh. In IC design, a plurality of devices may be grouped together as an SRAM cell, which serves as a basic building block of a memory array or memory device. To meet the constant need of scaling down, efforts are invested to bring down the size of an SRAM cell. This scaling down process is not without challenges. For example, to allow shared gate structures and shared source/drain contacts to reduce cell dimensions) Therefore, it would have been obvious for the third transistor to share an S/D region with the fifth transistor, and the fourth transistor to share an S/D region with the sixth transistor in order to reduce the cell size.
Regarding Claim 9, Liaw (‘951) further discloses (as shown in Fig. 3) wherein the second transistor cell (200) further comprises a seventh transistor ([0028] second pass-gate transistor (PG-12)) comprising a fifth gate electrode ([0029] Referring still to FIG. 3, the gate structures of … the second pass-gate transistor (PG-12)) coupled to the third semiconductor body ([0028] second fin 204), (See Fig. 3, showing the gate PG-12 covering the fin 204)
and an eighth transistor ([0028] second isolation transistor (IS-12)) comprising a sixth gate electrode ([0029] Referring still to FIG. 3, the gate structures of the … the second isolation transistor (IS-12), …) coupled to the fourth semiconductor body ([0030] third fin 206 ), (See Fig. 3, showing the gate IS-12 covering the fin 206)
wherein the dielectric material separates the fifth gate electrode from the sixth gate electrode. ([0029] the gate structures of the first pass-gate transistor (PG-11) and the first isolation transistor (IS-11) may be formed from a single gate structure by dividing these gate structures with a dielectric feature)
Allowable Subject Matter
Claim 10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 10, neither Liaw (‘145) nor Liaw (‘951) disclose wherein the second transistor cell further comprises a seventh transistor and an eighth transistor, wherein the seventh transistor shares a source or drain with the fifth transistor (PU-12) and the eight transistor shares a source or drain with the sixth transistor (PD-12), and wherein the seventh and eighth transistors comprise a contiguous fifth gate electrode.
As noted in the rejection of Claim 9, Liaw (‘951) discloses:
a seventh transistor ([0028] second pass-gate transistor (PG-12)) comprising a fifth gate electrode ([0029] Referring still to FIG. 3, the gate structures of … the second pass-gate transistor (PG-12)) coupled to the third semiconductor body ([0028] second fin 204), (See Fig. 3, showing the gate PG-12 covering the fin 204)
and an eighth transistor ([0028] second isolation transistor (IS-12)) comprising a sixth gate electrode ([0029] Referring still to FIG. 3, the gate structures of the … the second isolation transistor (IS-12), …) coupled to the fourth semiconductor body ([0030] third fin 206 ), (See Fig. 3, showing the gate IS-12 covering the fin 206).
However, the transistors PG-12 and IS-12 are separated by a dielectric material. ([0029] the gate structures of the first pass-gate transistor (PG-11) and the first isolation transistor (IS-11) may be formed from a single gate structure by dividing these gate structures with a dielectric feature) It would not have been obvious to make the gates contiguous because the pass gates are always shown as isolated.
Therefore, the claim contains a limitation that is not contained in the prior art and therefore contains allowable subject matter.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON JAMES GREAVING whose telephone number is (703)756-5653. The examiner can normally be reached 7:30am - 5:00 pm.
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/JASON JAMES GREAVING/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893