DETAILED ACTION
This Office Action is in response to the Amendments filed 08 April 2026. Claims 1-14, 21-28 are pending in this application. Claims 15-20 have been cancelled.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Applicant’s amendments have addressed the previous 112b issues. Therefore, the previous 112b rejections are withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-2, 4-5, 8-9, 11, 14, 22, 24-25, 27-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara et. al (US 2020/0411063 A1) (newly cited) in view of Jeong (US 2020/0227421 A1) (newly cited).
Regarding Claim 1, Fujiwara discloses (as shown in Fig. 1A, 3A) an apparatus, comprising:
a first transistor cell ([0038] Referring to FIG. 3A, the two memory cells MC1), the first transistor cell comprising:
a first transistor ([0017] It should be noted that, each circuit element “transmission gate” mentioned in the present disclosure may include a complementary metal-oxide-semiconductor (CMOS) circuit having an N type MOSFET (e.g., a fin-type field effect transistor (finFET) of N type) and a P type MOSFET (e.g., a finFET of P type)) comprising a first gate electrode ([0019] the storage transmission gate line 102 includes first and second gate line segments 102a) coupled to a first semiconductor body ([0018] first … active structures F1); ([0019] The first gate line segment 102a intersects with the first active structures F1 from above the first active structures F1)
a second transistor ([0017] It should be noted that, each circuit element “transmission gate” mentioned in the present disclosure may include a complementary metal-oxide-semiconductor (CMOS) circuit having an N type MOSFET (e.g., a fin-type field effect transistor (finFET) of N type) and a P type MOSFET (e.g., a finFET of P type)) comprising a second gate electrode ([0019] the storage transmission gate line 102 includes first and second gate line segments … 102b) coupled to a second semiconductor body ([0018] second active structures … F2) ([0019] the second gate line segment 102b intersects with the second active structures F2 from above the second active structures F2)
substantially parallel to the first semiconductor body (F1); (See Fig. 1A)
wherein the first and second transistors comprise a first shared source or drain ([0019] The first … source/drain lines 104) coupled to the first (F1) and second (F2) semiconductor bodies, ([0019] The first and second source/drain lines 104 and 106 continuously extend to intersect the first and second active structures F1 and F2 from above the first and second active structures F1 and F2)
the first gate electrode (102a) and the second gate electrode (102b) are colinear, (See Fig. 1A)
and a second transistor cell ([0038] Referring to FIG. 3A, the two memory cells MC1 arranged along the second direction DR2 are each substantially identical to the memory cell MC1 shown in FIG. 2A, but are symmetrical with each other with respect to the common ground line GL shared by the two memory cells MC1), the second transistor cell comprising:
a third transistor ([0020] The first gate line 108, the second source/drain lines 106 and the third source/drain line 110 are functioned as terminals of the first inverter IV1 as shown in FIG. 1B.) comprising a third semiconductor body ([0018] first … active structures F1); ([0020] The first gate line 108 continuously extends to intersect the first and second active structures F1 and F2 from above the first and second active structures F1 and F2)
and a fourth transistor ([0020] The first gate line 108, the second source/drain lines 106 and the third source/drain line 110 are functioned as terminals of the first inverter IV1 as shown in FIG. 1B) comprising a fourth semiconductor body ([0018] second active structures … F2 ) ([0020] The first gate line 108 continuously extends to intersect the first and second active structures F1 and F2 from above the first and second active structures F1 and F2)
substantially parallel to the third semiconductor body (F1), (See Fig. 1A)
wherein the third (F1) and fourth (F2) transistors comprise a second shared source or drain ([0019] second source/drain line 106) coupled to the third and fourth semiconductor bodies, ([0019] The first and second source/drain lines 104 and 106 continuously extend to intersect the first and second active structures F1 and F2 from above the first and second active structures F1 and F2.)
and wherein the third and fourth transistors comprise a contiguous third gate electrode ([0020] first gate line 108) coupled to the third (F1) and fourth (F2) semiconductor bodies. ([0020] he first gate line 108 continuously extends to intersect the first and second active structures F1 and F2 from above the first and second active structures F1 and F2)
However, Fujiwara fails to disclose the first and second transistor cells are over a substrate,
and a dielectric material separating the first gate electrode from the second gate electrode, and the dielectric material fills a gate cut between the first gate electrode and the second gate electrode;
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have the first and second transistor cells over a substrate. Fujiwara teaches that the transistors are FinFets ([0017] It should be noted that, each circuit element “transmission gate” mentioned in the present disclosure may include a complementary metal-oxide-semiconductor (CMOS) circuit having an N type MOSFET (e.g., a fin-type field effect transistor (finFET) of N type) and a P type MOSFET (e.g., a finFET of P type)) which are a well-known type of transistor, which are known to be built on a substrate.
However, Fujiwara still fails to disclose a dielectric material separating the first gate electrode from the second gate electrode, and the dielectric material fills a gate cut between the first gate electrode and the second gate electrode.
Jeong discloses (as shown in Fig. 2) a dielectric material ([0029] gate isolation layers IG1, IG2, IG3, and IG) separating the first gate electrode ([0027] second pass transistor PG2) from the second gate electrode ([0027] first pull-up transistor PU1), and the dielectric material (IG) fills a gate cut between the first gate electrode (PG2) and the second gate electrode (PU1). ([0035] The gate isolation layers IG1, IG2, IG3, and IG may be disposed between the gate lines GL spaced apart from each other in the second direction. A first gate isolation layer IG1 may be disposed between the first gate line GL1 and the fourth gate line GL4 in the first SRAM cell C1. )
Claim Interpretation Note: A gate cut is just a technique that creates a gap in an otherwise continuous gate. Therefore, claiming a gate cut is just claiming a spacing between the ends of the gates facing each other since the product claim does not care how the spacing is formed. (See MPEP 2113, Product-by-Process Claims)
Jeong teaches that the gate isolation layer (IG) is used to separate one gate line (GL) into two gates. ([0057] Thus, One gate line GL may be separated to two by the gate isolation layer IG.) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the teachings of Fujiwara and Jeong in to fill a gate cut with a dielectric material in order to separate a single gate line into two gates.
Regarding Claim 2, Fujiwara further discloses (as shown in Fig. 3A) wherein the first and third transistors (F1) comprise NMOS transistors and the second and fourth transistors (F2) comprise PMOS transistors. ([0018] The first active structures F1 have a first conductive type, whereas the second active structures F2 have a second conductive complementary to the first conductive type. For instance, in some embodiments, the first conductive type is N type, whereas the second conductive type is P type)
Regarding Claim 4, Fujiwara further discloses (as shown in Fig. An. 3A) wherein the first transistor cell (MC1, upper) comprises a plurality of first NMOS transistors comprising first NMOS gate electrodes and a plurality of first PMOS transistors comprising first PMOS gate electrodes separated from the first NMOS gate electrodes by the dielectric material, (See An. Fig. 3A, showing a plurality of first NMOS transistors and first PMOS transistors with separated gates)
and the second transistor cell (MC1, lower) comprises a plurality of second NMOS transistors and a plurality of second PMOS transistors, wherein corresponding ones of the second NMOS and PMOS transistors comprise shared gate electrodes extending orthogonal to the third semiconductor body. (See An. Fig. 3A, showing a plurality of second NMOS transistors and second PMOS transistors with shared gates)
Jeong discloses (as shown in Fig. 2) a dielectric material ([0029] gate isolation layers IG1, IG2, IG3, and IG) separating the first NMOS gate electrode ([0027] second pass transistor PG2) from the First PMOS gate electrode ([0027] first pull-up transistor PU1), and the dielectric material (IG) fills a gate cut between the first gate electrode (PG2) and the second gate electrode (PU1). ([0035] The gate isolation layers IG1, IG2, IG3, and IG may be disposed between the gate lines GL spaced apart from each other in the second direction. A first gate isolation layer IG1 may be disposed between the first gate line GL1 and the fourth gate line GL4 in the first SRAM cell C1. )
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Regarding Claim 5, Fujiwara further discloses (as shown in Fig. 3A) wherein the first transistor comprises a first channel region, ([0018] portion of the first … active structures F1 … are included in the memory cell MC.)
the second transistor comprises a second channel region, ([0018] portion of the … second active structures … F2 are included in the memory cell MC.)
the third transistor comprises a third channel region, ([0018] portion of the first … active structures F1 … are included in the memory cell MC.)
and the fourth transistor comprises a fourth channel region, ([0018] portion of the … second active structures … F2 are included in the memory cell MC.)
and wherein the first and third channel regions comprise a first material composition ([0038] Referring to FIG. 3A, the two memory cells MC1 arranged along the second direction DR2 are each substantially identical to the memory cell MC1 shown in FIG. 2A)
and the second and fourth channel regions comprise a second material composition. ([0038] Referring to FIG. 3A, the two memory cells MC1 arranged along the second direction DR2 are each substantially identical to the memory cell MC1 shown in FIG. 2A)
Regarding Claim 8, Fujiwara further discloses (as shown in Figs. 1A, 3A) wherein the second transistor cell (See fig. 3A, M1, lower) further comprises a fifth transistor and a sixth transistor, ([0021] The second gate line 112, the third source/drain lines 110 and the fourth source/drain line 114 are functioned as terminals of the second inverter IV2 as shown in FIG. 1B)
wherein the fifth transistor shares a source or drain ([0020] The third source/drain line 110 includes first ... source/drain line segments 110a) with the third transistor (See Fig. 1A, showing source/drain line segment 110a shared by gates 108, 112)
and the sixth transistor shares a source or drain ([0020] The third source/drain line 110 includes … second source/drain line segments … 110b) with the fourth transistor, (See Fig. 1A, showing source/drain line segment 110b shared by gates 108, 112)
and wherein the fifth and sixth transistors comprise a contiguous fourth gate electrode. ([0021] The second gate line 112 and the fourth source/drain line 114 continuously extend to intersect the first and second active structures F1 and F2 from above the first and second active structures F1 and F2)
Regarding Claim 9, Fujiwara further discloses (as shown in Figs. 1A, 3A) wherein the second transistor cell (See Fig. 3A, M1, lower) further comprises a seventh transistor comprising a fifth gate electrode coupled to the third semiconductor body, ([0019] The storage transmission gate line 102 and the first and second source/drain lines 104 and 106 are functioned as terminals of the storage transmission gate ST as shown in FIG. 1B…The first gate line segment 102a intersects with the first active structures F1 from above the first active structures F1)
and an eighth transistor comprising a sixth gate electrode coupled to the fourth semiconductor body, ([0019] The storage transmission gate line 102 and the first and second source/drain lines 104 and 106 are functioned as terminals of the storage transmission gate ST as shown in FIG. 1B…whereas the second gate line segment 102b intersects with the second active structures F2 from above the second active structures F2) wherein the fifth (102a) and sixth (120b) gate electrodes are separated.([0019] In addition, the storage transmission gate line 102 includes first and second gate line segments 102a and 102b, which extend along the second direction DR2, and are separated from each other.)
However, Fujiwara fails to disclose the dielectric material separates the fifth gate electrode from the sixth gate electrode.
Jeong discloses a dielectric material separating the gate electrodes. ([0035] The gate isolation layers IG1, IG2, IG3, and IG may be disposed between the gate lines GL spaced apart from each other in the second direction. A first gate isolation layer IG1 may be disposed between the first gate line GL1 and the fourth gate line GL4 in the first SRAM cell C1.)
Regarding Claim 11, Fujiwara discloses (as shown in Figs. 1A, 3A) An apparatus, comprising:
first and second CMOS cells ([0038] Referring to FIG. 3A, the two memory cells MC1),
wherein the first CMOS cell (See Fig. 3A, upper MC1) comprises:
a first NMOS transistor ([0018] The first active structures F1 have a first conductive type, … For instance, in some embodiments, the first conductive type is N type) comprising a first gate electrode ([0019] the storage transmission gate line 102 includes first … gate line segments 102a) coupled to a first semiconductor body ([0018] first … active structures F1); ([0019] The first gate line segment 102a intersects with the first active structures F1 from above the first active structures F1)
and a first PMOS transistor ([0018] whereas the second active structures F2 have a second conductive complementary to the first conductive type… whereas the second conductive type is P type.) comprising a second gate electrode ([0019] the storage transmission gate line 102 includes … second gate line segments … 102b) coupled to a second semiconductor body ([0018] second active structures … F2) ([0019] the second gate line segment 102b intersects with the second active structures F2 from above the second active structures F2)
and the first NMOS and PMOS transistors comprise a first shared source or drain ([0019] The first … source/drain lines 104) coupled to the first (F1) and second (F2) semiconductor bodies, ([0019] The first and second source/drain lines 104 and 106 continuously extend to intersect the first and second active structures F1 and F2 from above the first and second active structures F1 and F2)
the first gate electrode (102a) and the second gate electrode (102b) are colinear, (See Fig. 1A)
and the second CMOS cell (See Fig. 3A, M1, lower) ([0038] Referring to FIG. 3A, the two memory cells MC1 arranged along the second direction DR2 are each substantially identical to the memory cell MC1 shown in FIG. 2A) comprises:
a second NMOS transistor ([0018] The first active structures F1 have a first conductive type, … For instance, in some embodiments, the first conductive type is N type) ([0019] ([0020] The first gate line 108, the second source/drain lines 106 and the third source/drain line 110 are functioned as terminals of the first inverter IV1 as shown in FIG. 1B.) ) comprising a third semiconductor body ([0018] first … active structures F1);
and a second PMOS transistor ([0018] whereas the second active structures F2 have a second conductive complementary to the first conductive type… whereas the second conductive type is P type.) ([0020] The first gate line 108, the second source/drain lines 106 and the third source/drain line 110 are functioned as terminals of the first inverter IV1 as shown in FIG. 1B.) ) comprising a fourth semiconductor body ([0018] second active structures … F2 ),
wherein the second NMOS and PMOS transistors comprise a second shared source or drain ([0019] second source/drain line 106) coupled to the third (F1) and fourth (F2) semiconductor bodies, ([0019] The first and second source/drain lines 104 and 106 continuously extend to intersect the first and second active structures F1 and F2 from above the first and second active structures F1 and F2.)
and the second NMOS and PMOS transistors comprise a shared third gate electrode ([0020] first gate line 108) coupled to the third (F1) and fourth (F2) semiconductor bodies. ([0030] The first gate line 108 continuously extends to intersect the first and second active structures F1 and F2 from above the first and second active structures F1 and F2)
However, Fujiwara fails to disclose the first and second transistor cells are over a substrate,
and a dielectric material separating the first gate electrode from the second gate electrode, and the dielectric material fills a gate cut between the first gate electrode and the second gate electrode;
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have the first and second transistor cells over a substrate. Fujiwara teaches that the transistors are FinFets ([0017] It should be noted that, each circuit element “transmission gate” mentioned in the present disclosure may include a complementary metal-oxide-semiconductor (CMOS) circuit having an N type MOSFET (e.g., a fin-type field effect transistor (finFET) of N type) and a P type MOSFET (e.g., a finFET of P type)) which are a well-known type of transistor, which are known to be built on a substrate.
However, Fujiwara still fails to disclose a dielectric material separating the first gate electrode from the second gate electrode, and the dielectric material fills a gate cut between the first gate electrode and the second gate electrode.
Jeong discloses (as shown in Fig. 2) a dielectric material ([0029] gate isolation layers IG1, IG2, IG3, and IG) separating the first gate electrode ([0027] second pass transistor PG2) from the second gate electrode ([0027] first pull-up transistor PU1), and the dielectric material (IG) fills a gate cut between the first gate electrode (PG2) and the second gate electrode (PU1). ([0035] The gate isolation layers IG1, IG2, IG3, and IG may be disposed between the gate lines GL spaced apart from each other in the second direction. A first gate isolation layer IG1 may be disposed between the first gate line GL1 and the fourth gate line GL4 in the first SRAM cell C1. )
Claim Interpretation Note: A gate cut is just a technique that creates a gap in an otherwise continuous gate. Therefore, claiming a gate cut is just claiming a spacing between the ends of the gates facing each other since the product claim does not care how the spacing is formed. (See MPEP 2113, Product-by-Process Claims)
Jeong teaches that the gate isolation layer (IG) is used to separate one gate line (GL) into two gates. ([0057] Thus, One gate line GL may be separated to two by the gate isolation layer IG.) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the teachings of Fujiwara and Jeong in to fill a gate cut with a dielectric material in order to separate a single gate line into two gates.
Regarding Claim 14, Fujiwara further discloses (as shown in Fig. An. 3A) wherein the first CMOS cell (MC1, upper) comprises a plurality of first NMOS transistors comprising first NMOS gate electrodes and a plurality of first PMOS transistors comprising first PMOS gate electrodes separated from the first NMOS gate electrodes, (See An. Fig. 3A, showing a plurality of first NMOS transistors and first PMOS transistors with separated gates)
and the second CMOS cell (MC1, lower) comprises a plurality of second NMOS transistors and a plurality of second PMOS transistors, wherein corresponding ones of the second NMOS and PMOS transistors comprise shared gate electrodes extending orthogonal to the third semiconductor body. (See An. Fig. 3A, showing a plurality of second NMOS transistors and second PMOS transistors with shared gates)
Jeong discloses (as shown in Fig. 2) a dielectric material ([0029] gate isolation layers IG1, IG2, IG3, and IG) separating the first NMOS gate electrode ([0027] second pass transistor PG2) from the first PMOS gate electrode ([0027] first pull-up transistor PU1), and the dielectric material (IG) fills a gate cut between the first gate electrode (PG2) and the second gate electrode (PU1). ([0035] The gate isolation layers IG1, IG2, IG3, and IG may be disposed between the gate lines GL spaced apart from each other in the second direction. A first gate isolation layer IG1 may be disposed between the first gate line GL1 and the fourth gate line GL4 in the first SRAM cell C1. )
Regarding Claim 22, Fujiwara further discloses (as shown in Fig. 3A) wherein the first NMOS transistor comprises a first channel region, ([0018] portion of the first … active structures F1 … are included in the memory cell MC.)
the first PMOS transistor comprises a second channel region, ([0018] portion of the … second active structures … F2 are included in the memory cell MC.)
the second NMOS transistor comprises a third channel region, ([0018] portion of the first … active structures F1 … are included in the memory cell MC.)
and the second PMOS transistor comprises a fourth channel region, ([0018] portion of the … second active structures … F2 are included in the memory cell MC.)
and wherein the first and third channel regions comprise a first material composition ([0038] Referring to FIG. 3A, the two memory cells MC1 arranged along the second direction DR2 are each substantially identical to the memory cell MC1 shown in FIG. 2A)
and the second and fourth channel regions comprise a second material composition. ([0038] Referring to FIG. 3A, the two memory cells MC1 arranged along the second direction DR2 are each substantially identical to the memory cell MC1 shown in FIG. 2A)
Regarding Claim 24, Fujiwara further discloses (as shown in Figs. 1A, 3A) wherein the second transistor cell (See fig. 3A, M1, lower) further comprises a third NMOS transistor and a third PMOS transistor, ([0021] The second gate line 112, the third source/drain lines 110 and the fourth source/drain line 114 are functioned as terminals of the second inverter IV2 as shown in FIG. 1B) ([0018] The first active structures F1 have a first conductive type, whereas the second active structures F2 have a second conductive complementary to the first conductive type. For instance, in some embodiments, the first conductive type is N type, whereas the second conductive type is P type.)
wherein the third NMOS transistor shares a source or drain ([0020] The third source/drain line 110 includes first … source/drain line segments 110a) with the second NMOS transistor (See Fig. 1A, showing source/drain line segment 110a shared by gates 108, 112)
and the third PMOS transistor shares a source or drain ([0020] The third source/drain line 110 includes … second source/drain line segments … 110b.) with the second PMOS transistor, (See Fig. 1A, showing source/drain line segment 110b shared by gates 108, 112) ([0018] The first active structures F1 have a first conductive type, whereas the second active structures F2 have a second conductive complementary to the first conductive type. For instance, in some embodiments, the first conductive type is N type, whereas the second conductive type is P type.)
and wherein the third NMOS and third PMOS transistors comprise a contiguous fourth gate electrode. ([0021] The second gate line 112 and the fourth source/drain line 114 continuously extend to intersect the first and second active structures F1 and F2 from above the first and second active structures F1 and F2)
Regarding Claim 25, Fujiwara further discloses (as shown in Figs. 1A, 3A) wherein the second transistor cell (See Fig. 3A, M1, lower) further comprises a fourth NMOS transistor comprising a fifth gate electrode coupled to the third semiconductor body, ([0019] The storage transmission gate line 102 and the first and second source/drain lines 104 and 106 are functioned as terminals of the storage transmission gate ST as shown in FIG. 1B…The first gate line segment 102a intersects with the first active structures F1 from above the first active structures F1) ([0018] The first active structures F1 have a first conductive type, whereas the second active structures F2 have a second conductive complementary to the first conductive type. For instance, in some embodiments, the first conductive type is N type, whereas the second conductive type is P type.)
and an fourth PMOS transistor comprising a sixth gate electrode coupled to the fourth semiconductor body, ([0019] The storage transmission gate line 102 and the first and second source/drain lines 104 and 106 are functioned as terminals of the storage transmission gate ST as shown in FIG. 1B…whereas the second gate line segment 102b intersects with the second active structures F2 from above the second active structures F2) ([0018] The first active structures F1 have a first conductive type, whereas the second active structures F2 have a second conductive complementary to the first conductive type. For instance, in some embodiments, the first conductive type is N type, whereas the second conductive type is P type.)
wherein the fifth (102a) and sixth (102b) gate electrodes are separated. (See Fig. 1A, showing 102a and 102b separated from each other)
However, Fujiwara fails to disclose the dielectric material separates the fifth gate electrode from the sixth gate electrode.
Jeong discloses a dielectric material separating the gate electrodes. ([0035] The gate isolation layers IG1, IG2, IG3, and IG may be disposed between the gate lines GL spaced apart from each other in the second direction. A first gate isolation layer IG1 may be disposed between the first gate line GL1 and the fourth gate line GL4 in the first SRAM cell C1.)
Regarding Claim 27, Jeong further discloses (as shown in Fig. 1) an integrated circuit die comprising the first CMOS cell and the second CMOS cell; and a power supply coupled to the integrated circuit die. ([0023] [0023] Referring to FIG. 1, an integrated circuit device 100 may include a pair of inverters INV1 and INV2 connected in parallel to each other between a power node Vcc and a ground node Vss)
Regarding Claim 28, Jeong further discloses (as shown in Fig. 1) an integrated circuit die comprising the first CMOS cell and the second CMOS cell; and a power supply coupled to the integrated circuit die. ([0023] [0023] Referring to FIG. 1, an integrated circuit device 100 may include a pair of inverters INV1 and INV2 connected in parallel to each other between a power node Vcc and a ground node Vss)
Claim(s) 3, 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara in view of Jeong as applied to claim 1 above, and further in view of Liaw (US 2022/0231145 A1) (previously cited)
Regarding Claim 3, Fujiwara in view of Jeong fails to disclose wherein the fourth transistor (108, F2) is to operate at a lower threshold voltage than the second transistor (102b, F1).
Liaw discloses (as shown in Figs. 2A-E, 3A-E) wherein the fourth transistor (PU-1) is to operate at a lower threshold voltage than the second transistor (PU-1). ([0056] a threshold voltage of p-type transistors PU-1, PU-2 of SRAM cell 400 is different than a threshold voltage of p-type transistors PU-1, PU-2 of SRAM cell 300. In some embodiments, the threshold voltage difference between the n-type transistors of the same type or the p-type transistors of the same type is about 30 mV to about 120 mV. Configuring a specific SRAM cell (such as SRAM cell 300 or 400) with transistors having lower threshold voltages (compared to transistors of the same type of other SRAM cells on the same memory chip) provides the specific SRAM cell with transistors that can be turned on at a lower power.) ([0057] In some embodiments, a threshold voltage of the transistors of SRAM cell 300 is lower than a threshold voltage of the same type of transistors of SRAM cell 400)
Liaw teaches that different threshold voltages are desirable for different applications. ([0022] Though each of SRAM cells 300, 400, and 500 (if present) share similar structures, they are designed to have different performance characteristics dedicated for different applications. Such different performance characteristics may be achieved by different physical dimensions and/or different material compositions. One important performance characteristic is threshold voltage of transistors… Advanced technologies generally benefit from a reduced threshold voltage, as it is an important scaling factor with respect to power efficiency. However, for low-power applications, a relatively high threshold voltage may be beneficial, as it reduces the leakage current and minimizes power consumption.) Therefore, it would have been obvious to a person having ordinary skill in the before the effective filing date of the application to have different threshold voltages in order to perform different applications.
Regarding claim 6, Fujiwara further discloses (as shown in Fig. 3A) wherein the contiguous third gate electrode (108) comprises a first region over the third semiconductor body (F1) and a second region over the fourth semiconductor body (F2) ([0020] The first gate line 108 continuously extends to intersect the first and second active structures F1 and F2 from above the first and second active structures F1 and F2)
However, Fujiwara in view of Jeong fails to disclose the first region comprising a first work function metal adjacent the third semiconductor body (F1) and the second region comprising a second work function metal adjacent the fourth semiconductor body (F2).
Liaw discloses (as shown in Figs. 2A-E, 3A-E) wherein the contiguous third gate electrode (See Fig 2B, showing the gate electrodes (330B, 330D) of the third (PD-1) and fourth (PU-1) transistors, respectively, are contiguous) comprises a first region (330B) over the third semiconductor body (320A) and a second region (330D) over the fourth semiconductor body (320B), (See Fig. 2B)
the first region (330B) comprising a first work function metal adjacent the third semiconductor body (320A) and the second region (330D) comprising a second work function metal adjacent the fourth semiconductor body (320B). ([0040] In some embodiments, one or more of gate electrodes 330A, 330B, 330E, and 330F include an n-type work function metal with a work function of about 4.0 eV to about 4.6 eV. In some embodiments, one or both gate electrodes 330C and 330D include a p-type work function metal with a work function of about 4.5 eV to about 5 eV.)
Liaw teaches that using work function metals can reduce the threshold voltage of the transistors. ([0022] Threshold voltage is largely determined by the difference in work function between the transistor channel semiconductor and the gate electrode. For a p-type transistor, a reduced threshold voltage may be achieved by utilizing a gate electrode material with a sufficiently high work function, such that the gate electrode work function approaches the valence band edge of the channel semiconductor. For an n-type transistor, a reduced threshold voltage may be achieved by utilizing a gate electrode material with a sufficiently low work function, such that the gate electrode work function approaches the conduction band edge of the channel semiconductor. In other words, threshold voltage of a transistor may be adjusted by proper selection of the gate electrode material based on their work functions.) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the teachings of Fujiwara in view of Jeong with Liaw to have the third transistor (which is n-type in Fujiwara) have an n-type work function gate metal and the fourth transistor (which is p-type in Fujiwara) have an p-type work function gate metal in order to reduce the threshold voltages.
Regarding Claim 7, Liaw further discloses (as shown in Figs. 2A-E, 3A-E) wherein the first (330B) and second (330D) region each comprises a common continuous fill metal over the first and second work function metals. ([0057] As described above with respect to FIGS. 2A-2E, the gate electrodes of the transistors of SRAM cell 300 may include a combination of p-type work function layer (such as a TiN layer), n-type work function layer (such as a TiAl layer), capping layer (such as a TaN layer), and metal fill layer (such as a W layer).)
Claim(s) 12-13, 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fujiwara in view of Jeong as applied to claim 11 above, and further in view of Liaw (US 2022/0231145 A1) (previously cited).
Regarding Claim 12, Fujiwara in view of Jeong fails to disclose wherein the second PMOS transistor (108, F2) is to operate at a lower threshold voltage than the First PMOS transistor (102b, F1).
Liaw discloses (as shown in Figs. 2A-E, 3A-E) wherein the fourth transistor (PU-1) is to operate at a lower threshold voltage than the second transistor (PU-1). ([0056] a threshold voltage of p-type transistors PU-1, PU-2 of SRAM cell 400 is different than a threshold voltage of p-type transistors PU-1, PU-2 of SRAM cell 300. In some embodiments, the threshold voltage difference between the n-type transistors of the same type or the p-type transistors of the same type is about 30 mV to about 120 mV. Configuring a specific SRAM cell (such as SRAM cell 300 or 400) with transistors having lower threshold voltages (compared to transistors of the same type of other SRAM cells on the same memory chip) provides the specific SRAM cell with transistors that can be turned on at a lower power.) ([0057] In some embodiments, a threshold voltage of the transistors of SRAM cell 300 is lower than a threshold voltage of the same type of transistors of SRAM cell 400)
Liaw teaches that different threshold voltages are desirable for different applications. ([0022] Though each of SRAM cells 300, 400, and 500 (if present) share similar structures, they are designed to have different performance characteristics dedicated for different applications. Such different performance characteristics may be achieved by different physical dimensions and/or different material compositions. One important performance characteristic is threshold voltage of transistors… Advanced technologies generally benefit from a reduced threshold voltage, as it is an important scaling factor with respect to power efficiency. However, for low-power applications, a relatively high threshold voltage may be beneficial, as it reduces the leakage current and minimizes power consumption.) Therefore, it would have been obvious to a person having ordinary skill in the before the effective filing date of the application to have different threshold voltages in order to perform different applications.
Regarding Claim 13, Fujiwara in view of Jeong and Sohn fail to disclose wherein the first PMOS transistor is to operate at a threshold voltage of not more than 250 mV and the second PMOS transistor is to operate at a threshold voltage of not more than 200 mV.
Liaw discloses (as shown in Figs. 2A-E, 3A-E) wherein the first PMOS transistor is to operate at a threshold voltage of not more than 250 mV ([0038] p-type transistors PU-1 and/or PU-2 may have a threshold voltage of about 0.2 V to about 0.4 V)
and the second PMOS transistor is to operate at a threshold voltage of not more than 200 mV. ([0038] In some implementations, the threshold voltage difference of p-type transistors of SRAM cell 300 relative to p-type transistors of the same type of other SRAM cells on the same memory chip may be 30 mV to 120 mV.
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have the threshold voltage of the second PMOS transistor (PU-1 of 300) to have a threshold voltage of not more than 200 mV. Liaw teaches that the threshold voltage is between 200 and 400 mV ([0038] p-type transistors PU-1 and/or PU-2 may have a threshold voltage of about 0.2 V to about 0.4 V) and this range overlaps with the claimed range at 200 mV.
It would also have been obvious to a person having ordinary skill in the art before the effective filing date of the application to have the threshold voltage of the first PMOS transistor (PU-1 of 400) to have a threshold voltage of not more than 250 mV. Liaw teaches that the PMOS transistor of the SRAM 300 is between 30 and 120 mV below the threshold voltage of the SRAM 400 ([0038] In some implementations, the threshold voltage difference of p-type transistors of SRAM cell 300 relative to p-type transistors of the same type of other SRAM cells on the same memory chip may be 30 mV to 120 mV.) This range overlaps with the claimed range when the PMOS transistor of SRAM 300 is on the low end (For example if the PMOS of the SRAM 300 is 200 mV is 30 mV lower than the PMOS transistor of SRAM 300)
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the teachings of Fujiwara in view of Jeong and Sohn with Liaw. Fujiwara in view of Jeong and Sohn fail to disclose the threshold voltages of the p-type transistors in the SRAM device. Liaw teaches that the voltages of the p-type transistors in the SRAM cell are between 0.2 and 0.4 V. ([0038] In some embodiments, p-type transistors PU-1 and/or PU-2 may have a threshold voltage of about 0.2 V to about 0.4 V. In some implementations, the threshold voltage difference of p-type transistors of SRAM cell 300 relative to p-type transistors of the same type of other SRAM cells on the same memory chip may be 30 mV to 120 mV.) It would have been obvious to use the threshold voltages of the p-type transistors of the SRAM cell in Liaw in the p-type transistors of the SRAM cell in Fujiwara in view of Jeong and Sohn.
Regarding claim 23, Fujiwara further discloses (as shown in Fig. 3A) wherein the shared third gate electrode (108) comprises a first region over the third semiconductor body (F1) and a second region over the fourth semiconductor body (F2) ([0020] The first gate line 108 continuously extends to intersect the first and second active structures F1 and F2 from above the first and second active structures F1 and F2.)
However, Fujiwara in view of Jeong fails to disclose the first region comprising a first work function metal adjacent the third semiconductor body (F1) and the second region comprising a second work function metal adjacent the fourth semiconductor body (F2)
and wherein the first and second region each comprises a common continuous fill metal over the first and second work function metals.
Liaw discloses (as shown in Figs. 2A-E, 3A-E) wherein the contiguous third gate electrode (See Fig 2B, showing the gate electrodes (330B, 330D) of the third (PD-1) and fourth (PU-1) transistors, respectively, are contiguous) comprises a first region (330B) over the third semiconductor body (320A) and a second region (330D) over the fourth semiconductor body (320B), (See Fig. 2B)
the first region (330B) comprising a first work function metal adjacent the third semiconductor body (320A) and the second region (330D) comprising a second work function metal adjacent the fourth semiconductor body (320B). ([0040] In some embodiments, one or more of gate electrodes 330A, 330B, 330E, and 330F include an n-type work function metal with a work function of about 4.0 eV to about 4.6 eV. In some embodiments, one or both gate electrodes 330C and 330D include a p-type work function metal with a work function of about 4.5 eV to about 5 eV.)
wherein the first (330B) and second (330D) region each comprises a common continuous fill metal over the first and second work function metals. ([0057] As described above with respect to FIGS. 2A-2E, the gate electrodes of the transistors of SRAM cell 300 may include a combination of p-type work function layer (such as a TiN layer), n-type work function layer (such as a TiAl layer), capping layer (such as a TaN layer), and metal fill layer (such as a W layer).)
Liaw teaches that using work function metals can reduce the threshold voltage of the transistors. ([0022] Threshold voltage is largely determined by the difference in work function between the transistor channel semiconductor and the gate electrode. For a p-type transistor, a reduced threshold voltage may be achieved by utilizing a gate electrode material with a sufficiently high work function, such that the gate electrode work function approaches the valence band edge of the channel semiconductor. For an n-type transistor, a reduced threshold voltage may be achieved by utilizing a gate electrode material with a sufficiently low work function, such that the gate electrode work function approaches the conduction band edge of the channel semiconductor. In other words, threshold voltage of a transistor may be adjusted by proper selection of the gate electrode material based on their work functions.) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the teachings of Fujiwara in view of Jeong with Liaw to have the third transistor (which is n-type in Fujiwara) have an n-type work function gate metal and the fourth transistor (which is p-type in Fujiwara) have an p-type work function gate metal in order to reduce the threshold voltages.
Allowable Subject Matter
Claim 10, 26 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 10, Fujiwara further discloses (as shown in Figs. 1A, 3A) wherein the second transistor cell (See Fig. 3A, M1, lower) further comprises a seventh transistor comprising a fifth gate electrode coupled to the third semiconductor body, ([0019] The storage transmission gate line 102 and the first and second source/drain lines 104 and 106 are functioned as terminals of the storage transmission gate ST as shown in FIG. 1B) ([0019] The first gate line segment 102a intersects with the first active structures F1 from above the first active structures F1)
and an eighth transistor comprising a sixth gate electrode coupled to the fourth semiconductor body, ([0019] The storage transmission gate line 102 and the first and second source/drain lines 104 and 106 are functioned as terminals of the storage transmission gate ST as shown in FIG. 1B) ([0019] whereas the second gate line segment 102b intersects with the second active structures F2 from above the second active structures F2)
However, Fujiwara fails to disclose wherein the seventh transistor shares a source or drain with the fifth transistor and the eighth transistor shares a source or drain with the sixth transistor, and wherein the seventh and eighth transistors comprise a contiguous fifth gate electrode.
Furthermore, neither Jeong nor Liaw fix this deficiency. For this reason, Claim 10 contains allowable subject matter.
Regarding Claim 26, Fujiwara further discloses (as shown in Fig. 1A, 3A)
wherein the second transistor cell (See Fig. 3A, M1, lower) further comprises a fourth NMOS transistor comprising a fifth gate electrode coupled to the third semiconductor body, ([0019] The storage transmission gate line 102 and the first and second source/drain lines 104 and 106 are functioned as terminals of the storage transmission gate ST as shown in FIG. 1B) ([0019] The first gate line segment 102a intersects with the first active structures F1 from above the first active structures F1)
and an fourth PMOS transistor comprising a sixth gate electrode coupled to the fourth semiconductor body, ([0019] The storage transmission gate line 102 and the first and second source/drain lines 104 and 106 are functioned as terminals of the storage transmission gate ST as shown in FIG. 1B) ([0019] whereas the second gate line segment 102b intersects with the second active structures F2 from above the second active structures F2)
However, Fujiwara fails to disclose wherein the fourth NMOS transistor shares a source or drain with the third NMOS transistor and the fourth PMOS transistor shares a source or drain with the third PMOS transistor, and wherein the fourth NMOS transistor and the fourth PMOS transistor comprise a contiguous fifth gate electrode.
Furthermore, neither Jeong nor Liaw fix this deficiency. For this reason, Claim 26 contains allowable subject matter.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JASON JAMES GREAVING/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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