Prosecution Insights
Last updated: April 19, 2026
Application No. 17/956,343

CURRENT LIMITER CIRCUIT WITH ADJUSTABLE RESPONSE TIME

Non-Final OA §102§112
Filed
Sep 29, 2022
Examiner
BELLIDO, NICOLAS G
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
2 (Non-Final)
89%
Grant Probability
Favorable
2-3
OA Rounds
2y 6m
To Grant
99%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allow Rate
288 granted / 324 resolved
+20.9% vs TC avg
Moderate +13% lift
Without
With
+13.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
11 currently pending
Career history
335
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
43.7%
+3.7% vs TC avg
§102
28.7%
-11.3% vs TC avg
§112
23.6%
-16.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 324 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on November 04, 2025 has been entered. Drawings The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitations of claim 1 “an amplifier having an input coupled to a first current terminal and an amplifier output, the amplifier output coupled to a switch control terminal; and a switch coupled between the switch control terminal and a second current terminal, the switch having a control terminal coupled to the amplifier output”; the limitations of claim 2 “a fourth switch coupled between the first and second current terminals, a control terminal of the fourth switch being the switch control terminal”; the limitations of claim 9 “a first switch having a first control terminal and first and second current terminals, the first current terminal coupled to the port; an amplifier having an input coupled to the first current terminal and an amplifier output, the amplifier output coupled to the first control terminal; and a second switch coupled between the first control terminal and the second current terminal, the second switch having a second control terminal coupled to the amplifier output”; and claim 18 “wherein the switch is a first switch, the current terminal is a first current terminal, the control terminal is a first control terminal, the first switch has a second current terminal, and the circuit further comprises a second switch coupled between the control terminal and the second current terminal, the second switch has a second control terminal coupled to the current limiter circuit” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL. - The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claim(s) 17 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Regarding claim 17, the limitation “a current limiter circuit having an input coupled to the current terminal and an output coupled to the control terminal, the current limiter circuit configurable to adjust a voltage at the control terminal at a first rate responsive to a current at the current terminal exceeding a first threshold and adjust the voltage at a second rate responsive to the current exceeding a second threshold” does not appear to have support in the originally filed disclosure. The applicant’s specification disclose various examples (embodiments), however fails to disclose “the current limiter circuit configurable to adjust a voltage at the control terminal at a first rate responsive to a current at the current terminal exceeding a first threshold and adjust the voltage at a second rate responsive to the current exceeding a second threshold”. The disclosure does not demonstrate that applicant has made an invention that achieves the claimed function because the invention is not described with sufficient detail such that one of ordinary skill in the art can reasonably conclude that the inventor has in possession of the claimed invention. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION. —The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim(s) 1-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. With regard to claim 1, recite the following limitations “an amplifier having an input coupled to a first current terminal and an amplifier output, the amplifier output coupled to a switch control terminal; and a switch coupled between the switch control terminal and a second current terminal, the switch having a control terminal coupled to the amplifier output” which renders the claim vague and indefinite. It is unclear because the applicant’s specification does not define the “first current terminal”, “switch control terminal”, “second current terminal”, and which component is “a switch coupled between the switch control terminal and a second current terminal, the switch having a control terminal coupled to the amplifier output”. A question is raised, so the Figures are correct or the instant language? Clarification is required. Claim(s) 2-8 are indefinite by dependence on claim 1. With regard to claim 9, recite the following limitations “a first switch having a first control terminal and first and second current terminals, the first current terminal coupled to the port; an amplifier having an input coupled to the first current terminal and an amplifier output, the amplifier output coupled to the first control terminal; and a second switch coupled between the first control terminal and the second current terminal, the second switch having a second control terminal coupled to the amplifier output” which renders the claim vague and indefinite. It is unclear because the applicant’s specification does not define the “first switch”, “first control terminal”, “first and second current terminals”, “the first current terminal coupled to the port”, “amplifier having an input coupled the first current terminal”, “the amplifier output coupled to the first control terminal”, and which component is “a second switch coupled between the first control terminal and the second current terminal, the second switch having a second control terminal coupled to the amplifier output”. A question is raised, so the Figures are correct or the instant language? Clarification is required. Claim(s) 10-16 are indefinite by dependence on claim 9. With regard to claim 17, the limitation “a current limiter circuit having an input coupled to the current terminal and an output coupled to the control terminal” which renders the claim vague and indefinite. Figs. 1-3 teach a current limiter (104) (for details see Fig. 4), it is unclear if the claimed “current limiter circuit” is the current limiter (104). The current limiter (104) comprises: a power switch (M1, M2), an amplifier (206), a gain adjustment circuit (208), and a speedup circuit (210). It is unclear how the current limiter circuit having an input coupled to the current terminal and an output coupled to the control terminal of the switch. A question is raised, so the Figures are correct or the instant language? Clarification is required. Claim(s) 18-19 are indefinite by dependence on claim 17. With regard to claim 18, recite the following limitations “the switch is a first switch, the current terminal is a first current terminal, the control terminal is a first control terminal, the first switch has a second current terminal, and the circuit further comprises a second switch coupled between the control terminal and the second current terminal, the second switch has a second control terminal coupled to the current limiter circuit” which renders the claim vague and indefinite. Figs. 1-3 teach a current limiter (104) (for details see Fig. 4), it is unclear if the claimed “current limiter circuit” is the current limiter (104). The current limiter (104) comprises: a power switch (M1, M2), an amplifier (206), a gain adjustment circuit (208), and a speedup circuit (210). It is unclear the limitation “the second switch has a second control terminal coupled to the current limiter circuit”. A question is raised, so the Figures are correct or the instant language? Clarification is required. Examiner’s Note: If the examiner is incorrect and the claims were drafted correctly, a brief explanation as to where the claim is taught in the specification would be helpful to overcome the rejection under 35 U.S.C. 112(b). The dependent claims necessarily inherit the indefiniteness of the claims on which they dependent. Examination Notice In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were effectively filed absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned at the time a later invention was effectively filed in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 9 and 17-19 are rejected under 35 U.S.C. 102 (a)(1) and 35 U.S.C. 102 (a)(2) as being anticipated by Matyscak (US 11,281,244 B2). With regard to claim 1, Matyscak teaches an apparatus (Abstract, lines 1-2) comprising: an amplifier (120 – Fig. 1) having an input (+ 120 – Fig. 1) coupled to a first current terminal (right terminal of 110 – Fig. 1) and an amplifier output (121 – Fig. 1), the amplifier output (121 – Fig. 1) coupled to a switch control terminal (switch control terminal of M0 – Fig. 2); and a switch (110 – Fig. 1, Fig. 2) coupled between the switch control terminal (switch control terminal of M0 – Fig. 2) and a second current terminal (left terminal of 110 – Fig. 1), the switch (110 – Fig. 1, Fig. 2) having a control terminal (control terminal of 110 – Fig. 1) coupled to the amplifier output (121 – Fig. 1) (coupled via 140). With regard to claim 9, Matyscak teaches a system (Fig. 1 – Fig. 4) comprising: a port (OUT – Fig. 1; 201 – Fig. 2-Fig. 3); a first switch (110 – Fig. 1, Fig. 2) having a first control terminal (control terminal of 110 – Fig. 1) and first and second current terminals (right and left terminals of 110 – Fig. 1), the first current terminal (right terminal of 110 – Fig. 1; lower terminal of 110 Fig. 2) coupled to the port (OUT – Fig. 1; 201 – Fig. 2-Fig. 3); an amplifier (120 – Fig. 1) having an input (+ 120 – Fig. 1) coupled to the first current terminal (right terminal of 110 – Fig. 1) and an amplifier output (121 – Fig. 1), the amplifier output (121 – Fig. 1) coupled to the first control terminal (first control terminal of M0 – Fig. 2); and a second switch (M10 – Fig. 2) coupled between the first control terminal (first control terminal of M0 – Fig. 2) and the second current terminal (upper terminal of 110 – Fig. 2), the second switch (M10 – Fig. 2) having a second control terminal (second control terminal of M10 – Fig. 2) coupled to the amplifier output (121 – Fig. 1) (electrically coupled). With regard to claim 17, Matyscak teaches a circuit (Abstract, lines 1-2), comprising: a switch (110 – Fig. 1) having a current terminal (left terminal of 110 – Fig. 1) and a control terminal (111 – Fig. 1); and a current limiter circuit (140 – Fig. 1) having an input (input to receive IQ3 – Fig. 1) coupled to the current terminal (left terminal of 110 – Fig. 1) and an output (output of 140 coupled to the control terminal of 110 – Fig. 1) coupled to the control terminal (111 – Fig. 1), the current limiter circuit (140 – Fig. 1) configurable to adjust a voltage (col. 4, lines 34-45) at the control terminal (111 – Fig. 1) at a first rate responsive to a current at the current terminal exceeding a first threshold (col. 3, lines 48-53) and adjust the voltage at a second rate responsive to the current exceeding a second threshold (col. 4, lines 25-33). With regard to claim 18, Matyscak teaches all the limitations of claim 17, and further teaches the switch (110 – Fig. 1) is a first switch, the current terminal (left terminal of 110 – Fig. 1, upper terminal of 110 – Fig. 2) is a first current terminal, the control terminal (111 – Fig. 1) is a first control terminal, the first switch has a second current terminal (right terminal of 110 – Fig. 1), and the circuit further comprises a second switch (M1 – Fig. 2) coupled between the control terminal (111 – Fig. 1) and the second current terminal (right terminal of 110 – Fig. 1; lower terminal of 110 – Fig. 2), the second switch (M1 – Fig. 2) has a second control terminal (lower terminal of M1 – Fig. 1) coupled to the current limiter circuit (140 – Fig. 1). With regard to claim 19, Matyscak teaches all the limitations of claim 17, and further teaches the current limiter circuit includes: an amplifier (120 – Fig. 1) having an input (- 120 – Fig. 1) coupled to the input (input to receive IQ3 – Fig. 1) of the current limiter circuit (140 – Fig. 1); and one or more current mirror circuits (M11, M12 – Fig. 2) coupled between an output (121 – Fig. 1) of the amplifier circuit (120 – Fig. 1) and the output (output of 140 coupled to 111 – Fig. 1) of the current limiter circuit (140 – Fig. 1). Allowable Subject Matter Claim(s) 2-8 and 10-16 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: With regard to claim 2, in combination with other limitations of the claim, the prior art fails to teach or fairly suggest “wherein the switch is a first switch, and the circuit further comprises a first current mirror having an input and an output; a second switch having a first terminal coupled to the amplifier output and having a second terminal coupled to the input of the first current mirror; a second current mirror having an input and an output; a third switch having a first terminal coupled to the amplifier output and having a second terminal coupled to input of the second current mirror; and a fourth switch coupled between the first and second current terminals, a control terminal of the fourth switch being the switch control terminal, wherein: the input is a first input, the amplifier has a second input and comprises a transconductance amplifier configured to receive a first voltage at a first input and a second voltage at a second input, wherein the first voltage represents a current at the first current terminal.” Claim(s) 3-8 are allowed by dependence on claim 1. With regard to claim 10, in combination with other limitations of the claim, the prior art fails to teach or fairly suggest “the amplifier comprises a transconductance amplifier configured to receive a first voltage at the first amplifier input and a reference voltage at the reference input; and the first voltage represents a current at the current terminal of the first switch.” Claim(s) 11 is allowed by dependence on claim 10. With regard to claim 12, in combination with other limitations of the claim, the prior art fails to teach or fairly suggest “a first current mirror having an input and an output; a third switch having a first terminal coupled to the amplifier output and having a second terminal coupled to the input of the first current mirror; a second current mirror having an input and an output; a fourth switch having a first terminal coupled to the amplifier output and having a second terminal coupled to input of the second current mirror; and a resistor coupled between the first control terminal and the outputs of the first and second current mirrors.” Claim(s) 13-15 are allowed by dependence on claim 12. With regard to claim 16, in combination with other limitations of the claim, the prior art fails to teach or fairly suggest “the first current mirror is configurable to conduct a current from the first control terminal at a first rate responsive to the third switch being closed, and the second current mirror is configurable to conduct a current from the first control terminal at a second rate responsive to the fourth switch being closed, the second rate being different from the first rate, and the system further includes: a fifth switch having a first terminal coupled to the amplifier output and having a second terminal; and a third current mirror having an input coupled to the second terminal of the fourth switch and having an output coupled to the first control terminal, wherein the third current mirror is configurable to conduct a current from the first control terminal at a third rate responsive to the fifth switch being closed, the third rate being different from the first rate and the second rate.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please see attached PTO-892. Ideno (US 2020/0081466 A1) teaches a semiconductor integrated circuit includes an output transistor, an error amplifier, a replica transistor, a current-limiting circuit, and a potential regulation circuit. The output transistor is electrically connected between a power supply-side first node and an output-side second node. The replica transistor is electrically connected between the first node and a fourth node. The replica transistor constitutes a circuit that is configured to operate to correspond to the output transistor. The current-limiting circuit has an input node, that is electrically connected to a fifth node between the fourth node and a first current source, and an output node that is electrically connected to a gate of the output transistor and a gate of the replica transistor. The potential regulation circuit is electrically connected to the second node and the fourth node. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nicolas Bellido whose telephone number is (571) 272-5034. The examiner can normally be reached Monday to Friday from 9:00 am to 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call (800) 786-9199 (IN USA OR CANADA) or (57) 272-1000. /N.B./Examiner, Art Unit 2838 /Scott Bauer/Primary Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

Sep 29, 2022
Application Filed
Jan 31, 2025
Request for Continued Examination
Feb 03, 2025
Response after Non-Final Action
Apr 01, 2025
Non-Final Rejection — §102, §112
Jul 08, 2025
Response Filed
Nov 04, 2025
Request for Continued Examination
Nov 11, 2025
Response after Non-Final Action
Jan 06, 2026
Non-Final Rejection — §102, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
89%
Grant Probability
99%
With Interview (+13.1%)
2y 6m
Median Time to Grant
Moderate
PTA Risk
Based on 324 resolved cases by this examiner. Grant probability derived from career allow rate.

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