DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
In claim 10, at line 3: replace “co” with “couple” in order to correct a typographical error.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 and 14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 1 and claim 14, the phrase “agnostic of physical layer circuitry” lacks objective boundaries. It is unclear whether “agnostic” means: the design does not include physical elements, the design not reference physical parameters, the design can operate with any physical element/parameters, or the designer simply ignores physical details at design time. Furthermore, the claims do not define how much physical knowledge is too much to lose agnosticism.
Claims 2-9 are rejected for their dependency on rejected base claim 1.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-11 and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Pub. No. 2019/0138680 to Teh et al. (“Teh").
As to independent claim 1, an article of manufacture comprising one or more tangible, non-transitory, machine-readable media having instructions stored thereon that, when executed by one or more processors, cause the one or more processors to (Fig. 1, 2 teach these components.): model a circuit design for an integrated circuit system (¶ 0017-0022, Fig. 3. Teh teaches modeling/generating a circuit design for an IC system using design software. Teh states the designer may use the design software 204 to generate a design and the device may be programmed to implement a circuit design (e.g., higher-level circuit design). The further explains the design software and complier operate on an integrated circuit device 102, which is a disaggregated, multi-die IC system including programmable fabric dies and periphery IP tiles.), wherein the circuit design is agnostic of physical layer circuitry of the integrated circuit system (¶ 0019, 0027, 0029. Teh teaches the circuit design is independent of, and does not require modeling of, the physical die-to-die interface circuitry. Teh repeatedly emphasizes despite the presence of the physical interface structures; the IC device may appear and be programmed as a monolithic IC. This satisfies the “agnostic” limitation because the software abstracts the complex physical layer (separate fabric dies and periphery tiles) from the designer, allowing them to model the circuit without regard for physical separation.); generate configuration data based on the circuit design (¶ 0023. Teh teaches a complier generating configuration data based on the designer specified functionality.); and transfer the configuration data to the integrated circuit system to cause programmable logic of the integrated circuit system to implement the circuit design (¶ 0023, 0025. Teh teaches loading the bitstream onto the device, which configures the programmable logic (fabric) to implement the design.).
As to claim 2, the article of manufacture of claim 1, wherein the instructions, when executed by the one or more processors, cause the one or more processors to model the circuit design without modeling the physical layer circuitry (¶ 0019. Teh treats the device as monolithic, resulting in a model that ignores (i.e., is without modeling) the actual physical layer circuitry.).
As to claim 3, the article of manufacture of claim 1, wherein the instructions, when executed by the one or more processors, cause the one or more processors to model the circuit design with a die-to-die adapter layer (¶ 0029. Teh teaches modeling a circuit design with a die-to-die adapter layer by disclosing a standardized modular interface that adapts communication between dies and is included in the system architecture during design and compilation even though it is abstracted from user authored logic.).
As to claim 4, the article of manufacture of claim 3, wherein the die-to-die adapter layer includes circuitry comprising advanced interface bus (AIB) circuitry, universal interconnect bus (UIB) circuitry, or both (¶ 0029).
As to claim 5, the article of manufacture of claim 1, wherein the circuit design is associated with a first chiplet configurable to communicatively couple to an integrated circuit die of the integrated circuit system (¶ 0017, 0018, 0022, 0029. Teh teaches the circuit design generated by the design software is associated with a first chiplet (e.g., periphery IP tile), which is configurable to communicatively couple to an IC die via a standardized die-to-die interface.).
As to claim 6, the article of manufacture of claim 5, wherein the integrated circuit die comprises the programmable logic (¶ 0017, 0025, Fig. 3: 302X. Teh teaches the IC die comprises programmable logic by explicitly teaching programmable fabric dies within the IC device.).
As to claim 7, the article of manufacture of claim 5, wherein the instructions, when executed by the one or more processors, cause the one or more processors to: model a second circuit design for the integrated circuit system, wherein the second circuit design is associated with a second chiplet configurable to communicatively couple to the integrated circuit die (¶ 0017, 0018, 0022, 0029. Teh teaches executing instructions that model circuit designs for an integrated circuit system, where each circuit design is associated with a different chiplet configurable to communicatively couple an integrated circuit die. Teh discloses a modularized IC device comprising multiple tiles (chiplets) and design software that models and programs the device as if monolithic, inherently modeling circuit designs associated with multiple chiplets that are communicatively coupled via die-to-die interface.).
As to claim 8, the article of manufacture of claim 7, wherein the integrated circuit die comprises the physical layer circuitry (¶ 0017, 0018, 0029, 0036. Teh teaches the device include periphery IP tiles, and the periphery IP tile may include hard IP blocks. Teh further teaches die-to-die interface circuitry including bidirectional I/O buffers associated with AIB-D interfaces.).
As to claim 9, the article of manufacture of claim 7, wherein the instructions, when executed by the one or more processors, cause the one or more processors to model the second circuit design without modeling the physical layer circuitry (¶ 0019, 0022, 0027, 0029. Because the communication interface is defined by a specification, the designer facing circuit design does not require modeling of the physical layer details (e.g., AIB-D, I/O buffers, microbumps), which are abstracted from the design flow.).
As to independent claim 10, an integrated circuit system (Fig. 1, 2 disclose a system.), comprising: a chiplet (¶ 0017, Fig. 3: Periphery IP Tile 304); and an integrated circuit die configurable to communicatively co to the chiplet (¶ 0019, Fig. 3: Programmable Fabric Die 302X. 304 and 302X are configurable to communicatively couple via interposer.), the integrated circuit die comprising programmable logic fabric configurable to implement a circuit design (¶ 0017, 0025. Programmable fabric die comprise programmable logic to implement a circuit design.), wherein the integrated circuit die receives configuration data based on the circuit design (¶ 0023, 0025. Compiler 206 provides instructions in the form of a configuration bitstream 208. The programmable logic receives the bitstream and may be configured in accordance with the circuit design embodied by the configuration bitstream.), and wherein the circuit design does not model physical layer circuitry associated with the integrated circuit die (¶ 0017-0019, 0027, 0029. The programmable device may appear and be programmed as a monolithic IC. The circuit design is modeled without modeling the physical layer circuitry associated with the die.).
As to claim 11, the integrated circuit system of claim 10, wherein the chiplet comprises a custom chiplet (¶ 0026).
As to independent claim 17, a method of preparing an integrated circuit (¶ 0022. Teh discloses an IC design process.), comprising: generating configuration data based on a user design for an integrated circuit system (¶ 0017, 0023. Teh teaches the design software uses compiler 206 to generate a lower-level circuit design configuration, and the compiler provides instructions in the form of a configuration bitstream. The user design and resulting configuration data are for an integrated circuit system, not a single monolithic die.) that is independent of physical layer circuitry of an integrated circuit die of the integrated circuit system (¶ 0017-0019, 0027, 0029. The programmable device may appear and be programmed as a monolithic IC. The circuit design is modeled without modeling the physical layer circuitry associated with the die.); and transferring the configuration data to the integrated circuit system to cause a portion of programmable logic of the integrated circuit die to implement the user design (¶ 0017-0025. Teh teaches the host processors coordinate the loading of the bitstream on the IC device (i.e., transferring the configuration data). The programmable logic receives the configuration bitstream and is configured in accordance with the circuit design embodied by the configuration bitstream.).
As to claim 18, the method of claim 17, wherein the user design is associated with a first chiplet configurable to communicatively couple to the integrated circuit die via the physical layer circuitry (¶ 0017-0029. Teh teaches the user design is associated with a first periphery IP tile that is configurable to communicatively couple to a programmable fabric die via physical layer circuitry (e.g. AIB-D interfaces, I/O buffers, microbumps, interposer).).
As to claim 19, the method of claim 18, comprising: generating second configuration data based on a second user design associated with a second chiplet, wherein the second user design is independent of the physical layer circuitry; and transferring the second configuration data to the integrated circuit system to cause a second portion of programmable logic of the integrated circuit die to implement the second user design (¶ 0017-0029. Teh teaches using design software and a complier to generate a configuration bitstream for modularized IC device that is disaggregated into multiple tiles, including programmable fabric dies and periphery IP tiles. Teh further teaches the device is programmed as if monolithic because the communication interface is defined by the specification, such that the circuit design is independent of physical interface circuitry (e.g., AIB-D interfaces, I/O buffers). Teh also teaches loading the configuration bitstream onto the integrated circuit device to configure the programmable logic in accordance with the circuit design. Accordingly, Teh teaches generating configuration data for multiple circuit designs associated with multiple tiles and transferring the configuration data to configure respective portions of programmable logic.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 12-16 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Teh in view of US Patent No. 10,909,652 to Koker et al. (“Koker”).
Teh teaches the limitations of claims 10 and 17 from which claims 12 and 20 depend. Teh does not teach the integrated circuit die is associated with a first manufacturer and the custom chiplet is associated with a second manufacturer, as required by claim 12 and similarly recited claim 20.
Koker teaches the concept of sourcing chiplets/die from different entities (“IP designers”) to be assembled into a single system (Abstract).
It would have been obvious to one of ordinary skill in the art to have modified Teh's system to include chiplets from a different/second manufacturer because it allows the integrator to use the “best” components available and may reduce time to market.
As to claim 13 and similarly recited claim 20, the integrated circuit system of claim 12, comprising: a first chiplet configurable to communicatively couple to the integrated circuit die; and a second chiplet configurable to communicatively couple to the integrated circuit die (¶ 0017-0019, 0029. Teh teaches multiple IP tiles and multiple programmable fabric dies each communicatively coupled via the same standardized direct interface.).
As to claim 14, the integrated circuit system of claim 13, wherein: the integrated circuit die is configurable to implement a first circuit design associated with the first chiplet and agnostic of the physical layer circuitry of the integrated circuit die; and the integrated circuit die is configurable to implement a second circuit design associated with the second chiplet and agnostic of the physical layer circuitry of the integrated circuit die (¶ 0017-0029. Teh teaches an IC die is configurable to implement multiple circuit designs, each associated with a respective chiplet, and that such circuit designs are modeled and programmed without modeling the physical layer circuitry because the system is programmed “as if monolithic”.).
As to claim 15, the integrated circuit system of claim 13, wherein the first chiplet is associated with a first manufacturer and the second chiplet is associated with a second manufacturer (Koker: Abstract).
As to claim 16, the integrated circuit system of claim 13, wherein the first chiplet is associated with a first manufacturer and the integrated circuit die is associated with a second manufacturer (Koker: Abstract).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Examiner SURESH MEMULA whose telephone number is (571)272-8046, and any inquiry for a formal Applicant initiated interview must be requested via a PTOL-413A form and faxed to the Examiner's personal fax phone number: (571) 273-8046. Furthermore, Applicant is invited to contact the Examiner via email (suresh.memula@uspto.gov) on the condition the communication is pursuant to and in accordance with MPEP §502.03 and §713.01. The Examiner can normally be reached Monday-Thursday: 9am-6pm. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, Jack Chiang, can be reached on 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned (i.e., central fax phone number) is 571-273-8300.
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/SURESH MEMULA/Primary Examiner, Art Unit 2851