DETAILED ACTION
The instant application having Application No. 17/956,387 filed on 9/29/2022 is presented for examination by the examiner. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Figures 1-3 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g).
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 9-14, and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Arps et al. (US 4,792,954).
As per Claim 1, Arps discloses a signal processing circuit, comprising: a sender circuit configured to: receive an input signal, transform the input signal to a first protected signal by multiplying an input value of the input signal by a first integer number greater than 2, and transmit the first protected signal (Abstract and Figures 1, 3 and Column 1, lines 11-19 and Column 3, lines 12-23 and Column 4, lines 6-12 and Column 8, lines 3-9, an encoder circuit shown in Figure 3 multiplies a signal 2-k by a scaling value n via multiplier 62 and transmits the resulting signal C’(s) over a channel);
a receiver circuit configured to: receive a second protected signal, transform the second protected signal to an output signal by dividing a protected value of the second protected signal by a second integer number greater than 2, determine whether an output value of the output signal is an integer number, and transmit the output signal in response to determining that the output value is an integer number, or transmit an error signal in response to determining that the output value is not an integer number (Figures 1, 6 and Column 1, lines 11-19 and Column 3, lines 12-23 and Column 4, lines 6-12 and Column 7, lines 62-68 and Column 8, lines 27-42 and Column 11, lines 16-19, a decoder circuit shown in Figure 6 receives signal C’(s), determines if the signal is divisible by integer n via modulo-n circuit 102, and outputs an error signal via comparator 103 if the signal is not divisible by n, i.e. modulo-n calculation is nonzero).
As per Claim 2, Arps discloses the signal processing circuit of claim 1, wherein at least one of the first integer number or the second integer number is an odd number (Abstract and Column 3, lines 15-25 and Column 4, lines 7-12 and 20-25, n is an odd integer not equal to +1 or -1).
As per Claim 3, Arps discloses the signal processing circuit of claim 1, wherein at least one of the first integer number or the second integer number, in binary representation, has the least significant bit set to 1 and at least another bit set to 1 (Column 9, lines 2-15 and 60-68, where n=3 = 11binary, i.e. two bits are set to 1 including the least significant bit).
As per Claim 4, Arps discloses the signal processing circuit of claim 1, wherein at least one of the first integer number or the second integer number, in binary representation, has the least significant bit set to 1 and at least two other bits set to 1 (Column 4, lines 20-25, n may be any odd integer, wherein 7 = 111binary for example).
As per Claim 5, Arps discloses the signal processing circuit of claim 1, wherein at least one of the first integer number or the second integer number is 5 or 9 (Column 9, lines 60-64, n may be 5).
As per Claim 6, Arps discloses the signal processing circuit of claim 1, wherein at least one of the first integer number or the second integer number is 7, 11 or 13 (Column 4, lines 20-25, n may be any odd integer, such as 7 for example).
As per Claims 9-14, they recite method(s) comprising the same limitations as recited in Claims 1-6. Thus, Claims 9-14 are rejected under the same rationale as presented in the rejection(s) of Claims 1-6 above.
As per Claims 17-20, they recite medium(s) comprising the same limitations as recited in Claims 1-4. Thus, Claims 17-20 are rejected under the same rationale as presented in the rejection(s) of Claims 1-4 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-8 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Arps in view of Flautner et al. (US 9,448,875).
As per Claim 7, Arps does not disclose the signal processing circuit of claim 1, further comprising a sensor configured to: receive the input signal; and send the input signal to the sender circuit.
However, Flautner teaches using the error detection disclosed by Arps in a memory, wherein the memory comprises a sense amplifier configured to receive an input signal and send the signal to error checking circuitry and then through further processing stages of a pipeline (Abstract and Figures 1, 5, 14-16 and Column 6, line 50 through Column 7, line 19 and Column 11, lines 6-11 and Column 13, lines 30-67, a sense amplifier receives a signal and outputs the signal to a plurality of error checking and processing stages, wherein the error checking in a memory system may scale a signal by e.g. n=3 and use a modulo-3 operation to detect errors, as described in Arps).
It would have obvious to one of ordinary skill in the art prior to the effective filing of the claimed invention to combine the error detecting and correcting pipeline architecture taught by Flautner with the error detection of Arps because Flautner explicitly uses AN codes such as those described by Arps, Arps provides modulo circuitry which is required by Flautner (Arps, Column 8, lines 60-67 and Flautner, Column 13, lines 40-67), and because Flautner’s pipeline reduces the operating margins of integrated circuits while also reducing the overhead of error detection and error correction circuits and operation (Flautner, Column 2, lines 1-5).
As per Claim 8, Arps does not disclose the signal processing circuit of claim 1, further comprising a controller configured to: receive the output signal; and generate a command making use of the output signal.
However, Flautner teaches further comprising a controller configured to: receive the output signal; and generate a command making use of the output signal (Figures 14-17 and Column 14, lines 5-43, after testing for error detection i.e. via modulo operation with the output signal, control signal(s) are generated therefrom which e.g. command pipeline stages to stall).
It would have obvious to one of ordinary skill in the art prior to the effective filing of the claimed invention to combine the error detecting and correcting pipeline architecture taught by Flautner with the error detection of Arps because Flautner explicitly uses AN codes such as those described by Arps, Arps provides modulo circuitry which is required by Flautner (Arps, Column 8, lines 60-67 and Flautner, Column 13, lines 40-67), and because Flautner’s pipeline reduces the operating margins of integrated circuits while also reducing the overhead of error detection and error correction circuits and operation (Flautner, Column 2, lines 1-5).
As per Claims 15-16, they recite method(s) comprising the same limitations as recited in Claims 7-8. Thus, Claims 15-16 are rejected under the same rationale as presented in the rejection(s) of Claims 7-8 above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW SANDIFER whose telephone number is (571)270-5175. The examiner can normally be reached Mon-Fri 9:30am-6pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Trujillo can be reached at (571) 272-3677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MATTHEW D SANDIFER/Primary Examiner, Art Unit 2151