Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Roberts(US 2016/0380635).
Regarding claim 1, Roberts discloses a method, comprising: receiving an indication that a programmable device is to transition from a user mode to a configuration mode(Paragraphs 3, 33, The FPGA typically has a “configuration mode” and a separate “user mode” where the entire chip is either in an idle state waiting to be programmed, or the programmed chip is running. In particular, configuration logic 121 responds to instructions received via the TSVs 104 by reconfiguring the hardware in the configurable logic blocks 131-134 of programming region 122 or configurable logic blocks 135-138 of programming region 123 from an existing hardware configuration to a new hardware configuration); in response to receiving the indication, storing one or more states managed by the programmable device in the user mode(Paragraph 45, The context memories 113 and 114 are used to store the state information of the logic blocks in their respective programming regions 122 and 123. Prior to a reconfiguration of one of the programming regions 122 or 123, the context memory of the programming region to be reconfigured stores the state information of the logic blocks in the programming region so that the original configuration of the programming region can be restored later with the same context); maintaining the one or more states via proxy handling circuitry while the programmable device is in the configuration mode(Paragraph 45, The context memories 113 and 114 are used to store the state information of the logic blocks in their respective programming regions 122 and 123. Prior to a reconfiguration of one of the programming regions 122 or 123, the context memory of the programming region to be reconfigured stores the state information of the logic blocks in the programming region so that the original configuration of the programming region can be restored later with the same context); and in response to receiving an indication that the programmable device transitions from the configuration mode to the user mode, restoring the one or more states to the programmable device(Paragraph 46, When the programming region is reconfigured back to the first configuration, the context data for the first configuration is popped from the stack to restore the context for the first configuration).
Regarding claim 16, Roberts discloses a tangible, non-transitory, computer-readable medium comprising computer-readable instructions that, when executed, cause one or more processors of an electronic device to: receive an indication that a programmable device is to transition from a user mode to a configuration mode(Paragraphs 3, 33, The FPGA typically has a “configuration mode” and a separate “user mode” where the entire chip is either in an idle state waiting to be programmed, or the programmed chip is running. In particular, configuration logic 121 responds to instructions received via the TSVs 104 by reconfiguring the hardware in the configurable logic blocks 131-134 of programming region 122 or configurable logic blocks 135-138 of programming region 123 from an existing hardware configuration to a new hardware configuration); in response to receiving the indication, store one or more states managed by the programmable device in the user mode(Paragraph 45, The context memories 113 and 114 are used to store the state information of the logic blocks in their respective programming regions 122 and 123. Prior to a reconfiguration of one of the programming regions 122 or 123, the context memory of the programming region to be reconfigured stores the state information of the logic blocks in the programming region so that the original configuration of the programming region can be restored later with the same context); maintain the one or more states via proxy handling circuitry while the programmable device is in the configuration mode(Paragraph 45, The context memories 113 and 114 are used to store the state information of the logic blocks in their respective programming regions 122 and 123. Prior to a reconfiguration of one of the programming regions 122 or 123, the context memory of the programming region to be reconfigured stores the state information of the logic blocks in the programming region so that the original configuration of the programming region can be restored later with the same context); and in response to receiving an indication that the programmable device transitions from the configuration mode to the user mode, restore the one or more states to the programmable device(Paragraph 46, When the programming region is reconfigured back to the first configuration, the context data for the first configuration is popped from the stack to restore the context for the first configuration).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Roberts(US 2016/0380635) and Applicant’s admitted prior art(AAPA).
Regarding claim 2, Roberts discloses a method of claim 1, but does not specifically teach the one or more states comprise a memory mapped input/output (MMIO) state, a Peripheral Component Internet Express (PCIe) configuration state, or both. However, AAPA, in paragraph 4, discloses PCIe functions implemented by FPGA and Roberts, in paragraph 19, discloses memory 110 also includes context memory 113 and context memory 114, which are used to store state information associated with different configurations. Context memory 113 and context memory 114 store state information for programming regions 122 and 123, respectively. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art have the one or more states comprise a memory mapped input/output (MMIO) state, a Peripheral Component Internet Express (PCIe) configuration state, or both. The motivation would be that PCIE config states can be saved for later restoration.
Regarding claim 20, Roberts discloses tangible, non-transitory, computer-readable medium of claim 16, wherein the one or more states comprise a memory mapped input/output (MMIO) state, a Peripheral Component Internet Express (PCIe) configuration state, or both. However, AAPA, in paragraph 4, discloses PCIe functions implemented by FPGA and Roberts, in paragraph 19, discloses memory 110 also includes context memory 113 and context memory 114, which are used to store state information associated with different configurations. Context memory 113 and context memory 114 store state information for programming regions 122 and 123, respectively. Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art have the one or more states comprise a memory mapped input/output (MMIO) state, a Peripheral Component Internet Express (PCIe) configuration state, or both. The motivation would be that PCIE config states can be saved for later restoration.
Allowable Subject Matter
Claims 6-15 are allowed.
Claims 3-5 and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record fails to teach or suggest, either alone or in combination, proxy handling circuitry configured to service a plurality of transactions during reconfiguration of the programmable logic, the proxy handling circuitry comprising: a host interface controller configured to interface between the proxy handling circuitry and one or more hosts; and a proxy agent controller, the proxy agent controller configured to: receive an indication that the programmable logic is to transition from a user mode to a configuration mode; in response to receiving the indication, store one or more states managed by the programmable logic; and maintain the one or more states while the programmable logic is in the configuration mode, to enable servicing of host application transactions while the programmable logic is in the configuration mode, as recited in claim 6.
Conclusion
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/NIMESH G PATEL/Primary Examiner, Art Unit 2187