DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Claims 1-7 in the reply filed on 12 February 2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites elements that are “configurable” to achieve various functions. “Configurable” may be interpreted as “able to be configured”, which implies that an element may potentially be configured in a certain manner without explicitly requiring such configuring. For example, a programmable logic device is “configurable” to implement an adder, a multiplexer, or a state machine even though it is in an unprogrammed state. This language is therefore indefinite because it is unclear whether the features that follow the word “configurable” are required by the claim. The Examiner recommends that the claims be amended to indicate that the elements are configured to have those features, and therefore explicitly indicate that the claim is limited by them.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Langhammer et al., U.S. Patent Application Publication No. 2016/0358638.
Regarding claim 1, Langhammer discloses an integrated circuit comprising:
programmable logic circuitry [Fig. 8: memory array 131];
a register configurable to receive an output of the programmable logic circuitry [data register 702] and configurable to receive a first clock signal [CPa]; and
embedded function circuitry comprising one or more pipeline registers [Fig. 7: Reg 600; also Fig. 12A, para. 0069, 0070: “…the DSP blocks within a programmable integrated circuit are often configured to operate as a multiplier accumulator… As shown in FIG. 12A, multiplier accumulator 1100 may include… a first register 1106, and a second optional output register 1108...“], wherein the embedded function circuitry is configurable to receive a second clock signal [Fig. 7: DSP 120 receives a 2GHz clock], wherein the second clock signal has a higher frequency than the first clock signal [para. 0054: For example, pairs of 8-bit words can be read in parallel from a memory block 130 at 1 GHz while individual 8-bit words can be successively fed to a corresponding DSP block 120 at 2 GHz.” Fig. 3 and 6: system clock used to generate CPa and CPb, which are used to generate 2x clock].
Regarding claim 2, Langhammer teaches that the second clock signal is aligned and locked to the first clock signal [Fig. 6].
Regarding claim 3, Langhammer teaches that the programmable logic circuitry comprises FPGA circuitry [Fig. 1; para. 0075].
Regarding claim 4, Langhammer teaches that the embedded function circuitry comprises a DSP block [Fig. 7: DSP 120].
Regarding claim 5, Langhammer teaches that the second clock signal comprises clock pulses configurable to latch a signal of the embedded function circuitry to the one or more pipelined registers during each clock cycle of the first clock signal [Fig. 6: each rising edge of Clk1 coincides with a rising edge of 2x clock OUT; Fig. 7: Reg 600 operates on the 2GHz clock; para. 0070: “…accumulator 1100, adder 1104, and register 1106 may be operated at 2× data rate…”].
Regarding claim 6, Langhammer teaches that the clock pulses of the second clock signal repeat with each clock cycle of the first clock signal [Fig. 6: 2x clock OUT has two clock pulses for each pulse of Clk1].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Langhammer in view of Hoshaku, U.S. Patent Application Publication No. 2007/0283128.
Regarding claim 7, Langhammer discloses the IC of claim 1, and also discloses second embedded function circuitry comprising one or more pipeline registers and configured to receive a third clock signal [Fig. 1: plurality of DSP cores on PLD 100 with presumable the same structure as shown in Fig. 7 and 12]. Langhammer does not teach that the third clock signal comprises a phase-shifted version of the second clock signal.
Hoshaku discloses an IC with a plurality of cores, a given core receiving a phase-shifted version of a clock signal supplied to another core [Fig. 2, para. 0036: “Clock skew mediation section 112 performs control for arbitrarily shifting the clock phase relationship among a first signal processing group configured with first CPU core 101a (CPU #1)… a second signal processing group configured with second CPU core 101b (CPU #2)…”].
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to combine the teachings of Langhammer and Hoshaku by modifying Langhammer to supply, to a second core, a phase-shifted version of a clock signal provided to a first core, as taught by Hoshaku. Langhammer and Hoshaku both disclose ICs with a plurality of functional blocks that are supplied with respective clock signals. Hoshaku teaches that introducing an arbitrary phase shift between the respective clocks results in improved performance [para. 0063: “Therefore, asymmetric multiprocessor 100 has a configuration for adjusting the phase of the CPU clock signals, and thereby IR drops and reductions of the peak current can be minimized. By this means, it is possible to prevent malfunction of the processor and further reduce power consumption.”]. Therefore, it would have been obvious to one of ordinary skill in the art to apply the teachings of Hoshaku to Langhammer’s system based on the improvements suggested by Hoshaku.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ganusov et al., U.S. Patent Application Publication No. 2022/0334609, disclosed an IC with programmable logic circuitry [Fig. 3], a register to receive an output of the programmable logic circuitry and configurable to receive a first clock [Fig. 5: register 106] , embedded function circuitry [Fig. 3: DSP] comprising one or more pipeline registers receiving a second clock [Fig. 4].
Hazanchuk, U.S. Patent No. 8,977,885, discloses a PLD with a DSP block comprising a plurality of registers that operates at a multiple of the system clock rate [abstract, Fig. 2].
Sun et al., U.S. Patent No. 7,298,178, discloses an IC with a programmable logic block and a plurality of DSP blocks [Fig. 1; col. 5, lines 37-41].
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JI H BAE whose telephone number is (571)272-7181. The examiner can normally be reached Tuesday to Friday and every other Monday, 9 am to 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JI H BAE/Primary Examiner, Art Unit 2176 U.S. Patent and Trademark Office
Phone: 571-272-7181
Fax: 571-273-7181
ji.bae@uspto.gov