CTNF 17/956,844 CTNF 100392 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This Action is non-final and is in response to the claims filed 09/30/2022. Claims 1-20 are currently pending, of which claims 1-20 are currently rejected. Drawings Figures 1A, 6A and 6B should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. Paragraphs 0006, 0017, 0026 and 0027 of the specification describe figures 1A, 6A and 6B as conventional . See MPEP § 608.02(g). 06-22-07 AIA The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: Block 812 in Figure 8. The drawings are objected to as failing to comply with 37 CFR 1.84(o) because they lack suitable descriptive legends, such as Fig. 1B: blocks 116, 118, 120, and Fig. 8: blocks 811, 812, 814 . Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. 07-30-03-h AIA Claim Interpretation 07-30-03 AIA The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. 07-30-05 The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. The following limitations invoke 35 U.S.C. 112(f) because they use the words means and are not modified by sufficient structure, material, or acts for performing the claimed function: Claim 17: a plurality of means for receiving an electrical voltage or current (interpreted as input lines in the memory structure for receiving voltage signals, as disclosed in ¶0021 and Fig. 3); a plurality of means for outputting an altered electrical voltage or current (interpreted as output lines in the memory structure for outputting vector Y, as disclosed in ¶0024 and Fig. 3); a plurality of means for altering the electrical voltage or current (interpreted as the ohmic resistors or capacitive impedances as disclosed in ¶0022-0025 and Figs. 3 and 4), Claim 18: a sampling means for sampling a voltage of the analog electrical signal during each time period of the plurality of time periods (interpreted as one or more sample and hold circuits, as disclosed in ¶0031 and Fig. 8) Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 1-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites “A radiofrequency frontend device, comprising: a memory array, comprising: a plurality of input lines; … wherein the radiofrequency frontend device is configured to provide at each input line of the plurality of input lines a sampled voltage of an analog electric signal,” It is unclear how the radiofrequency frontend device can provide sampled voltages at each input line while the input line is inside the radiofrequency fronted device. Appropriate correction is required. For purposes of prior art rejection, it will be interpreted as the input lines being inside the radiofrequency fronted device. Claims 2-16 recite the same deficiency by reason of dependence. They are rejected for the same reasons as claim 1. Claim 11 recites the limitations “the in-phase signal” and “the quadrature signal”. There is insufficient antecedent basis for this limitation in the claim. Claim 14 recites the limitation “wherein the memory array is a phase-change random access memory, a memristor, resistive random access memory, or magnetic random access memory.” It is unclear if applicant intends the memory array to be one of the listed elements, or a group of these listed elements. Appropriate correction is required. For purposes of prior art rejection, it will be interpreted as only one. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-6 8-10, 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Ghosh et al. (U.S. Patent Application No.: US 20240005982 A1), hereinafter “Ghosh”, in view of Wang et al. (U.S. Patent No.: US 12050888 B2), hereinafter “Wang” . Regarding Claim 1 , Ghosh teaches: A radiofrequency frontend device (Fig. 1, e.g., radio architecture 100) , comprising: … wherein the radiofrequency frontend device is configured to provide [to a filter] a sampled voltage of an analog electric signal (¶0042, e.g., output of Front-End module circuitry 200 outputs RF signals (analog electric signal) to Radio IC; Fig. 3, e.g., shows filter 308 inside Radio IC Circuitry) , each sampled voltage corresponding to a voltage of the analog electric signal during a respective time period of a plurality of time periods (¶0046, e.g., quadrature passive mixers (inside mixer circuitry 302) may be driven by time-varying LO switching signals) ; … Ghosh does not teach: A radiofrequency frontend device, comprising: a memory array, comprising: a plurality of input lines; a plurality of output lines; a plurality of impedance devices, each impedance device of the plurality of impedance devices connecting an input line of the plurality of input lines to an output line of the plurality of output lines, wherein an impedance of each of the impedance devices represents a filter coefficient; wherein the radiofrequency frontend device is configured to provide at each input line of the plurality of input lines a sampled voltage of an analog electric signal, … when the memory array receives the sampled voltages, the memory array is configured to modify each of the sampled voltages by a respective impedance device of the plurality of impedance devices and sum the modified sampled voltages. However, Wang teaches: A … device , comprising: a memory array (Fig. 3, e.g., shows in-memory computing apparatus 30) , comprising: a plurality of input lines (Fig. 3, e.g., shows input lines) ; a plurality of output lines (Fig. 3, e.g., shows output lines) ; a plurality of impedance devices, each impedance device of the plurality of impedance devices connecting an input line of the plurality of input lines to an output line of the plurality of output lines (Fig. 3, e.g., shows array using memristors (plurality of impedance devices) connecting input lines with output lines) , wherein an impedance of each of the impedance devices represents a filter coefficient (Column 1, Lines 41-45, e.g., resistance values of the memristor represent weight values (filter coefficient)) ; wherein the … device is configured to provide at each input line of the plurality of input lines a … voltage of an analog electric signal (Column 1, Lines 41-45, e.g., memristors receive analog signals with different input voltages), … when the memory array receives the sampled voltages, the memory array is configured to modify each of the sampled voltages by a respective impedance device of the plurality of impedance devices and sum the modified sampled voltages (Column 1, Lines 41-45, e.g., resistance values of the memristor represent weight values (filter coefficient), and are multiplied accumulated by input voltages) . Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to substitute the filter 308 taught by Ghosh with the in-memory computing apparatus 30 taught by Wang. Wang discloses in Column 7 Lines 13-15 "such that the trained neural network 80 can be used to filter the noise from any speech signal input to the neural network 80 in practical implementation". One would have been motivated to perform this substitution because both references disclose filtering of noise analog signals, and Wang enhances the model of Ghosh by converting noisy signals into enhanced speech signals. See Wang: Fig. 7 and Column 6 Line 55 - Column 7 Line 15. Regarding Claim 2 , Ghosh in view of Wang teach: The radiofrequency frontend device of claim 1, further comprising a sampler, configured to sample a voltage of the analog electrical signal during each time period of the plurality of time periods and to connect the sampled voltage to a respective input line of the plurality of input lines (Ghosh: Fig. 3, e.g., shows mixer circuitry 302 and synthesizer 304 (sampler); ¶0046, e.g., quadrature passive mixers (inside mixer circuitry 302) may be driven by time-varying LO switching signals by synthesizer circuitry 304; Wang: Column 1, Lines 41-45, e.g., memristors receive analog signals with different input voltages (sampled voltage)) . The motivation to combine provided with respect to claim 1 applies equally to claim 2. Regarding Claim 3 , Ghosh in view of Wang teach: The radiofrequency frontend device of claim 2, further comprising an antenna port, configured to receive the analog electrical signal (Ghosh: Fig. 1, e.g., shows antennas 101; ¶0023) ; wherein the analog electrical signal represents a radiofrequency transmission received on one or more antennas (Ghosh: ¶0023, e.g., antennas receive RF signals (analog electrical signals)) , and wherein the sampler is electrically conductively connected to the antenna port (Ghosh: Fig. 1, e.g., Antenna 101 is connected to Radio IC Circuitry WLAN; Fig. 3, e.g., Radio IC Circuitry contains synthesizer 304 (sampler)) . Regarding Claim 4 , Ghosh in view of Wang teach: The radiofrequency frontend device of claim 1, further comprising an analog to digital converter, configured to convert the summed, modified sampled voltages to a digital signal (Ghosh: Fig. 4, e.g., Analog to Digital converter 410 receives Analog result from filter 307, and converts it to digital; ¶0054; Wang: Column 1, Lines 41-45, e.g., in-memory computing apparatus performs MAC operations (summed voltages)) . The motivation to combine provided with respect to claim 1 applies equally to claim 4. Regarding Claim 5 , Ghosh in view of Wang teach: The radiofrequency frontend device of claim 1, wherein the plurality of impedance devices are a plurality of ohmic resistors (Wang: Fig. 3, e.g., memristors are used in the in-memory computing apparatus) . The motivation to combine provided with respect to claim 1 applies equally to claim 5. Regarding Claim 6 , Ghosh in view of Wang teach: The radiofrequency frontend device of claim 1, wherein the plurality of impedance devices are a plurality of variable ohmic resistors (Wang: Fig. 3, e.g., memristors, which use dynamic resistance, are used in the in-memory computing apparatus) . The motivation to combine provided with respect to claim 1 applies equally to claim 6. Regarding Claim 8 , Ghosh in view of Wang teach: The radiofrequency frontend device of claim 1, further comprising an in-phase and quadrature demodulator, configured to generate an in-phase signal and a quadrature signal from the analog electrical signal (Ghosh: ¶0045, e.g., Mixer circuitry 302 comprises quadrature passive mixers for generating I and Q signals) . The motivation to combine provided with respect to claim 1 applies equally to claim 8. Regarding Claim 9 , Ghosh in view of Wang teach: The radiofrequency frontend device of claim 8, wherein the plurality of input lines comprises a first plurality of input lines and a second plurality of input lines (Wang: Fig. 3, e.g., shows plurality of input lines) ; and wherein the first plurality of input lines is configured to receive sampled voltages corresponding to the in-phase signal and wherein the second plurality of input lines is configured to receive sampled voltages corresponding to the quadrature signal (Wang: Fig. 3, e.g., shows plurality of input lines; Ghosh: ¶0048, e.g., filter receives I and Q baseband output signals; Combination would cause for Wang’s input lines to receive in-phase and quadrature signals) . The motivation to combine provided with respect to claim 1 applies equally to claim 9. Regarding Claim 10 , Ghosh in view of Wang teach: The radiofrequency frontend device of claim 8, wherein the plurality of output lines comprises a first plurality of output lines and a second plurality of output lines (Wang: Fig. 3, e.g., shows plurality of output lines) ; and wherein each impedance device of the plurality of impedance devices connected to the first plurality of output lines corresponds to a filter coefficient for an in-phase signal, a filter coefficient for a quadrature signal, or an inverse filter coefficient for a quadrature signal (Wang: Column 1, Lines 41-45, e.g., resistance values of the memristor represent weight values (filter coefficient); Ghosh: ¶0048, e.g., filter receives I and Q baseband output signals; Combination would cause for Ghosh’s I and Q signals to be connected to Wang’s in-memory computing apparatus, including memristors connected to output lines) . The motivation to combine provided with respect to claim 1 applies equally to claim 10. Regarding Claim 13 , Ghosh in view of Wang teach: The radiofrequency frontend device of claim 1, wherein the memory array is configured to store bits in one or more resistance levels (Wang: Column 1, Lines 41-45, e.g., resistance values of the memristor represent weight values (bits)) . The motivation to combine provided with respect to claim 1 applies equally to claim 13. Regarding Claim 14 , Ghosh in view of Wang teach: The radiofrequency frontend device of claim 13, wherein the memory array is a phase-change random access memory, a memristor, resistive random access memory, or magnetic random access memory (Wang: Column 1, Lines 41-45, e.g., array uses memristors) . The motivation to combine provided with respect to claim 1 applies equally to claim 14. With regards to Claims 17-18 , this is a means plus function version of the claimed radiofrequency frontend device above (claims 1-2 respectively), wherein all claim limitations also have been addressed and/or covered in cited areas. Thus, accordingly, this claim is rejected for at least the same reasons therein. Regarding Claims 19-20 , they are method claim practiced by the apparatus of claims 1-2. It is rejected for the same reasons as claims 1-2 . 07-21-aia AIA Claim s 7 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Ghosh in view of Wang, further in view of Kai-Uwe Demasius in NPL: “Energy-efficient memcapacitor devices for neuromorphic computing” (www.nature.com/articles/s41928-021-00649-y), hereinafter “Demasius” . Regarding Claim 7 , Ghosh in view of Wang teach: The radiofrequency frontend device of claim 1, wherein the plurality of impedance devices are a plurality of [memristors] (Wang: Column 1, Lines 41-45, e.g., array uses memristors) . Ghosh in view of Wang do not teach: The radiofrequency frontend device of claim 1, wherein the plurality of impedance devices are a plurality of variable capacitors. However, in the same field of endeavor, Demasius teaches how memory arrays could use memcapacitors instead of memristors. Demasius explains “Memcapacitive devices are similar to memristive devices but are based on a capacitive principle, and could potentially offer a lower static power consumption than memristive devices … We fabricate devices on the scale of tens of micrometres and use them to create a crossbar array architecture” (Page 748, First Column, Second and Third paragraph) Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to substitute the memristors taught by Ghosh in view of Wang with the memcapacitors taught by Demasius. One would have been motivated to combine these references because both references disclose memory arrays, and Demasius enhances the model of Ghosh in view of Wang because “memcapacitor devices based on charge shielding that can offer high dynamic range and low power operation.” (Demasius: Page 748, First Column, Third paragraph) Regarding Claim 15 , Ghosh in view of Wang in view of Demasius teach: The radiofrequency frontend device of claim 1, wherein the memory array is configured to store bits in one or more capacitance levels (Demasius: Abstract, e.g., array ensures high precision (6-8 bits), therefore array stores bits) . The motivation to combine provided with respect to claim 7 applies equally to claim 15. Regarding Claim 16 , Ghosh in view of Wang in view of Demasius teach: The radiofrequency frontend device of claim 15, wherein the memory array is a ferroelectric random access memory or an Adamantine embedded dynamic random access memory (Wang: Column 5, Lines 5-6, e.g., memory array is a random access memory; Demasius: Page 750, Second Column, Last paragraph, e.g., memory uses ferroelectric switching) . The motivation to combine provided with respect to claim 7 applies equally to claim 16 . 07-21-aia AIA Claim s 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Ghosh in view of Wang, further in view of Bayat et al. (U.S. Patent No.: US 10891080 B1), hereinafter “Bayat” . Regarding Claim 11 , Ghosh in view of Wang teach: The radiofrequency frontend device of claim 2, … wherein the [sampler is] configured to sample electrical charges corresponding to the in-phase signal, and wherein the [sampler is] configured to sample electrical charges corresponding to the quadrature signal (Ghosh: ¶0048, e.g., filter receives I and Q baseband output signals; Fig. 3, e.g., shows mixer 302 and synthesizer 304 (sampler)) . Ghosh in view of Wang do not teach: wherein the sampler comprises a first plurality of sampling circuits and a second plurality of sampling circuits; wherein the first plurality of sampling circuits are configured to sample electrical charges corresponding to the in-phase signal , and wherein the second plurality of sampling circuits are configured to sample electrical charges corresponding to the quadrature signal . However, in the same field of endeavor, Bayat teaches using sample and hold circuits in every input line of the memory array. Bayat explains “In some embodiments, the buffers 110 may be omitted and the capacitors in the SH circuits 108 may provide the analog signals directly to the corresponding rows of devices in the memory array 112.” See Bayat: Column 5 Lines 40-43 and Figure 1. Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to modify the mixer and synthesizer as taught by Ghosh in view of Wang to include the sample and hold circuits in each input line as taught by Bayat. One would have been motivated to combine these references because both references disclose memory arrays, and Bayat enhances the model of Ghosh in view of Wang because “the SH circuits 108 may be used to store the inputs of the memory array 112” (Bayat: Column 5 Lines 19-20). Combination would cause for the input lines of the in-memory computing apparatus, as taught by Wang, to include the sample and hold circuits in each input, as taught by Bayat, and to receive in-phase and quadrature signals, as taught by Ghosh. Regarding Claim 12 , Ghosh in view of Wang in view of Bayat teach: The radiofrequency frontend device of claim 2, wherein the sampler comprises a plurality of sample and hold circuits (Bayat: Column 5 Lines 40-43 and Figure 1) . The motivation to combine provided with respect to claim 11 applies equally to claim 12. Prior Art Made of Record NPL: “Comparison of Downconversion Techniques for Software Radio” (www.ee.ucl.ac.uk/lcs/previous/LCS2000/lcs050.pdf) – teaches using a sample and hold circuit before a filter. See Section 3. Bandpass Sampling US 20220351032 A1 – teaches CIM array module using sample and hold circuits. See Figs. 3A and 3B, and corresponding description. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CARLOS H DE LA GARZA whose telephone number is (571)272-0474. The examiner can normally be reached Monday-Friday 9:30AM-6PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Caldwell can be reached at (571) 272-3702. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.H.D./ Carlos H. De La GarzaExaminer, Art Unit 2182 (571)272-0474 /EMILY E LAROCQUE/Primary Examiner, Art Unit 2182 Application/Control Number: 17/956,844 Page 2 Art Unit: 2182 Application/Control Number: 17/956,844 Page 3 Art Unit: 2182 Application/Control Number: 17/956,844 Page 4 Art Unit: 2182 Application/Control Number: 17/956,844 Page 5 Art Unit: 2182 Application/Control Number: 17/956,844 Page 6 Art Unit: 2182 Application/Control Number: 17/956,844 Page 7 Art Unit: 2182 Application/Control Number: 17/956,844 Page 8 Art Unit: 2182 Application/Control Number: 17/956,844 Page 9 Art Unit: 2182 Application/Control Number: 17/956,844 Page 10 Art Unit: 2182 Application/Control Number: 17/956,844 Page 11 Art Unit: 2182 Application/Control Number: 17/956,844 Page 12 Art Unit: 2182 Application/Control Number: 17/956,844 Page 13 Art Unit: 2182 Application/Control Number: 17/956,844 Page 14 Art Unit: 2182
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