DETAILED ACTION
This office action is responsive to the Applicant’s reply filed on 03/02/2026.
Response to Arguments
Applicant’s arguments, filed on 03/02/2026, with respect to claim objections have been fully considered and are persuasive. The objections of claims 16-20 have been withdrawn.
Applicant's arguments, filed on 03/02/2026, with respect to claim rejections have been fully considered but they are not persuasive.
(1), Applicant’s argument: “Dhanasekaran’s architecture is structurally and functionally distinct from Applicant’s claimed open-loop, transmitter-side digital crosstalk cancellation. …… Dhanasekaran’s closed-loop feedback arrangement does not disclose Applicant’s claimed ‘first conductive node to generate a first crosstalk cancelled signal by combining the first analog output signal with the analog cancellation signal’ as recited in claim 10.”
Examiner’s response: Applicant’s claim 10 recites a transmitter-side digital cross-talk cancellation. Dhanasekaran also teaches a crosstalk cancellation system 200 on a transmitter that cancels crosstalk between two digital stereo signals (see Dhanasekaran at Fig. 2 and paragraph 0041). Applicant claim 10 does not mention that the crosstalk cancellation system is open-loop. Since Dhanasekaran’s crosstalk cancellation system 200 does not receive any feedback from a receiver, it could be considered an open-loop system.
(2), Applicant’s argument: “Detector 220 does not combine the analog output signal with an analog cancellation signal to produce a transmitted crosstalk-canceled signal. In contrast, Applicant's claimed ‘first conductive node’ includes a physical circuit node at the transmitter output where the analog output signal from the transmission amplifier and the analog cancellation signal from the crosstalk cancellation circuit are superimposed to produce the crosstalk-canceled signal that is then conveyed to the transmission channel.
Examiner’s response: Dhanasekaran’s detector 220 combines the analog signal VAR and the analog signal VAL in order for the crosstalk canceller 206 to generate a crosstalk cancelling signal DRXC (see Dhanasekaran at Fig. 2 and paragraph 0047). In claim 10, Applicant's ‘first conductive node’ generates a “first crosstalk canceled signal”. However, claim 10 does not recite that the “first crosstalk canceled signal” is “superimposed” and “conveyed to the transmission channel”.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 10 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Dhanasekaran (US 2023/0232155 A1).
Consider claim 10:
Dhanasekaran discloses a system (see Fig. 2 and paragraph 0041, where Dhanasekaran describes a crosstalk cancellation system 200 used in a stereo audio transmission) comprising:
a transmitter multiple integrated circuit (IC) chiplet package including a system on a chip (SOC), the SOC including a processor and a transmitter chiplet (see Fig. 6 and paragraphs 0070-0071, where Dhanasekaran describes that the crosstalk cancellation system includes a transmitter 660, an integrated circuit (IC) 610, which may be implemented as a system on chip (SCO), the SCO 610 may include processing core 615 coupled to a processor 625), the transmitter chiplet including:
a transmission amplifier (see Fig. 2 and paragraph 0042, where Dhanasekaran describes that the crosstalk cancellation system 200 includes an amplifier 212-R) to receive a first digital signal and generate a first analog output signal (see Fig. 2 and paragraph 0046, where Dhanasekaran describes that the amplifier 212-R receives a digital audio signal DR2 and generates an analog signal VAR),
the first digital signal including a crosstalk signal caused by a second digital signal (see Fig. 2 and paragraph 0044, where Dhanasekaran describes that a crosstalk canceller 206 is configured to cancel crosstalk between the digital audio signal DR2 and a second digital audio signal DL2);
a crosstalk cancellation circuit (see Fig. 2 and paragraph 0044, where Dhanasekaran describes that the crosstalk cancellation system 200 includes a crosstalk canceller 206) to receive the second digital signal and generate an analog cancellation signal (see Fig. 2 and paragraph 0047, where Dhanasekaran describes that the crosstalk canceller 206 receives the second digital audio signal DL2 and generates an analog signal VAL which will be used to cancel crosstalk),
the analog cancellation signal configured to cancel the crosstalk signal within the first digital signal without requiring a crosstalk cancellation capacitor (see Fig. 2 and paragraphs 0046-0047, where Dhanasekaran describes that the analog signal VAL is fed back to the crosstalk canceller 206 to generate a crosstalk cancelling signal DRXC to cancel the crosstalk signal within the digital audio signal DR2 by using a summer 208-R); and
a first conductive node to generate a first crosstalk canceled signal by combining the first analog output signal with the analog cancellation signal (see Fig. 2 and paragraph 0047, where Dhanasekaran describes that a detector 220 is configured to generate a signal ZS which is provided to the crosstalk canceller 206 to generate the crosstalk cancelling signal DRXC , and the detector 220 combines the analog signal VAR and the analog signal VAL).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Dhanasekaran (US 2023/0232155 A1) in view of Rachmady et al. (US 2020/0098921 A1).
Consider claim 1:
Dhanasekaran discloses a system (see Fig. 2 and paragraph 0041, where Dhanasekaran describes a crosstalk cancellation system 200 used in a stereo audio transmission) comprising:
a transmission amplifier (see Fig. 2 and paragraph 0042, where Dhanasekaran describes that the crosstalk cancellation system 200 includes an amplifier 212-R),
the transmission amplifier to receive a first digital signal and generate a first analog output signal (see Fig. 2 and paragraph 0046, where Dhanasekaran describes that the amplifier 212-R receives a digital audio signal DR2 and generates an analog signal VAR),
the first digital signal including a crosstalk signal caused by a second digital signal (see Fig. 2 and paragraph 0044, where Dhanasekaran describes that a crosstalk canceller 206 is configured to cancel crosstalk between the digital audio signal DR2 and a second digital audio signal DL2);
a crosstalk cancellation circuit (see Fig. 2 and paragraph 0044, where Dhanasekaran describes that the crosstalk cancellation system 200 includes a crosstalk canceller 206),
the crosstalk cancellation circuit to receive the second digital signal and generate an analog cancellation signal (see Fig. 2 and paragraph 0047, where Dhanasekaran describes that the crosstalk canceller 206 receives the second digital audio signal DL2 and generates an analog signal VAL which will be used to cancel crosstalk),
the analog cancellation signal configured to cancel the crosstalk signal within the first digital signal without requiring a crosstalk cancellation capacitor (see Fig. 2 and paragraphs 0046-0047, where Dhanasekaran describes that the analog signal VAL is fed back to the crosstalk canceller 206 to generate a crosstalk cancelling signal DRXC to cancel the crosstalk signal within the digital audio signal DR2 by using a summer 208-R); and
a first conductive node to generate a first crosstalk canceled signal by combining the first analog output signal with the analog cancellation signal (see Fig. 2 and paragraph 0047, where Dhanasekaran describes that a detector 220 is configured to generate a signal ZS which is provided to the crosstalk canceller 206 to generate the crosstalk cancelling signal DRXC , and the detector 220 combines the analog signal VAR and the analog signal VAL).
Dhanasekaran does not specifically disclose: the above components are disposed on a metal layer of a multiple metal layer circuit board.
Rachmady teaches: components are disposed on a metal layer of a multiple metal layer circuit board (see Fig. 4 and paragraph 0071, where Rachmady describes components on a layer of a circuit board 402 which may include multiple metal layers).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include that the above components are disposed on a metal layer of a multiple metal layer circuit board, as taught by Rachmady to modify the method of Dhanasekaran in order to form a desired circuit pattern, as discussed by Rachmady (see paragraph 0071).
Consider claim 16:
Dhanasekaran discloses a system (see Fig. 2 and paragraph 0041, where Dhanasekaran describes a crosstalk cancellation system 200 used in a stereo audio transmission) comprising:
a transmission amplifier branch circuit (see Fig. 2 and paragraph 0042, where Dhanasekaran describes that the crosstalk cancellation system 200 includes an amplifier 212-R) to generate an analog output signal based on a first digital signal (see Fig. 2 and paragraph 0046, where Dhanasekaran describes that the amplifier 212-R receives a digital audio signal DR2 and generates an analog signal VAR),
a crosstalk cancellation branch circuit (see Fig. 2 and paragraph 0044, where Dhanasekaran describes that the crosstalk cancellation system 200 includes a crosstalk canceller 206) to generate an analog cancellation signal (see Fig. 2 and paragraph 0047, where Dhanasekaran describes that the crosstalk canceller 206 receives the second digital audio signal DL2 and generates an analog signal VAL which will be used to cancel crosstalk),
the analog cancellation signal configured to cancel the crosstalk signal within the first digital signal without requiring a crosstalk cancellation capacitor (see Fig. 2 and paragraphs 0046-0047, where Dhanasekaran describes that the analog signal VAL is fed back to the crosstalk canceller 206 to generate a crosstalk cancelling signal DRXC to cancel the crosstalk signal within the digital audio signal DR2 by using a summer 208-R); and
a conductive cancellation node coupled to the CMOS transmission amplifier branch circuit and to the CMOS transmission amplifier branch circuit, the conductive cancellation node to generate a first crosstalk canceled signal by combining the first analog output signal with the analog cancellation signal (see Fig. 2 and paragraph 0047, where Dhanasekaran describes that a detector 220 is configured to generate a signal ZS which is provided to the crosstalk canceller 206 to generate the crosstalk cancelling signal DRXC , and the detector 220 combines the analog signal VAR and the analog signal VAL).
Dhanasekaran does not specifically disclose: the above circuit is CMOS circuit.
Rachmady teaches: CMOS circuit (see Fig. 4 and paragraph 0070, where Rachmady describes a circuit board which may include a number of CMOS components).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include that the above circuit is CMOS circuit, as taught by Rachmady to modify the method of Dhanasekaran in order to form a desired circuit pattern, as discussed by Rachmady (see paragraph 0071).
Consider claim 2:
Dhanasekaran in view of Rachmady discloses the system of claim 1 above. Dhanasekaran discloses: the crosstalk cancellation circuit further to receive the first digital signal, wherein the analog cancellation signal is generated based on the first digital signal and the second digital signal (see Fig. 2 and paragraph 0044, where Dhanasekaran describes that the crosstalk canceller 206 receives the first digital audio signal DR2 and the second digital audio signal DL2; see Fig. 2 and paragraph 0047, where Dhanasekaran describes that the analog signal VAL is generated based on the first digital audio signal DR2 and the second digital audio signal DL2).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Dhanasekaran (US 2023/0232155 A1) in view of Rachmady et al. (US 2020/0098921 A1), as applied to claim 1 above, and further in view of Lin (US 6,034,414).
Consider claim 8:
Dhanasekaran in view of Rachmady discloses the system of claim 1 above. Dhanasekaran does not specifically disclose: a first serial resistor coupled to the first conductive node; and a conductive pad to convey the first crosstalk canceled signal from the first serial resistor to a first transmission channel.
Lin teaches: a first serial resistor coupled to a first conductive node, and a conductive pad to convey a signal from the first serial resistor to a first transmission channel (see Fig. 2b and col. 4, lines 65-67, where Lin describes a circuit which includes two conductive pads 60 and 62 to connect with two ends of two resistors 48a and 48b in serial).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: a first serial resistor coupled to the first conductive node; and a conductive pad to convey the first crosstalk canceled signal from the first serial resistor to a first transmission channel, as taught by Lin to modify the method of Dhanasekaran in order to make adjustment in real time, as discussed by Lin (see col. 2, lines 20-25).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Dhanasekaran (US 2023/0232155 A1) in view of Rachmady et al. (US 2020/0098921 A1), as applied to claim 1 above, and further in view of Lin et al. (US 2013/0058175 A1).
Consider claim 9:
Dhanasekaran in view of Rachmady discloses the system of claim 1 above. Dhanasekaran discloses a memory transmitter (see Fig. 2 and paragraph 0043, where Dhanasekaran describes that the crosstalk cancellation system 200 is a transmitter that includes a processor and a memory device).
Dhanasekaran does not specifically disclose: a double data rate (DDR) memory transmitter.
Lin teaches: a double data rate (DDR) memory transmitter (see Fig. 11 and paragraph 0024, where Lin describes a double data rate unit of a data transmitter of a DDR PSRAM; see paragraph 0008, where Lin describes that the DDR PSRAM includes a memory).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: a double data rate (DDR) memory transmitter, as taught by Lin to modify the method of Dhanasekaran in order to double the data rate, as discussed by Lin (see paragraph 0007).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Dhanasekaran (US 2023/0232155 A1), as applied to claim 10 above, and further in view of Anim-Appiah (US 9,781,254 B1).
Consider claim 11:
Dhanasekaran discloses the system of claim 10 above. Dhanasekaran discloses a memory chiplet (see paragraph 0043, where Dhanasekaran describes that a memory is connected to the processor).
Dhanasekaran does not specifically disclose: a memory chiplet to receive the first crosstalk cancelled signal from the transmitter chiplet.
Anim-Appiah teaches: a memory chiplet to receive a first crosstalk cancelled signal from a transmitter chiplet (see Fig. 1 and col. 15, lines 54-58, where Anim-Appiah describes that crosstalk cancelled samples are converted to data symbols which are stored in a memory 128).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: a memory chiplet to receive the first crosstalk cancelled signal from the transmitter chiplet, as taught by Anim-Appiah to modify the method of Dhanasekaran in order to cancel noise from a continuously sampled signal, as discussed by Anim-Appiah (see col. 15, lines 59-61).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Dhanasekaran (US 2023/0232155 A1), as applied to claim 10 above, and further in view of Rachmady et al. (US 2020/0098921 A1).
Consider claim 12:
Dhanasekaran discloses the system of claim 10 above. Dhanasekaran does not specifically disclose: the transmitter chiplet disposed within a multiple metal layer circuit board.
Rachmady teaches: a transmitter chiplet disposed within a multiple metal layer circuit board (see Fig. 4 and paragraph 0071, where Rachmady describes components on a layer of a circuit board 402 which may include multiple metal layers).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the transmitter chiplet disposed within a multiple metal layer circuit board, as taught by Rachmady to modify the method of Dhanasekaran in order to form a desired circuit pattern, as discussed by Rachmady (see paragraph 0071).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Dhanasekaran (US 2023/0232155 A1), as applied to claim 10 above, and further in view of Lin et al. (US 2013/0058175 A1).
Consider claim 13:
Dhanasekaran discloses the system of claim 10 above. Dhanasekaran does not specifically disclose: the transmitter chiplet included within a double data rate (DDR) memory transmitter.
Lin teaches: a double data rate (DDR) memory transmitter (see Fig. 11 and paragraph 0024, where Lin describes a double data rate unit of a data transmitter of a DDR PSRAM; see paragraph 0008, where Lin describes that the DDR PSRAM includes a memory).
Therefore, it would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to include: the transmitter chiplet included within a double data rate (DDR) memory transmitter, as taught by Lin to modify the method of Dhanasekaran in order to double the data rate, as discussed by Lin (see paragraph 0007).
Allowable Subject Matter
Claims 3-7, 14-15 and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LIHONG YU whose telephone number is (571)270-5147. The examiner can normally be reached 10:00 am-6:00 pm EST Monday-Friday.
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/LIHONG YU/Primary Examiner, Art Unit 2631